1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek DWMAC glue layer controller
8
9maintainers:
10  - Biao Huang <biao.huang@mediatek.com>
11
12description:
13  This file documents platform glue layer for stmmac.
14
15# We need a select here so we don't match all nodes with 'snps,dwmac'
16select:
17  properties:
18    compatible:
19      contains:
20        enum:
21          - mediatek,mt2712-gmac
22          - mediatek,mt8188-gmac
23          - mediatek,mt8195-gmac
24  required:
25    - compatible
26
27allOf:
28  - $ref: snps,dwmac.yaml#
29
30properties:
31  compatible:
32    oneOf:
33      - items:
34          - enum:
35              - mediatek,mt2712-gmac
36          - const: snps,dwmac-4.20a
37      - items:
38          - enum:
39              - mediatek,mt8195-gmac
40          - const: snps,dwmac-5.10a
41      - items:
42          - enum:
43              - mediatek,mt8188-gmac
44          - const: mediatek,mt8195-gmac
45          - const: snps,dwmac-5.10a
46
47  clocks:
48    minItems: 5
49    items:
50      - description: AXI clock
51      - description: APB clock
52      - description: MAC Main clock
53      - description: PTP clock
54      - description: RMII reference clock provided by MAC
55      - description: MAC clock gate
56
57  clock-names:
58    minItems: 5
59    items:
60      - const: axi
61      - const: apb
62      - const: mac_main
63      - const: ptp_ref
64      - const: rmii_internal
65      - const: mac_cg
66
67  interrupts:
68    maxItems: 1
69
70  interrupt-names:
71    const: macirq
72
73  power-domains:
74    maxItems: 1
75
76  mediatek,pericfg:
77    $ref: /schemas/types.yaml#/definitions/phandle
78    description:
79      The phandle to the syscon node that control ethernet
80      interface and timing delay.
81
82  mediatek,tx-delay-ps:
83    description:
84      The internal TX clock delay (provided by this driver) in nanoseconds.
85      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
86      or will round down. Range 0~31*170.
87      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
88      or will round down. Range 0~31*550.
89      For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
90      or will round down. Range 0~31*290.
91
92  mediatek,rx-delay-ps:
93    description:
94      The internal RX clock delay (provided by this driver) in nanoseconds.
95      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
96      or will round down. Range 0~31*170.
97      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
98      or will round down. Range 0~31*550.
99      For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
100      of 290, or will round down. Range 0~31*290.
101
102  mediatek,rmii-rxc:
103    type: boolean
104    description:
105      If present, indicates that the RMII reference clock, which is from external
106      PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
107
108  mediatek,rmii-clk-from-mac:
109    type: boolean
110    description:
111      If present, indicates that MAC provides the RMII reference clock, which
112      outputs to TXC pin only.
113
114  mediatek,txc-inverse:
115    type: boolean
116    description:
117      If present, indicates that
118      1. tx clock will be inversed in MII/RGMII case,
119      2. tx clock inside MAC will be inversed relative to reference clock
120         which is from external PHYs in RMII case, and it rarely happen.
121      3. the reference clock, which outputs to TXC pin will be inversed in RMII case
122         when the reference clock is from MAC.
123
124  mediatek,rxc-inverse:
125    type: boolean
126    description:
127      If present, indicates that
128      1. rx clock will be inversed in MII/RGMII case.
129      2. reference clock will be inversed when arrived at MAC in RMII case, when
130         the reference clock is from external PHYs.
131      3. the inside clock, which be sent to MAC, will be inversed in RMII case when
132         the reference clock is from MAC.
133
134  mediatek,mac-wol:
135    type: boolean
136    description:
137      If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
138      Otherwise, PHY WOL is preferred.
139
140required:
141  - compatible
142  - reg
143  - interrupts
144  - interrupt-names
145  - clocks
146  - clock-names
147  - phy-mode
148  - mediatek,pericfg
149
150unevaluatedProperties: false
151
152examples:
153  - |
154    #include <dt-bindings/clock/mt2712-clk.h>
155    #include <dt-bindings/gpio/gpio.h>
156    #include <dt-bindings/interrupt-controller/arm-gic.h>
157    #include <dt-bindings/interrupt-controller/irq.h>
158    #include <dt-bindings/power/mt2712-power.h>
159
160    eth: ethernet@1101c000 {
161        compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
162        reg = <0x1101c000 0x1300>;
163        interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
164        interrupt-names = "macirq";
165        phy-mode = "rgmii-rxid";
166        mac-address = [00 55 7b b5 7d f7];
167        clock-names = "axi",
168                      "apb",
169                      "mac_main",
170                      "ptp_ref",
171                      "rmii_internal";
172        clocks = <&pericfg CLK_PERI_GMAC>,
173                 <&pericfg CLK_PERI_GMAC_PCLK>,
174                 <&topckgen CLK_TOP_ETHER_125M_SEL>,
175                 <&topckgen CLK_TOP_ETHER_50M_SEL>,
176                 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
177        assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
178                          <&topckgen CLK_TOP_ETHER_50M_SEL>,
179                          <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
180        assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
181                                 <&topckgen CLK_TOP_APLL1_D3>,
182                                 <&topckgen CLK_TOP_ETHERPLL_50M>;
183        power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
184        mediatek,pericfg = <&pericfg>;
185        mediatek,tx-delay-ps = <1530>;
186        snps,txpbl = <1>;
187        snps,rxpbl = <1>;
188        snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
189        snps,reset-delays-us = <0 10000 10000>;
190    };
191