1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm External Bus Interface 2 (EBI2)
8
9description: |
10  The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
11  external memory (such as NAND or other memory-mapped peripherals) whereas
12  LCDC handles LCD displays.
13
14  As it says it connects devices to an external bus interface, meaning address
15  lines (up to 9 address lines so can only address 1KiB external memory space),
16  data lines (16 bits), OE (output enable), ADV (address valid, used on some
17  NOR flash memories), WE (write enable). This on top of 6 different chip selects
18  (CS0 thru CS5) so that in theory 6 different devices can be connected.
19
20  Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
21  and the bus can only come out on these pins, however if some of the pins are
22  unused they can be left unconnected or remuxed to be used as GPIO or in some
23  cases other orthogonal functions as well.
24
25  Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
26
27  The chip selects have the following memory range assignments. This region of
28  memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
29
30  Chip Select                     Physical address base
31  CS0 GPIO134                     0x1a800000-0x1b000000 (8MB)
32  CS1 GPIO39 (A) / GPIO123 (B)    0x1b000000-0x1b800000 (8MB)
33  CS2 GPIO40 (A) / GPIO124 (B)    0x1b800000-0x1c000000 (8MB)
34  CS3 GPIO133                     0x1d000000-0x25000000 (128 MB)
35  CS4 GPIO132                     0x1c800000-0x1d000000 (8MB)
36  CS5 GPIO131                     0x1c000000-0x1c800000 (8MB)
37
38  The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
39  August 6, 2012 contains some incomplete documentation of the EBI2.
40
41  FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
42  We have not been able to figure out which bit fields these correspond to
43  in the hardware, or what valid values exist. The current hypothesis is that
44  this is something just used on the FAST chip selects and that the SLOW
45  chip selects are understood fully. There is also a "byte device enable"
46  flag somewhere for 8bit memories.
47
48  FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
49  unclear what this means, if they are mutually exclusive or can be used
50  together, or if some chip selects are hardwired to be FAST and others are SLOW
51  by design.
52
53  The XMEM registers are totally undocumented but could be partially decoded
54  because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
55  similar register layout, see: http://www.cypress.com/file/105771/download
56
57maintainers:
58  - Bjorn Andersson <andersson@kernel.org>
59
60properties:
61  compatible:
62    enum:
63      - qcom,apq8060-ebi2
64      - qcom,msm8660-ebi2
65
66  reg:
67    items:
68      - description: EBI2 config region
69      - description: XMEM config region
70
71  reg-names:
72    items:
73      - const: ebi2
74      - const: xmem
75
76  ranges: true
77
78  clocks:
79    items:
80      - description: EBI_2X clock
81      - description: EBI clock
82
83  clock-names:
84    items:
85      - const: ebi2x
86      - const: ebi2
87
88  '#address-cells':
89    const: 2
90
91  '#size-cells':
92    const: 1
93
94required:
95  - compatible
96  - reg
97  - reg-names
98  - ranges
99  - clocks
100  - clock-names
101  - '#address-cells'
102  - '#size-cells'
103
104patternProperties:
105  "^.*@[0-5],[0-9a-f]+$":
106    type: object
107    $ref: mc-peripheral-props.yaml#
108    additionalProperties: true
109
110additionalProperties: false
111
112examples:
113  - |
114    #include <dt-bindings/clock/qcom,gcc-msm8660.h>
115    #include <dt-bindings/interrupt-controller/irq.h>
116    #include <dt-bindings/gpio/gpio.h>
117
118    external-bus@1a100000 {
119        compatible = "qcom,msm8660-ebi2";
120        reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
121        reg-names = "ebi2", "xmem";
122        ranges = <0 0x0 0x1a800000 0x00800000>,
123                 <1 0x0 0x1b000000 0x00800000>,
124                 <2 0x0 0x1b800000 0x00800000>,
125                 <3 0x0 0x1d000000 0x08000000>,
126                 <4 0x0 0x1c800000 0x00800000>,
127                 <5 0x0 0x1c000000 0x00800000>;
128
129        clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
130        clock-names = "ebi2x", "ebi2";
131
132        #address-cells = <2>;
133        #size-cells = <1>;
134
135        ethernet@2,0 {
136            compatible = "smsc,lan9221", "smsc,lan9115";
137            reg = <2 0x0 0x100>;
138
139            interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
140                                  <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
141            reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
142
143            phy-mode = "mii";
144            reg-io-width = <2>;
145            smsc,force-external-phy;
146            smsc,irq-push-pull;
147
148            /* SLOW chipselect config */
149            qcom,xmem-recovery-cycles = <0>;
150            qcom,xmem-write-hold-cycles = <3>;
151            qcom,xmem-write-delta-cycles = <31>;
152            qcom,xmem-read-delta-cycles = <28>;
153            qcom,xmem-write-wait-cycles = <9>;
154            qcom,xmem-read-wait-cycles = <9>;
155        };
156    };
157