1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC SROM Controller driver
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13  The SROM controller can be used to attach external peripherals. In this case
14  extra properties, describing the bus behind it, should be specified.
15
16properties:
17  compatible:
18    items:
19      - const: samsung,exynos4210-srom
20
21  reg:
22    maxItems: 1
23
24  "#address-cells":
25    const: 2
26
27  "#size-cells":
28    const: 1
29
30  ranges:
31    minItems: 1
32    maxItems: 4
33    description: |
34      Reflects the memory layout with four integer values per bank. Format:
35      <bank-number> 0 <parent address of bank> <size>
36      Up to four banks are supported.
37
38patternProperties:
39  "^.*@[0-3],[a-f0-9]+$":
40    type: object
41    $ref: mc-peripheral-props.yaml#
42    additionalProperties: true
43
44    properties:
45      reg-io-width:
46        enum: [1, 2]
47        description:
48          Data width in bytes (1 or 2). If omitted, default of 1 is used.
49
50    required:
51      - samsung,srom-timing
52
53required:
54  - compatible
55  - reg
56
57additionalProperties: false
58
59examples:
60  - |
61    // Example: basic definition, no banks are configured
62    memory-controller@12560000 {
63        compatible = "samsung,exynos4210-srom";
64        reg = <0x12560000 0x14>;
65    };
66
67  - |
68    // Example: SROMc with SMSC911x ethernet chip on bank 3
69    memory-controller@12570000 {
70        #address-cells = <2>;
71        #size-cells = <1>;
72        ranges = <0 0 0x04000000 0x20000   // Bank0
73                  1 0 0x05000000 0x20000   // Bank1
74                  2 0 0x06000000 0x20000   // Bank2
75                  3 0 0x07000000 0x20000>; // Bank3
76
77        compatible = "samsung,exynos4210-srom";
78        reg = <0x12570000 0x14>;
79
80        ethernet@3,0 {
81            compatible = "smsc,lan9115";
82            reg = <3 0 0x10000>;     // Bank 3, offset = 0
83            phy-mode = "mii";
84            interrupt-parent = <&gpx0>;
85            interrupts = <5 8>;
86            reg-io-width = <2>;
87            smsc,irq-push-pull;
88            smsc,force-internal-phy;
89
90            samsung,srom-page-mode;
91            samsung,srom-timing = <9 12 1 9 1 1>;
92        };
93    };
94