1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies legacy IOMMU implementations
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm "B" family devices which are not compatible with arm-smmu have
14  a similar looking IOMMU, but without access to the global register space
15  and optionally requiring additional configuration to route context IRQs
16  to non-secure vs secure interrupt line.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - qcom,msm8916-iommu
24              - qcom,msm8917-iommu
25              - qcom,msm8937-iommu
26              - qcom,msm8953-iommu
27          - const: qcom,msm-iommu-v1
28      - items:
29          - enum:
30              - qcom,msm8953-iommu
31              - qcom,msm8976-iommu
32          - const: qcom,msm-iommu-v2
33
34  clocks:
35    items:
36      - description: Clock required for IOMMU register group access
37      - description: Clock required for underlying bus access
38
39  clock-names:
40    items:
41      - const: iface
42      - const: bus
43
44  power-domains:
45    maxItems: 1
46
47  reg:
48    maxItems: 1
49
50  ranges: true
51
52  qcom,iommu-secure-id:
53    $ref: /schemas/types.yaml#/definitions/uint32
54    description:
55      The SCM secure ID of the IOMMU instance.
56
57  '#address-cells':
58    const: 1
59
60  '#size-cells':
61    const: 1
62
63  '#iommu-cells':
64    const: 1
65
66patternProperties:
67  "^iommu-ctx@[0-9a-f]+$":
68    type: object
69    additionalProperties: false
70    properties:
71      compatible:
72        enum:
73          - qcom,msm-iommu-v1-ns
74          - qcom,msm-iommu-v1-sec
75          - qcom,msm-iommu-v2-ns
76          - qcom,msm-iommu-v2-sec
77
78      interrupts:
79        maxItems: 1
80
81      reg:
82        maxItems: 1
83
84      qcom,ctx-asid:
85        $ref: /schemas/types.yaml#/definitions/uint32
86        description:
87          The ASID number associated to the context bank.
88
89    required:
90      - compatible
91      - interrupts
92      - reg
93
94required:
95  - compatible
96  - clocks
97  - clock-names
98  - ranges
99  - '#address-cells'
100  - '#size-cells'
101  - '#iommu-cells'
102
103additionalProperties: false
104
105examples:
106  - |
107    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
108    #include <dt-bindings/interrupt-controller/arm-gic.h>
109
110    apps_iommu: iommu@1e20000 {
111      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
112      reg = <0x01ef0000 0x3000>;
113      clocks = <&gcc GCC_SMMU_CFG_CLK>,
114               <&gcc GCC_APSS_TCU_CLK>;
115      clock-names = "iface", "bus";
116      qcom,iommu-secure-id = <17>;
117      #address-cells = <1>;
118      #size-cells = <1>;
119      #iommu-cells = <1>;
120      ranges = <0 0x01e20000 0x40000>;
121
122      /* mdp_0: */
123      iommu-ctx@4000 {
124        compatible = "qcom,msm-iommu-v1-ns";
125        reg = <0x4000 0x1000>;
126        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
127      };
128    };
129