1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB I2C Controller
8
9maintainers:
10  - Jarkko Nikula <jarkko.nikula@linux.intel.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          not:
18            contains:
19              const: mscc,ocelot-i2c
20    then:
21      properties:
22        reg:
23          maxItems: 1
24
25properties:
26  compatible:
27    oneOf:
28      - description: Generic Synopsys DesignWare I2C controller
29        const: snps,designware-i2c
30      - description: Renesas RZ/N1D I2C controller
31        items:
32          - const: renesas,r9a06g032-i2c  # RZ/N1D
33          - const: renesas,rzn1-i2c       # RZ/N1
34          - const: snps,designware-i2c
35      - description: Microsemi Ocelot SoCs I2C controller
36        items:
37          - const: mscc,ocelot-i2c
38          - const: snps,designware-i2c
39      - description: Baikal-T1 SoC System I2C controller
40        const: baikal,bt1-sys-i2c
41      - description: T-HEAD TH1520 SoCs I2C controller
42        items:
43          - const: thead,th1520-i2c
44          - const: snps,designware-i2c
45
46  reg:
47    minItems: 1
48    items:
49      - description: DW APB I2C controller memory mapped registers
50      - description: |
51          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
52          This registers are specific to the Ocelot I2C-controller.
53
54  interrupts:
55    maxItems: 1
56
57  clocks:
58    minItems: 1
59    items:
60      - description: I2C controller reference clock source
61      - description: APB interface clock source
62
63  clock-names:
64    minItems: 1
65    items:
66      - const: ref
67      - const: pclk
68
69  resets:
70    maxItems: 1
71
72  clock-frequency:
73    description: Desired I2C bus clock frequency in Hz
74    enum: [100000, 400000, 1000000, 3400000]
75    default: 400000
76
77  i2c-sda-hold-time-ns:
78    description: |
79      The property should contain the SDA hold time in nanoseconds. This option
80      is only supported in hardware blocks version 1.11a or newer or on
81      Microsemi SoCs.
82
83  i2c-scl-falling-time-ns:
84    description: |
85      The property should contain the SCL falling time in nanoseconds.
86      This value is used to compute the tLOW period.
87    default: 300
88
89  i2c-sda-falling-time-ns:
90    description: |
91      The property should contain the SDA falling time in nanoseconds.
92      This value is used to compute the tHIGH period.
93    default: 300
94
95  dmas:
96    items:
97      - description: TX DMA Channel
98      - description: RX DMA Channel
99
100  dma-names:
101    items:
102      - const: tx
103      - const: rx
104
105  snps,bus-capacitance-pf:
106    $ref: /schemas/types.yaml#/definitions/uint32
107    description:
108      This property indicates the bus capacitance in picofarads (pF).
109      This value is used to compute the tHIGH and tLOW periods for high speed
110      mode.
111    enum: [100, 400]
112    default: 100
113
114  snps,clk-freq-optimized:
115    description:
116      This property indicates whether the hardware reduce its clock frequency
117      by reducing the internal latency required to generate the high period and
118      low period of SCL line.
119    type: boolean
120
121unevaluatedProperties: false
122
123required:
124  - compatible
125  - reg
126  - interrupts
127
128examples:
129  - |
130    i2c@f0000 {
131      compatible = "snps,designware-i2c";
132      reg = <0xf0000 0x1000>;
133      interrupts = <11>;
134      clock-frequency = <400000>;
135    };
136  - |
137    i2c@1120000 {
138      compatible = "snps,designware-i2c";
139      reg = <0x1120000 0x1000>;
140      interrupts = <12 1>;
141      clock-frequency = <400000>;
142      i2c-sda-hold-time-ns = <300>;
143      i2c-sda-falling-time-ns = <300>;
144      i2c-scl-falling-time-ns = <300>;
145      snps,bus-capacitance-pf = <400>;
146      snps,clk-freq-optimized;
147    };
148  - |
149    i2c@2000 {
150      compatible = "snps,designware-i2c";
151      reg = <0x2000 0x100>;
152      #address-cells = <1>;
153      #size-cells = <0>;
154      clock-frequency = <400000>;
155      clocks = <&i2cclk>;
156      interrupts = <0>;
157
158      eeprom@64 {
159        compatible = "atmel,24c02";
160        reg = <0x64>;
161      };
162    };
163  - |
164    i2c@100400 {
165      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
166      reg = <0x100400 0x100>, <0x198 0x8>;
167      pinctrl-0 = <&i2c_pins>;
168      pinctrl-names = "default";
169      interrupts = <8>;
170      clocks = <&ahb_clk>;
171    };
172...
173