1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Atmel Direct Memory Access Controller (DMA)
8
9maintainers:
10  - Ludovic Desroches <ludovic.desroches@microchip.com>
11
12description:
13  The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
14  peripheral to a destination peripheral over one or more AMBA buses. One channel
15  is required for each source/destination pair. In the most basic configuration,
16  the DMAC has one master interface and one channel. The master interface reads
17  the data from a source and writes it to a destination. Two AMBA transfers are
18  required for each DMAC data transfer. This is also known as a dual-access transfer.
19  The DMAC is programmed via the APB interface.
20
21properties:
22  compatible:
23    enum:
24      - atmel,at91sam9g45-dma
25      - atmel,at91sam9rl-dma
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  "#dma-cells":
34    description:
35      Must be <2>, used to represent the number of integer cells in the dma
36      property of client devices. The two cells in order are
37      1. The first cell represents the channel number.
38      2. The second cell is 0 for RX and 1 for TX transfers.
39    const: 2
40
41  clocks:
42    maxItems: 1
43
44  clock-names:
45    const: dma_clk
46
47required:
48  - compatible
49  - reg
50  - interrupts
51  - "#dma-cells"
52  - clocks
53  - clock-names
54
55additionalProperties: false
56
57examples:
58  - |
59    dma-controller@ffffec00 {
60        compatible = "atmel,at91sam9g45-dma";
61        reg = <0xffffec00 0x200>;
62        interrupts = <21>;
63        #dma-cells = <2>;
64        clocks = <&pmc 2 20>;
65        clock-names = "dma_clk";
66    };
67
68...
69