1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 Display MDSS
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12description:
13  SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8550-mdss
21
22  clocks:
23    items:
24      - description: Display MDSS AHB
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    items:
34      - description: Interconnect path from mdp0 port to the data bus
35      - description: Interconnect path from CPU to the reg bus
36
37  interconnect-names:
38    items:
39      - const: mdp0-mem
40      - const: cpu-cfg
41
42patternProperties:
43  "^display-controller@[0-9a-f]+$":
44    type: object
45    additionalProperties: true
46
47    properties:
48      compatible:
49        const: qcom,sm8550-dpu
50
51  "^displayport-controller@[0-9a-f]+$":
52    type: object
53    additionalProperties: true
54
55    properties:
56      compatible:
57        items:
58          - const: qcom,sm8550-dp
59          - const: qcom,sm8350-dp
60
61  "^dsi@[0-9a-f]+$":
62    type: object
63    additionalProperties: true
64
65    properties:
66      compatible:
67        items:
68          - const: qcom,sm8550-dsi-ctrl
69          - const: qcom,mdss-dsi-ctrl
70
71  "^phy@[0-9a-f]+$":
72    type: object
73    additionalProperties: true
74
75    properties:
76      compatible:
77        const: qcom,sm8550-dsi-phy-4nm
78
79required:
80  - compatible
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
87    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
88    #include <dt-bindings/clock/qcom,rpmh.h>
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
91    #include <dt-bindings/power/qcom,rpmhpd.h>
92
93    display-subsystem@ae00000 {
94        compatible = "qcom,sm8550-mdss";
95        reg = <0x0ae00000 0x1000>;
96        reg-names = "mdss";
97
98        interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
99                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
100        interconnect-names = "mdp0-mem", "cpu-cfg";
101
102        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103
104        power-domains = <&dispcc MDSS_GDSC>;
105
106        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
107                 <&gcc GCC_DISP_AHB_CLK>,
108                 <&gcc GCC_DISP_HF_AXI_CLK>,
109                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
110        clock-names = "iface", "bus", "nrt_bus", "core";
111
112        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
113        interrupt-controller;
114        #interrupt-cells = <1>;
115
116        iommus = <&apps_smmu 0x1c00 0x2>;
117
118        #address-cells = <1>;
119        #size-cells = <1>;
120        ranges;
121
122        display-controller@ae01000 {
123            compatible = "qcom,sm8550-dpu";
124            reg = <0x0ae01000 0x8f000>,
125                  <0x0aeb0000 0x2008>;
126            reg-names = "mdp", "vbif";
127
128            clocks = <&gcc GCC_DISP_AHB_CLK>,
129                    <&gcc GCC_DISP_HF_AXI_CLK>,
130                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
131                    <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132                    <&dispcc DISP_CC_MDSS_MDP_CLK>,
133                    <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134            clock-names = "bus",
135                          "nrt_bus",
136                          "iface",
137                          "lut",
138                          "core",
139                          "vsync";
140
141            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
142            assigned-clock-rates = <19200000>;
143
144            operating-points-v2 = <&mdp_opp_table>;
145            power-domains = <&rpmhpd RPMHPD_MMCX>;
146
147            interrupt-parent = <&mdss>;
148            interrupts = <0>;
149
150            ports {
151                #address-cells = <1>;
152                #size-cells = <0>;
153
154                port@0 {
155                    reg = <0>;
156                    dpu_intf1_out: endpoint {
157                        remote-endpoint = <&dsi0_in>;
158                    };
159                };
160
161                port@1 {
162                    reg = <1>;
163                    dpu_intf2_out: endpoint {
164                        remote-endpoint = <&dsi1_in>;
165                    };
166                };
167            };
168
169            mdp_opp_table: opp-table {
170                compatible = "operating-points-v2";
171
172                opp-200000000 {
173                    opp-hz = /bits/ 64 <200000000>;
174                    required-opps = <&rpmhpd_opp_low_svs>;
175                };
176
177                opp-325000000 {
178                    opp-hz = /bits/ 64 <325000000>;
179                    required-opps = <&rpmhpd_opp_svs>;
180                };
181
182                opp-375000000 {
183                    opp-hz = /bits/ 64 <375000000>;
184                    required-opps = <&rpmhpd_opp_svs_l1>;
185                };
186
187                opp-514000000 {
188                    opp-hz = /bits/ 64 <514000000>;
189                    required-opps = <&rpmhpd_opp_nom>;
190                };
191            };
192        };
193
194        dsi@ae94000 {
195            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
196            reg = <0x0ae94000 0x400>;
197            reg-names = "dsi_ctrl";
198
199            interrupt-parent = <&mdss>;
200            interrupts = <4>;
201
202            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
203                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
204                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
205                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
206                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
207                     <&gcc GCC_DISP_HF_AXI_CLK>;
208            clock-names = "byte",
209                          "byte_intf",
210                          "pixel",
211                          "core",
212                          "iface",
213                          "bus";
214
215            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
216                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
217            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
218
219            operating-points-v2 = <&dsi_opp_table>;
220            power-domains = <&rpmhpd RPMHPD_MMCX>;
221
222            phys = <&dsi0_phy>;
223            phy-names = "dsi";
224
225            #address-cells = <1>;
226            #size-cells = <0>;
227
228            ports {
229                #address-cells = <1>;
230                #size-cells = <0>;
231
232                port@0 {
233                    reg = <0>;
234                    dsi0_in: endpoint {
235                        remote-endpoint = <&dpu_intf1_out>;
236                    };
237                };
238
239                port@1 {
240                    reg = <1>;
241                    dsi0_out: endpoint {
242                    };
243                };
244            };
245
246            dsi_opp_table: opp-table {
247                compatible = "operating-points-v2";
248
249                opp-187500000 {
250                    opp-hz = /bits/ 64 <187500000>;
251                    required-opps = <&rpmhpd_opp_low_svs>;
252                };
253
254                opp-300000000 {
255                    opp-hz = /bits/ 64 <300000000>;
256                    required-opps = <&rpmhpd_opp_svs>;
257                };
258
259                opp-358000000 {
260                    opp-hz = /bits/ 64 <358000000>;
261                    required-opps = <&rpmhpd_opp_svs_l1>;
262                };
263            };
264        };
265
266        dsi0_phy: phy@ae94400 {
267            compatible = "qcom,sm8550-dsi-phy-4nm";
268            reg = <0x0ae95000 0x200>,
269                  <0x0ae95200 0x280>,
270                  <0x0ae95500 0x400>;
271            reg-names = "dsi_phy",
272                        "dsi_phy_lane",
273                        "dsi_pll";
274
275            #clock-cells = <1>;
276            #phy-cells = <0>;
277
278            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
279                     <&rpmhcc RPMH_CXO_CLK>;
280            clock-names = "iface", "ref";
281        };
282
283        dsi@ae96000 {
284            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
285            reg = <0x0ae96000 0x400>;
286            reg-names = "dsi_ctrl";
287
288            interrupt-parent = <&mdss>;
289            interrupts = <5>;
290
291            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
292                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
293                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
294                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
295                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
296                     <&gcc GCC_DISP_HF_AXI_CLK>;
297            clock-names = "byte",
298                          "byte_intf",
299                          "pixel",
300                          "core",
301                          "iface",
302                          "bus";
303
304            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
305                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
306            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
307
308            operating-points-v2 = <&dsi_opp_table>;
309            power-domains = <&rpmhpd RPMHPD_MMCX>;
310
311            phys = <&dsi1_phy>;
312            phy-names = "dsi";
313
314            #address-cells = <1>;
315            #size-cells = <0>;
316
317            ports {
318                #address-cells = <1>;
319                #size-cells = <0>;
320
321                port@0 {
322                    reg = <0>;
323                    dsi1_in: endpoint {
324                        remote-endpoint = <&dpu_intf2_out>;
325                    };
326                };
327
328                port@1 {
329                    reg = <1>;
330                    dsi1_out: endpoint {
331                    };
332                };
333            };
334        };
335
336        dsi1_phy: phy@ae96400 {
337            compatible = "qcom,sm8550-dsi-phy-4nm";
338            reg = <0x0ae97000 0x200>,
339                  <0x0ae97200 0x280>,
340                  <0x0ae97500 0x400>;
341            reg-names = "dsi_phy",
342                        "dsi_phy_lane",
343                        "dsi_pll";
344
345            #clock-cells = <1>;
346            #phy-cells = <0>;
347
348            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
349                     <&rpmhcc RPMH_CXO_CLK>;
350            clock-names = "iface", "ref";
351        };
352    };
353...
354