1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - items:
27          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28          - const: qcom,adreno-gmu
29      - const: qcom,adreno-gmu-wrapper
30
31  reg:
32    minItems: 1
33    maxItems: 4
34
35  reg-names:
36    minItems: 1
37    maxItems: 4
38
39  clocks:
40    minItems: 4
41    maxItems: 7
42
43  clock-names:
44    minItems: 4
45    maxItems: 7
46
47  interrupts:
48    items:
49      - description: GMU HFI interrupt
50      - description: GMU interrupt
51
52  interrupt-names:
53    items:
54      - const: hfi
55      - const: gmu
56
57  power-domains:
58    items:
59      - description: CX power domain
60      - description: GX power domain
61
62  power-domain-names:
63    items:
64      - const: cx
65      - const: gx
66
67  iommus:
68    maxItems: 1
69
70  qcom,qmp:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description: Reference to the AOSS side-channel message RAM
73
74  operating-points-v2: true
75
76  opp-table:
77    type: object
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - power-domains
84  - power-domain-names
85
86additionalProperties: false
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - qcom,adreno-gmu-618.0
95              - qcom,adreno-gmu-630.2
96    then:
97      properties:
98        reg:
99          items:
100            - description: Core GMU registers
101            - description: GMU PDC registers
102            - description: GMU PDC sequence registers
103        reg-names:
104          items:
105            - const: gmu
106            - const: gmu_pdc
107            - const: gmu_pdc_seq
108        clocks:
109          items:
110            - description: GMU clock
111            - description: GPU CX clock
112            - description: GPU AXI clock
113            - description: GPU MEMNOC clock
114        clock-names:
115          items:
116            - const: gmu
117            - const: cxo
118            - const: axi
119            - const: memnoc
120
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - qcom,adreno-gmu-623.0
127              - qcom,adreno-gmu-635.0
128              - qcom,adreno-gmu-660.1
129              - qcom,adreno-gmu-663.0
130    then:
131      properties:
132        reg:
133          items:
134            - description: Core GMU registers
135            - description: Resource controller registers
136            - description: GMU PDC registers
137        reg-names:
138          items:
139            - const: gmu
140            - const: rscc
141            - const: gmu_pdc
142        clocks:
143          items:
144            - description: GMU clock
145            - description: GPU CX clock
146            - description: GPU AXI clock
147            - description: GPU MEMNOC clock
148            - description: GPU AHB clock
149            - description: GPU HUB CX clock
150            - description: GPU SMMU vote clock
151        clock-names:
152          items:
153            - const: gmu
154            - const: cxo
155            - const: axi
156            - const: memnoc
157            - const: ahb
158            - const: hub
159            - const: smmu_vote
160
161  - if:
162      properties:
163        compatible:
164          contains:
165            enum:
166              - qcom,adreno-gmu-640.1
167    then:
168      properties:
169        reg:
170          items:
171            - description: Core GMU registers
172            - description: GMU PDC registers
173            - description: GMU PDC sequence registers
174        reg-names:
175          items:
176            - const: gmu
177            - const: gmu_pdc
178            - const: gmu_pdc_seq
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - qcom,adreno-gmu-650.2
186    then:
187      properties:
188        reg:
189          items:
190            - description: Core GMU registers
191            - description: Resource controller registers
192            - description: GMU PDC registers
193            - description: GMU PDC sequence registers
194        reg-names:
195          items:
196            - const: gmu
197            - const: rscc
198            - const: gmu_pdc
199            - const: gmu_pdc_seq
200
201  - if:
202      properties:
203        compatible:
204          contains:
205            enum:
206              - qcom,adreno-gmu-640.1
207              - qcom,adreno-gmu-650.2
208    then:
209      properties:
210        clocks:
211          items:
212            - description: GPU AHB clock
213            - description: GMU clock
214            - description: GPU CX clock
215            - description: GPU AXI clock
216            - description: GPU MEMNOC clock
217        clock-names:
218          items:
219            - const: ahb
220            - const: gmu
221            - const: cxo
222            - const: axi
223            - const: memnoc
224
225  - if:
226      properties:
227        compatible:
228          contains:
229            enum:
230              - qcom,adreno-gmu-730.1
231              - qcom,adreno-gmu-740.1
232              - qcom,adreno-gmu-750.1
233              - qcom,adreno-gmu-x185.1
234    then:
235      properties:
236        reg:
237          items:
238            - description: Core GMU registers
239            - description: Resource controller registers
240            - description: GMU PDC registers
241        reg-names:
242          items:
243            - const: gmu
244            - const: rscc
245            - const: gmu_pdc
246        clocks:
247          items:
248            - description: GPU AHB clock
249            - description: GMU clock
250            - description: GPU CX clock
251            - description: GPU AXI clock
252            - description: GPU MEMNOC clock
253            - description: GMU HUB clock
254            - description: GPUSS DEMET clock
255        clock-names:
256          items:
257            - const: ahb
258            - const: gmu
259            - const: cxo
260            - const: axi
261            - const: memnoc
262            - const: hub
263            - const: demet
264
265      required:
266        - qcom,qmp
267
268  - if:
269      properties:
270        compatible:
271          contains:
272            const: qcom,adreno-gmu-wrapper
273    then:
274      properties:
275        reg:
276          items:
277            - description: GMU wrapper register space
278        reg-names:
279          items:
280            - const: gmu
281    else:
282      required:
283        - clocks
284        - clock-names
285        - interrupts
286        - interrupt-names
287        - iommus
288        - operating-points-v2
289
290examples:
291  - |
292    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
293    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
294    #include <dt-bindings/interrupt-controller/irq.h>
295    #include <dt-bindings/interrupt-controller/arm-gic.h>
296
297    gmu: gmu@506a000 {
298        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
299
300        reg = <0x506a000 0x30000>,
301              <0xb280000 0x10000>,
302              <0xb480000 0x10000>;
303        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
304
305        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
306                 <&gpucc GPU_CC_CXO_CLK>,
307                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
308                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
309        clock-names = "gmu", "cxo", "axi", "memnoc";
310
311        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
312                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
313        interrupt-names = "hfi", "gmu";
314
315        power-domains = <&gpucc GPU_CX_GDSC>,
316                        <&gpucc GPU_GX_GDSC>;
317        power-domain-names = "cx", "gx";
318
319        iommus = <&adreno_smmu 5>;
320        operating-points-v2 = <&gmu_opp_table>;
321    };
322
323    gmu_wrapper: gmu@596a000 {
324        compatible = "qcom,adreno-gmu-wrapper";
325        reg = <0x0596a000 0x30000>;
326        reg-names = "gmu";
327        power-domains = <&gpucc GPU_CX_GDSC>,
328                        <&gpucc GPU_GX_GDSC>;
329        power-domain-names = "cx", "gx";
330    };
331