1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8976-dsi-ctrl 23 - qcom,msm8996-dsi-ctrl 24 - qcom,msm8998-dsi-ctrl 25 - qcom,qcm2290-dsi-ctrl 26 - qcom,sc7180-dsi-ctrl 27 - qcom,sc7280-dsi-ctrl 28 - qcom,sdm660-dsi-ctrl 29 - qcom,sdm670-dsi-ctrl 30 - qcom,sdm845-dsi-ctrl 31 - qcom,sm6115-dsi-ctrl 32 - qcom,sm6125-dsi-ctrl 33 - qcom,sm6150-dsi-ctrl 34 - qcom,sm6350-dsi-ctrl 35 - qcom,sm6375-dsi-ctrl 36 - qcom,sm7150-dsi-ctrl 37 - qcom,sm8150-dsi-ctrl 38 - qcom,sm8250-dsi-ctrl 39 - qcom,sm8350-dsi-ctrl 40 - qcom,sm8450-dsi-ctrl 41 - qcom,sm8550-dsi-ctrl 42 - qcom,sm8650-dsi-ctrl 43 - const: qcom,mdss-dsi-ctrl 44 - enum: 45 - qcom,dsi-ctrl-6g-qcm2290 46 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 47 deprecated: true 48 49 reg: 50 maxItems: 1 51 52 reg-names: 53 const: dsi_ctrl 54 55 interrupts: 56 maxItems: 1 57 58 clocks: 59 description: | 60 Several clocks are used, depending on the variant. Typical ones are:: 61 - bus:: Display AHB clock. 62 - byte:: Display byte clock. 63 - byte_intf:: Display byte interface clock. 64 - core:: Display core clock. 65 - core_mss:: Core MultiMedia SubSystem clock. 66 - iface:: Display AXI clock. 67 - mdp_core:: MDP Core clock. 68 - mnoc:: MNOC clock 69 - pixel:: Display pixel clock. 70 minItems: 3 71 maxItems: 9 72 73 clock-names: 74 minItems: 3 75 maxItems: 9 76 77 phys: 78 maxItems: 1 79 80 phy-names: 81 deprecated: true 82 const: dsi 83 84 syscon-sfpb: 85 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 86 $ref: /schemas/types.yaml#/definitions/phandle 87 88 qcom,dual-dsi-mode: 89 type: boolean 90 description: | 91 Indicates if the DSI controller is driving a panel which needs 92 2 DSI links. 93 94 qcom,master-dsi: 95 type: boolean 96 description: | 97 Indicates if the DSI controller is the master DSI controller when 98 qcom,dual-dsi-mode enabled. 99 100 qcom,sync-dual-dsi: 101 type: boolean 102 description: | 103 Indicates if the DSI controller needs to sync the other DSI controller 104 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 105 106 assigned-clocks: 107 minItems: 2 108 maxItems: 4 109 description: | 110 Parents of "byte" and "pixel" for the given platform. 111 For DSIv2 platforms this should contain "byte", "esc", "src" and 112 "pixel_src" clocks. 113 114 assigned-clock-parents: 115 minItems: 2 116 maxItems: 4 117 description: | 118 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 119 120 power-domains: 121 maxItems: 1 122 123 operating-points-v2: true 124 125 opp-table: 126 type: object 127 128 ports: 129 $ref: /schemas/graph.yaml#/properties/ports 130 description: | 131 Contains DSI controller input and output ports as children, each 132 containing one endpoint subnode. 133 134 properties: 135 port@0: 136 $ref: /schemas/graph.yaml#/$defs/port-base 137 unevaluatedProperties: false 138 description: | 139 Input endpoints of the controller. 140 properties: 141 endpoint: 142 $ref: /schemas/media/video-interfaces.yaml# 143 unevaluatedProperties: false 144 properties: 145 data-lanes: 146 maxItems: 4 147 minItems: 1 148 items: 149 enum: [ 0, 1, 2, 3 ] 150 151 port@1: 152 $ref: /schemas/graph.yaml#/$defs/port-base 153 unevaluatedProperties: false 154 description: | 155 Output endpoints of the controller. 156 properties: 157 endpoint: 158 $ref: /schemas/media/video-interfaces.yaml# 159 unevaluatedProperties: false 160 properties: 161 data-lanes: 162 maxItems: 4 163 minItems: 1 164 items: 165 enum: [ 0, 1, 2, 3 ] 166 167 qcom,te-source: 168 $ref: /schemas/types.yaml#/definitions/string 169 description: 170 Specifies the source of vsync signal from the panel used for 171 tearing elimination. 172 default: mdp_vsync_p 173 enum: 174 - mdp_vsync_p 175 - mdp_vsync_s 176 - mdp_vsync_e 177 - timer0 178 - timer1 179 - timer2 180 - timer3 181 - timer4 182 183 required: 184 - port@0 185 - port@1 186 187 avdd-supply: 188 description: 189 Phandle to vdd regulator device node 190 191 refgen-supply: 192 description: 193 Phandle to REFGEN regulator device node 194 195 vcca-supply: 196 description: 197 Phandle to vdd regulator device node 198 199 vdd-supply: 200 description: 201 VDD regulator 202 203 vddio-supply: 204 description: 205 VDD-IO regulator 206 207 vdda-supply: 208 description: 209 VDDA regulator 210 211required: 212 - compatible 213 - reg 214 - reg-names 215 - interrupts 216 - clocks 217 - clock-names 218 - phys 219 - assigned-clocks 220 - assigned-clock-parents 221 - ports 222 223allOf: 224 - $ref: ../dsi-controller.yaml# 225 - if: 226 properties: 227 compatible: 228 contains: 229 enum: 230 - qcom,apq8064-dsi-ctrl 231 then: 232 properties: 233 clocks: 234 minItems: 7 235 maxItems: 7 236 clock-names: 237 items: 238 - const: iface 239 - const: bus 240 - const: core_mmss 241 - const: src 242 - const: byte 243 - const: pixel 244 - const: core 245 246 - if: 247 properties: 248 compatible: 249 contains: 250 enum: 251 - qcom,msm8916-dsi-ctrl 252 - qcom,msm8953-dsi-ctrl 253 - qcom,msm8976-dsi-ctrl 254 then: 255 properties: 256 clocks: 257 minItems: 6 258 maxItems: 6 259 clock-names: 260 items: 261 - const: mdp_core 262 - const: iface 263 - const: bus 264 - const: byte 265 - const: pixel 266 - const: core 267 268 - if: 269 properties: 270 compatible: 271 contains: 272 enum: 273 - qcom,msm8226-dsi-ctrl 274 - qcom,msm8974-dsi-ctrl 275 then: 276 properties: 277 clocks: 278 minItems: 7 279 maxItems: 7 280 clock-names: 281 items: 282 - const: mdp_core 283 - const: iface 284 - const: bus 285 - const: byte 286 - const: pixel 287 - const: core 288 - const: core_mmss 289 290 - if: 291 properties: 292 compatible: 293 contains: 294 enum: 295 - qcom,msm8996-dsi-ctrl 296 then: 297 properties: 298 clocks: 299 minItems: 7 300 maxItems: 7 301 clock-names: 302 items: 303 - const: mdp_core 304 - const: byte 305 - const: iface 306 - const: bus 307 - const: core_mmss 308 - const: pixel 309 - const: core 310 311 - if: 312 properties: 313 compatible: 314 contains: 315 enum: 316 - qcom,msm8998-dsi-ctrl 317 - qcom,sc7180-dsi-ctrl 318 - qcom,sc7280-dsi-ctrl 319 - qcom,sdm845-dsi-ctrl 320 - qcom,sm6115-dsi-ctrl 321 - qcom,sm6125-dsi-ctrl 322 - qcom,sm6350-dsi-ctrl 323 - qcom,sm6375-dsi-ctrl 324 - qcom,sm6150-dsi-ctrl 325 - qcom,sm7150-dsi-ctrl 326 - qcom,sm8150-dsi-ctrl 327 - qcom,sm8250-dsi-ctrl 328 - qcom,sm8350-dsi-ctrl 329 - qcom,sm8450-dsi-ctrl 330 - qcom,sm8550-dsi-ctrl 331 - qcom,sm8650-dsi-ctrl 332 then: 333 properties: 334 clocks: 335 minItems: 6 336 maxItems: 6 337 clock-names: 338 items: 339 - const: byte 340 - const: byte_intf 341 - const: pixel 342 - const: core 343 - const: iface 344 - const: bus 345 346 - if: 347 properties: 348 compatible: 349 contains: 350 enum: 351 - qcom,sdm660-dsi-ctrl 352 then: 353 properties: 354 clocks: 355 minItems: 9 356 maxItems: 9 357 clock-names: 358 items: 359 - const: mdp_core 360 - const: byte 361 - const: byte_intf 362 - const: mnoc 363 - const: iface 364 - const: bus 365 - const: core_mmss 366 - const: pixel 367 - const: core 368 369unevaluatedProperties: false 370 371examples: 372 - | 373 #include <dt-bindings/interrupt-controller/arm-gic.h> 374 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 375 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 376 #include <dt-bindings/power/qcom-rpmpd.h> 377 378 dsi@ae94000 { 379 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 380 reg = <0x0ae94000 0x400>; 381 reg-names = "dsi_ctrl"; 382 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 interrupt-parent = <&mdss>; 387 interrupts = <4>; 388 389 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 390 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 391 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 392 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 393 <&dispcc DISP_CC_MDSS_AHB_CLK>, 394 <&dispcc DISP_CC_MDSS_AXI_CLK>; 395 clock-names = "byte", 396 "byte_intf", 397 "pixel", 398 "core", 399 "iface", 400 "bus"; 401 402 phys = <&dsi0_phy>; 403 phy-names = "dsi"; 404 405 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 406 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 407 408 power-domains = <&rpmhpd SC7180_CX>; 409 operating-points-v2 = <&dsi_opp_table>; 410 411 ports { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 415 port@0 { 416 reg = <0>; 417 endpoint { 418 remote-endpoint = <&dpu_intf1_out>; 419 }; 420 }; 421 422 port@1 { 423 reg = <1>; 424 endpoint { 425 remote-endpoint = <&sn65dsi86_in>; 426 data-lanes = <0 1 2 3>; 427 qcom,te-source = "mdp_vsync_e"; 428 }; 429 }; 430 }; 431 }; 432... 433