1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,sc7180-cpufreq-hw
26              - qcom,sc8180x-cpufreq-hw
27              - qcom,sdm670-cpufreq-hw
28              - qcom,sdm845-cpufreq-hw
29              - qcom,sm6115-cpufreq-hw
30              - qcom,sm6350-cpufreq-hw
31              - qcom,sm8150-cpufreq-hw
32          - const: qcom,cpufreq-hw
33
34      - description: v2 of CPUFREQ HW (EPSS)
35        items:
36          - enum:
37              - qcom,qcs8300-cpufreq-epss
38              - qcom,qdu1000-cpufreq-epss
39              - qcom,sa8255p-cpufreq-epss
40              - qcom,sa8775p-cpufreq-epss
41              - qcom,sar2130p-cpufreq-epss
42              - qcom,sc7280-cpufreq-epss
43              - qcom,sc8280xp-cpufreq-epss
44              - qcom,sdx75-cpufreq-epss
45              - qcom,sm4450-cpufreq-epss
46              - qcom,sm6375-cpufreq-epss
47              - qcom,sm8250-cpufreq-epss
48              - qcom,sm8350-cpufreq-epss
49              - qcom,sm8450-cpufreq-epss
50              - qcom,sm8550-cpufreq-epss
51              - qcom,sm8650-cpufreq-epss
52          - const: qcom,cpufreq-epss
53
54  reg:
55    minItems: 1
56    items:
57      - description: Frequency domain 0 register region
58      - description: Frequency domain 1 register region
59      - description: Frequency domain 2 register region
60      - description: Frequency domain 3 register region
61
62  reg-names:
63    minItems: 1
64    items:
65      - const: freq-domain0
66      - const: freq-domain1
67      - const: freq-domain2
68      - const: freq-domain3
69
70  clocks:
71    items:
72      - description: XO Clock
73      - description: GPLL0 Clock
74
75  clock-names:
76    items:
77      - const: xo
78      - const: alternate
79
80  interrupts:
81    minItems: 1
82    maxItems: 4
83
84  interrupt-names:
85    minItems: 1
86    items:
87      - const: dcvsh-irq-0
88      - const: dcvsh-irq-1
89      - const: dcvsh-irq-2
90      - const: dcvsh-irq-3
91
92  '#freq-domain-cells':
93    const: 1
94
95  '#clock-cells':
96    const: 1
97
98required:
99  - compatible
100  - reg
101  - clocks
102  - clock-names
103  - '#freq-domain-cells'
104
105additionalProperties: false
106
107allOf:
108  - if:
109      properties:
110        compatible:
111          contains:
112            enum:
113              - qcom,qcm2290-cpufreq-hw
114              - qcom,sar2130p-cpufreq-epss
115              - qcom,sdx75-cpufreq-epss
116    then:
117      properties:
118        reg:
119          maxItems: 1
120
121        reg-names:
122          maxItems: 1
123
124        interrupts:
125          maxItems: 1
126
127        interrupt-names:
128          maxItems: 1
129
130  - if:
131      properties:
132        compatible:
133          contains:
134            enum:
135              - qcom,qdu1000-cpufreq-epss
136              - qcom,sa8255p-cpufreq-epss
137              - qcom,sa8775p-cpufreq-epss
138              - qcom,sc7180-cpufreq-hw
139              - qcom,sc8180x-cpufreq-hw
140              - qcom,sc8280xp-cpufreq-epss
141              - qcom,sdm670-cpufreq-hw
142              - qcom,sdm845-cpufreq-hw
143              - qcom,sm4450-cpufreq-epss
144              - qcom,sm6115-cpufreq-hw
145              - qcom,sm6350-cpufreq-hw
146              - qcom,sm6375-cpufreq-epss
147    then:
148      properties:
149        reg:
150          minItems: 2
151          maxItems: 2
152
153        reg-names:
154          minItems: 2
155          maxItems: 2
156
157        interrupts:
158          minItems: 2
159          maxItems: 2
160
161        interrupt-names:
162          minItems: 2
163          maxItems: 2
164
165  - if:
166      properties:
167        compatible:
168          contains:
169            enum:
170              - qcom,qcs8300-cpufreq-epss
171              - qcom,sc7280-cpufreq-epss
172              - qcom,sm8250-cpufreq-epss
173              - qcom,sm8350-cpufreq-epss
174              - qcom,sm8450-cpufreq-epss
175              - qcom,sm8550-cpufreq-epss
176    then:
177      properties:
178        reg:
179          minItems: 3
180          maxItems: 3
181
182        reg-names:
183          minItems: 3
184          maxItems: 3
185
186        interrupts:
187          minItems: 3
188          maxItems: 3
189
190        interrupt-names:
191          minItems: 3
192          maxItems: 3
193
194  - if:
195      properties:
196        compatible:
197          contains:
198            enum:
199              - qcom,sm8150-cpufreq-hw
200    then:
201      properties:
202        reg:
203          minItems: 3
204          maxItems: 3
205
206        reg-names:
207          minItems: 3
208          maxItems: 3
209
210        # On some SoCs the Prime core shares the LMH irq with Big cores
211        interrupts:
212          minItems: 2
213          maxItems: 2
214
215        interrupt-names:
216          minItems: 2
217          maxItems: 2
218
219  - if:
220      properties:
221        compatible:
222          contains:
223            enum:
224              - qcom,sm8650-cpufreq-epss
225    then:
226      properties:
227        reg:
228          minItems: 4
229          maxItems: 4
230
231        reg-names:
232          minItems: 4
233          maxItems: 4
234
235        interrupts:
236          minItems: 4
237          maxItems: 4
238
239        interrupt-names:
240          minItems: 4
241          maxItems: 4
242
243examples:
244  - |
245    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
246    #include <dt-bindings/clock/qcom,rpmh.h>
247
248    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
249    // switch DCVS state together.
250    cpus {
251      #address-cells = <2>;
252      #size-cells = <0>;
253
254      CPU0: cpu@0 {
255        device_type = "cpu";
256        compatible = "qcom,kryo385";
257        reg = <0x0 0x0>;
258        enable-method = "psci";
259        next-level-cache = <&L2_0>;
260        qcom,freq-domain = <&cpufreq_hw 0>;
261        clocks = <&cpufreq_hw 0>;
262        L2_0: l2-cache {
263          compatible = "cache";
264          cache-unified;
265          cache-level = <2>;
266          next-level-cache = <&L3_0>;
267          L3_0: l3-cache {
268            compatible = "cache";
269            cache-unified;
270            cache-level = <3>;
271          };
272        };
273      };
274
275      CPU1: cpu@100 {
276        device_type = "cpu";
277        compatible = "qcom,kryo385";
278        reg = <0x0 0x100>;
279        enable-method = "psci";
280        next-level-cache = <&L2_100>;
281        qcom,freq-domain = <&cpufreq_hw 0>;
282        clocks = <&cpufreq_hw 0>;
283        L2_100: l2-cache {
284          compatible = "cache";
285          cache-unified;
286          cache-level = <2>;
287          next-level-cache = <&L3_0>;
288        };
289      };
290
291      CPU2: cpu@200 {
292        device_type = "cpu";
293        compatible = "qcom,kryo385";
294        reg = <0x0 0x200>;
295        enable-method = "psci";
296        next-level-cache = <&L2_200>;
297        qcom,freq-domain = <&cpufreq_hw 0>;
298        clocks = <&cpufreq_hw 0>;
299        L2_200: l2-cache {
300          compatible = "cache";
301          cache-unified;
302          cache-level = <2>;
303          next-level-cache = <&L3_0>;
304        };
305      };
306
307      CPU3: cpu@300 {
308        device_type = "cpu";
309        compatible = "qcom,kryo385";
310        reg = <0x0 0x300>;
311        enable-method = "psci";
312        next-level-cache = <&L2_300>;
313        qcom,freq-domain = <&cpufreq_hw 0>;
314        clocks = <&cpufreq_hw 0>;
315        L2_300: l2-cache {
316          compatible = "cache";
317          cache-unified;
318          cache-level = <2>;
319          next-level-cache = <&L3_0>;
320        };
321      };
322
323      CPU4: cpu@400 {
324        device_type = "cpu";
325        compatible = "qcom,kryo385";
326        reg = <0x0 0x400>;
327        enable-method = "psci";
328        next-level-cache = <&L2_400>;
329        qcom,freq-domain = <&cpufreq_hw 1>;
330        clocks = <&cpufreq_hw 1>;
331        L2_400: l2-cache {
332          compatible = "cache";
333          cache-unified;
334          cache-level = <2>;
335          next-level-cache = <&L3_0>;
336        };
337      };
338
339      CPU5: cpu@500 {
340        device_type = "cpu";
341        compatible = "qcom,kryo385";
342        reg = <0x0 0x500>;
343        enable-method = "psci";
344        next-level-cache = <&L2_500>;
345        qcom,freq-domain = <&cpufreq_hw 1>;
346        clocks = <&cpufreq_hw 1>;
347        L2_500: l2-cache {
348          compatible = "cache";
349          cache-unified;
350          cache-level = <2>;
351          next-level-cache = <&L3_0>;
352        };
353      };
354
355      CPU6: cpu@600 {
356        device_type = "cpu";
357        compatible = "qcom,kryo385";
358        reg = <0x0 0x600>;
359        enable-method = "psci";
360        next-level-cache = <&L2_600>;
361        qcom,freq-domain = <&cpufreq_hw 1>;
362        clocks = <&cpufreq_hw 1>;
363        L2_600: l2-cache {
364          compatible = "cache";
365          cache-unified;
366          cache-level = <2>;
367          next-level-cache = <&L3_0>;
368        };
369      };
370
371      CPU7: cpu@700 {
372        device_type = "cpu";
373        compatible = "qcom,kryo385";
374        reg = <0x0 0x700>;
375        enable-method = "psci";
376        next-level-cache = <&L2_700>;
377        qcom,freq-domain = <&cpufreq_hw 1>;
378        clocks = <&cpufreq_hw 1>;
379        L2_700: l2-cache {
380          compatible = "cache";
381          cache-unified;
382          cache-level = <2>;
383          next-level-cache = <&L3_0>;
384        };
385      };
386    };
387
388    soc {
389      #address-cells = <1>;
390      #size-cells = <1>;
391
392      cpufreq@17d43000 {
393        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
394        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
395        reg-names = "freq-domain0", "freq-domain1";
396
397        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
398        clock-names = "xo", "alternate";
399
400        #freq-domain-cells = <1>;
401        #clock-cells = <1>;
402      };
403    };
404...
405