1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX8MP AudioMIX Block Control 8 9maintainers: 10 - Marek Vasut <marex@denx.de> 11 12description: | 13 NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP 14 used to control Audio related clock on the SoC. 15 16properties: 17 compatible: 18 const: fsl,imx8mp-audio-blk-ctrl 19 20 reg: 21 maxItems: 1 22 23 power-domains: 24 maxItems: 1 25 26 clocks: 27 minItems: 8 28 maxItems: 8 29 30 clock-names: 31 items: 32 - const: ahb 33 - const: sai1 34 - const: sai2 35 - const: sai3 36 - const: sai5 37 - const: sai6 38 - const: sai7 39 - const: axi 40 41 '#clock-cells': 42 const: 1 43 description: 44 The clock consumer should specify the desired clock by having the clock 45 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h 46 for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs. 47 48 '#reset-cells': 49 const: 1 50 51required: 52 - compatible 53 - reg 54 - clocks 55 - clock-names 56 - power-domains 57 - '#clock-cells' 58 59additionalProperties: false 60 61examples: 62 # Clock Control Module node: 63 - | 64 #include <dt-bindings/clock/imx8mp-clock.h> 65 66 clock-controller@30e20000 { 67 compatible = "fsl,imx8mp-audio-blk-ctrl"; 68 reg = <0x30e20000 0x10000>; 69 #clock-cells = <1>; 70 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 71 <&clk IMX8MP_CLK_SAI1>, 72 <&clk IMX8MP_CLK_SAI2>, 73 <&clk IMX8MP_CLK_SAI3>, 74 <&clk IMX8MP_CLK_SAI5>, 75 <&clk IMX8MP_CLK_SAI6>, 76 <&clk IMX8MP_CLK_SAI7>, 77 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; 78 clock-names = "ahb", 79 "sai1", "sai2", "sai3", 80 "sai5", "sai6", "sai7", "axi"; 81 power-domains = <&pgc_audio>; 82 }; 83 84... 85