1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,avalanche
89      - apple,blizzard
90      - apple,cyclone
91      - apple,firestorm
92      - apple,hurricane-zephyr
93      - apple,icestorm
94      - apple,mistral
95      - apple,monsoon
96      - apple,twister
97      - apple,typhoon
98      - arm,arm710t
99      - arm,arm720t
100      - arm,arm740t
101      - arm,arm7ej-s
102      - arm,arm7tdmi
103      - arm,arm7tdmi-s
104      - arm,arm9es
105      - arm,arm9ej-s
106      - arm,arm920t
107      - arm,arm922t
108      - arm,arm925
109      - arm,arm926e-s
110      - arm,arm926ej-s
111      - arm,arm940t
112      - arm,arm946e-s
113      - arm,arm966e-s
114      - arm,arm968e-s
115      - arm,arm9tdmi
116      - arm,arm1020e
117      - arm,arm1020t
118      - arm,arm1022e
119      - arm,arm1026ej-s
120      - arm,arm1136j-s
121      - arm,arm1136jf-s
122      - arm,arm1156t2-s
123      - arm,arm1156t2f-s
124      - arm,arm1176jzf
125      - arm,arm1176jz-s
126      - arm,arm1176jzf-s
127      - arm,arm11mpcore
128      - arm,armv8 # Only for s/w models
129      - arm,cortex-a5
130      - arm,cortex-a7
131      - arm,cortex-a8
132      - arm,cortex-a9
133      - arm,cortex-a12
134      - arm,cortex-a15
135      - arm,cortex-a17
136      - arm,cortex-a32
137      - arm,cortex-a34
138      - arm,cortex-a35
139      - arm,cortex-a53
140      - arm,cortex-a55
141      - arm,cortex-a57
142      - arm,cortex-a65
143      - arm,cortex-a72
144      - arm,cortex-a73
145      - arm,cortex-a75
146      - arm,cortex-a76
147      - arm,cortex-a77
148      - arm,cortex-a78
149      - arm,cortex-a78ae
150      - arm,cortex-a78c
151      - arm,cortex-a510
152      - arm,cortex-a520
153      - arm,cortex-a710
154      - arm,cortex-a715
155      - arm,cortex-a720
156      - arm,cortex-a725
157      - arm,cortex-m0
158      - arm,cortex-m0+
159      - arm,cortex-m1
160      - arm,cortex-m3
161      - arm,cortex-m4
162      - arm,cortex-r4
163      - arm,cortex-r5
164      - arm,cortex-r7
165      - arm,cortex-r52
166      - arm,cortex-x1
167      - arm,cortex-x1c
168      - arm,cortex-x2
169      - arm,cortex-x3
170      - arm,cortex-x4
171      - arm,cortex-x925
172      - arm,neoverse-e1
173      - arm,neoverse-n1
174      - arm,neoverse-n2
175      - arm,neoverse-n3
176      - arm,neoverse-v1
177      - arm,neoverse-v2
178      - arm,neoverse-v3
179      - arm,neoverse-v3ae
180      - arm,rainier
181      - brcm,brahma-b15
182      - brcm,brahma-b53
183      - brcm,vulcan
184      - cavium,thunder
185      - cavium,thunder2
186      - faraday,fa526
187      - intel,sa110
188      - intel,sa1100
189      - marvell,feroceon
190      - marvell,mohawk
191      - marvell,pj4a
192      - marvell,pj4b
193      - marvell,sheeva-v5
194      - marvell,sheeva-v7
195      - nvidia,tegra132-denver
196      - nvidia,tegra186-denver
197      - nvidia,tegra194-carmel
198      - qcom,krait
199      - qcom,kryo
200      - qcom,kryo240
201      - qcom,kryo250
202      - qcom,kryo260
203      - qcom,kryo280
204      - qcom,kryo360
205      - qcom,kryo385
206      - qcom,kryo465
207      - qcom,kryo468
208      - qcom,kryo485
209      - qcom,kryo560
210      - qcom,kryo570
211      - qcom,kryo660
212      - qcom,kryo670
213      - qcom,kryo685
214      - qcom,kryo780
215      - qcom,oryon
216      - qcom,scorpion
217      - samsung,mongoose-m2
218      - samsung,mongoose-m3
219      - samsung,mongoose-m5
220
221  enable-method:
222    $ref: /schemas/types.yaml#/definitions/string
223    oneOf:
224      # On ARM v8 64-bit this property is required
225      - enum:
226          - psci
227          - spin-table
228      # On ARM 32-bit systems this property is optional
229      - enum:
230          - actions,s500-smp
231          - allwinner,sun6i-a31
232          - allwinner,sun8i-a23
233          - allwinner,sun9i-a80-smp
234          - allwinner,sun8i-a83t-smp
235          - amlogic,meson8-smp
236          - amlogic,meson8b-smp
237          - arm,realview-smp
238          - aspeed,ast2600-smp
239          - brcm,bcm11351-cpu-method
240          - brcm,bcm23550
241          - brcm,bcm2836-smp
242          - brcm,bcm63138
243          - brcm,bcm-nsp-smp
244          - brcm,brahma-b15
245          - marvell,armada-375-smp
246          - marvell,armada-380-smp
247          - marvell,armada-390-smp
248          - marvell,armada-xp-smp
249          - marvell,98dx3236-smp
250          - marvell,mmp3-smp
251          - mediatek,mt6589-smp
252          - mediatek,mt81xx-tz-smp
253          - qcom,gcc-msm8660
254          - qcom,kpss-acc-v1
255          - qcom,kpss-acc-v2
256          - qcom,msm8226-smp
257          - qcom,msm8909-smp
258          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
259          - qcom,msm8916-smp
260          - renesas,apmu
261          - renesas,r9a06g032-smp
262          - rockchip,rk3036-smp
263          - rockchip,rk3066-smp
264          - socionext,milbeaut-m10v-smp
265          - ste,dbx500-smp
266          - ti,am3352
267          - ti,am4372
268
269  cpu-release-addr:
270    oneOf:
271      - $ref: /schemas/types.yaml#/definitions/uint32
272      - $ref: /schemas/types.yaml#/definitions/uint64
273    description:
274      The DT specification defines this as 64-bit always, but some 32-bit Arm
275      systems have used a 32-bit value which must be supported.
276      Required for systems that have an "enable-method"
277        property value of "spin-table".
278
279  cpu-idle-states:
280    $ref: /schemas/types.yaml#/definitions/phandle-array
281    items:
282      maxItems: 1
283    description: |
284      List of phandles to idle state nodes supported
285      by this cpu (see ./idle-states.yaml).
286
287  capacity-dmips-mhz:
288    description:
289      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
290      DMIPS/MHz, relative to highest capacity-dmips-mhz
291      in the system.
292
293  cci-control-port: true
294
295  dynamic-power-coefficient:
296    $ref: /schemas/types.yaml#/definitions/uint32
297    description:
298      A u32 value that represents the running time dynamic
299      power coefficient in units of uW/MHz/V^2. The
300      coefficient can either be calculated from power
301      measurements or derived by analysis.
302
303      The dynamic power consumption of the CPU  is
304      proportional to the square of the Voltage (V) and
305      the clock frequency (f). The coefficient is used to
306      calculate the dynamic power as below -
307
308      Pdyn = dynamic-power-coefficient * V^2 * f
309
310      where voltage is in V, frequency is in MHz.
311
312  performance-domains:
313    maxItems: 1
314    description:
315      List of phandles and performance domain specifiers, as defined by
316      bindings of the performance domain provider. See also
317      dvfs/performance-domain.yaml.
318
319  power-domains:
320    description:
321      List of phandles and PM domain specifiers, as defined by bindings of the
322      PM domain provider (see also ../power_domain.txt).
323
324  power-domain-names:
325    description:
326      A list of power domain name strings sorted in the same order as the
327      power-domains property.
328
329      For PSCI based platforms, the name corresponding to the index of the PSCI
330      PM domain provider, must be "psci". For SCMI based platforms, the name
331      corresponding to the index of an SCMI performance domain provider, must be
332      "perf".
333
334  qcom,saw:
335    $ref: /schemas/types.yaml#/definitions/phandle
336    description: |
337      Specifies the SAW* node associated with this CPU.
338
339      Required for systems that have an "enable-method" property
340      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
341
342      * arm/msm/qcom,saw2.txt
343
344  qcom,acc:
345    $ref: /schemas/types.yaml#/definitions/phandle
346    description: |
347      Specifies the ACC* node associated with this CPU.
348
349      Required for systems that have an "enable-method" property
350      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
351      "qcom,msm8916-smp".
352
353      * arm/msm/qcom,kpss-acc.txt
354
355  rockchip,pmu:
356    $ref: /schemas/types.yaml#/definitions/phandle
357    description: |
358      Specifies the syscon node controlling the cpu core power domains.
359
360      Optional for systems that have an "enable-method"
361      property value of "rockchip,rk3066-smp"
362      While optional, it is the preferred way to get access to
363      the cpu-core power-domains.
364
365  secondary-boot-reg:
366    $ref: /schemas/types.yaml#/definitions/uint32
367    description: |
368      Required for systems that have an "enable-method" property value of
369      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
370
371      This includes the following SoCs: |
372      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
373      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
374
375      The secondary-boot-reg property is a u32 value that specifies the
376      physical address of the register used to request the ROM holding pen
377      code release a secondary CPU. The value written to the register is
378      formed by encoding the target CPU id into the low bits of the
379      physical start address it should jump to.
380
381if:
382  # If the enable-method property contains one of those values
383  properties:
384    enable-method:
385      contains:
386        enum:
387          - brcm,bcm11351-cpu-method
388          - brcm,bcm23550
389          - brcm,bcm-nsp-smp
390  # and if enable-method is present
391  required:
392    - enable-method
393
394then:
395  required:
396    - secondary-boot-reg
397
398required:
399  - device_type
400  - reg
401  - compatible
402
403dependencies:
404  rockchip,pmu: [enable-method]
405
406additionalProperties: true
407
408examples:
409  - |
410    cpus {
411      #size-cells = <0>;
412      #address-cells = <1>;
413
414      cpu@0 {
415        device_type = "cpu";
416        compatible = "arm,cortex-a15";
417        reg = <0x0>;
418      };
419
420      cpu@1 {
421        device_type = "cpu";
422        compatible = "arm,cortex-a15";
423        reg = <0x1>;
424      };
425
426      cpu@100 {
427        device_type = "cpu";
428        compatible = "arm,cortex-a7";
429        reg = <0x100>;
430      };
431
432      cpu@101 {
433        device_type = "cpu";
434        compatible = "arm,cortex-a7";
435        reg = <0x101>;
436      };
437    };
438
439  - |
440    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
441    cpus {
442      #size-cells = <0>;
443      #address-cells = <1>;
444
445      cpu@0 {
446        device_type = "cpu";
447        compatible = "arm,cortex-a8";
448        reg = <0x0>;
449      };
450    };
451
452  - |
453    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
454    cpus {
455      #size-cells = <0>;
456      #address-cells = <1>;
457
458      cpu@0 {
459        device_type = "cpu";
460        compatible = "arm,arm926ej-s";
461        reg = <0x0>;
462      };
463    };
464
465  - |
466    //  Example 4 (ARM Cortex-A57 64-bit system):
467    cpus {
468      #size-cells = <0>;
469      #address-cells = <2>;
470
471      cpu@0 {
472        device_type = "cpu";
473        compatible = "arm,cortex-a57";
474        reg = <0x0 0x0>;
475        enable-method = "spin-table";
476        cpu-release-addr = <0 0x20000000>;
477      };
478
479      cpu@1 {
480        device_type = "cpu";
481        compatible = "arm,cortex-a57";
482        reg = <0x0 0x1>;
483        enable-method = "spin-table";
484        cpu-release-addr = <0 0x20000000>;
485      };
486
487      cpu@100 {
488        device_type = "cpu";
489        compatible = "arm,cortex-a57";
490        reg = <0x0 0x100>;
491        enable-method = "spin-table";
492        cpu-release-addr = <0 0x20000000>;
493      };
494
495      cpu@101 {
496        device_type = "cpu";
497        compatible = "arm,cortex-a57";
498        reg = <0x0 0x101>;
499        enable-method = "spin-table";
500        cpu-release-addr = <0 0x20000000>;
501      };
502
503      cpu@10000 {
504        device_type = "cpu";
505        compatible = "arm,cortex-a57";
506        reg = <0x0 0x10000>;
507        enable-method = "spin-table";
508        cpu-release-addr = <0 0x20000000>;
509      };
510
511      cpu@10001 {
512        device_type = "cpu";
513        compatible = "arm,cortex-a57";
514        reg = <0x0 0x10001>;
515        enable-method = "spin-table";
516        cpu-release-addr = <0 0x20000000>;
517      };
518
519      cpu@10100 {
520        device_type = "cpu";
521        compatible = "arm,cortex-a57";
522        reg = <0x0 0x10100>;
523        enable-method = "spin-table";
524        cpu-release-addr = <0 0x20000000>;
525      };
526
527      cpu@10101 {
528        device_type = "cpu";
529        compatible = "arm,cortex-a57";
530        reg = <0x0 0x10101>;
531        enable-method = "spin-table";
532        cpu-release-addr = <0 0x20000000>;
533      };
534
535      cpu@100000000 {
536        device_type = "cpu";
537        compatible = "arm,cortex-a57";
538        reg = <0x1 0x0>;
539        enable-method = "spin-table";
540        cpu-release-addr = <0 0x20000000>;
541      };
542
543      cpu@100000001 {
544        device_type = "cpu";
545        compatible = "arm,cortex-a57";
546        reg = <0x1 0x1>;
547        enable-method = "spin-table";
548        cpu-release-addr = <0 0x20000000>;
549      };
550
551      cpu@100000100 {
552        device_type = "cpu";
553        compatible = "arm,cortex-a57";
554        reg = <0x1 0x100>;
555        enable-method = "spin-table";
556        cpu-release-addr = <0 0x20000000>;
557      };
558
559      cpu@100000101 {
560        device_type = "cpu";
561        compatible = "arm,cortex-a57";
562        reg = <0x1 0x101>;
563        enable-method = "spin-table";
564        cpu-release-addr = <0 0x20000000>;
565      };
566
567      cpu@100010000 {
568        device_type = "cpu";
569        compatible = "arm,cortex-a57";
570        reg = <0x1 0x10000>;
571        enable-method = "spin-table";
572        cpu-release-addr = <0 0x20000000>;
573      };
574
575      cpu@100010001 {
576        device_type = "cpu";
577        compatible = "arm,cortex-a57";
578        reg = <0x1 0x10001>;
579        enable-method = "spin-table";
580        cpu-release-addr = <0 0x20000000>;
581      };
582
583      cpu@100010100 {
584        device_type = "cpu";
585        compatible = "arm,cortex-a57";
586        reg = <0x1 0x10100>;
587        enable-method = "spin-table";
588        cpu-release-addr = <0 0x20000000>;
589      };
590
591      cpu@100010101 {
592        device_type = "cpu";
593        compatible = "arm,cortex-a57";
594        reg = <0x1 0x10101>;
595        enable-method = "spin-table";
596        cpu-release-addr = <0 0x20000000>;
597      };
598    };
599...
600