1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for OmniVision OV2722 1080p HD camera sensor. 4 * 5 * Copyright (c) 2013 Intel Corporation. All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License version 9 * 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 */ 18 19 #ifndef __OV2722_H__ 20 #define __OV2722_H__ 21 #include <linux/kernel.h> 22 #include <linux/types.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/spinlock.h> 27 #include <media/v4l2-subdev.h> 28 #include <media/v4l2-device.h> 29 #include <linux/v4l2-mediabus.h> 30 #include <media/media-entity.h> 31 #include <media/v4l2-ctrls.h> 32 33 #include "../include/linux/atomisp_platform.h" 34 35 #define OV2722_POWER_UP_RETRY_NUM 5 36 37 /* Defines for register writes and register array processing */ 38 #define I2C_MSG_LENGTH 0x2 39 #define I2C_RETRY_COUNT 5 40 41 #define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ 42 43 #define MAX_FMTS 1 44 45 /* 46 * focal length bits definition: 47 * bits 31-16: numerator, bits 15-0: denominator 48 */ 49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 50 51 /* 52 * current f-number bits definition: 53 * bits 31-16: numerator, bits 15-0: denominator 54 */ 55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a 56 57 /* 58 * f-number range bits definition: 59 * bits 31-24: max f-number numerator 60 * bits 23-16: max f-number denominator 61 * bits 15-8: min f-number numerator 62 * bits 7-0: min f-number denominator 63 */ 64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a 65 #define OV2720_ID 0x2720 66 #define OV2722_ID 0x2722 67 68 #define OV2722_FINE_INTG_TIME_MIN 0 69 #define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 70 #define OV2722_COARSE_INTG_TIME_MIN 1 71 #define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 72 73 /* 74 * OV2722 System control registers 75 */ 76 #define OV2722_SW_SLEEP 0x0100 77 #define OV2722_SW_RESET 0x0103 78 #define OV2722_SW_STREAM 0x0100 79 80 #define OV2722_SC_CMMN_CHIP_ID_H 0x300A 81 #define OV2722_SC_CMMN_CHIP_ID_L 0x300B 82 #define OV2722_SC_CMMN_SCCB_ID 0x300C 83 #define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ 84 85 #define OV2722_SC_CMMN_PAD_OEN0 0x3000 86 #define OV2722_SC_CMMN_PAD_OEN1 0x3001 87 #define OV2722_SC_CMMN_PAD_OEN2 0x3002 88 #define OV2722_SC_CMMN_PAD_OUT0 0x3008 89 #define OV2722_SC_CMMN_PAD_OUT1 0x3009 90 #define OV2722_SC_CMMN_PAD_OUT2 0x300D 91 #define OV2722_SC_CMMN_PAD_SEL0 0x300E 92 #define OV2722_SC_CMMN_PAD_SEL1 0x300F 93 #define OV2722_SC_CMMN_PAD_SEL2 0x3010 94 95 #define OV2722_SC_CMMN_PAD_PK 0x3011 96 #define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 97 #define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 98 99 #define OV2722_SC_CMMN_CLKRST0 0x301A 100 #define OV2722_SC_CMMN_CLKRST1 0x301B 101 #define OV2722_SC_CMMN_CLKRST2 0x301C 102 #define OV2722_SC_CMMN_CLKRST3 0x301D 103 #define OV2722_SC_CMMN_CLKRST4 0x301E 104 #define OV2722_SC_CMMN_CLKRST5 0x3005 105 #define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 106 #define OV2722_SC_CMMN_CLOCK_SEL 0x3020 107 #define OV2722_SC_SOC_CLKRST5 0x3040 108 109 #define OV2722_SC_CMMN_PLL_CTRL0 0x3034 110 #define OV2722_SC_CMMN_PLL_CTRL1 0x3035 111 #define OV2722_SC_CMMN_PLL_CTRL2 0x3039 112 #define OV2722_SC_CMMN_PLL_CTRL3 0x3037 113 #define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 114 #define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 115 #define OV2722_SC_CMMN_PLLS_CTRL0 0x303A 116 #define OV2722_SC_CMMN_PLLS_CTRL1 0x303B 117 #define OV2722_SC_CMMN_PLLS_CTRL2 0x303C 118 #define OV2722_SC_CMMN_PLLS_CTRL3 0x303D 119 120 #define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 121 #define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 122 #define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 123 #define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 124 #define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 125 #define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 126 127 #define OV2722_AEC_PK_EXPO_H 0x3500 128 #define OV2722_AEC_PK_EXPO_M 0x3501 129 #define OV2722_AEC_PK_EXPO_L 0x3502 130 #define OV2722_AEC_MANUAL_CTRL 0x3503 131 #define OV2722_AGC_ADJ_H 0x3508 132 #define OV2722_AGC_ADJ_L 0x3509 133 #define OV2722_VTS_DIFF_H 0x350c 134 #define OV2722_VTS_DIFF_L 0x350d 135 #define OV2722_GROUP_ACCESS 0x3208 136 #define OV2722_HTS_H 0x380c 137 #define OV2722_HTS_L 0x380d 138 #define OV2722_VTS_H 0x380e 139 #define OV2722_VTS_L 0x380f 140 141 #define OV2722_MWB_GAIN_R_H 0x5186 142 #define OV2722_MWB_GAIN_R_L 0x5187 143 #define OV2722_MWB_GAIN_G_H 0x5188 144 #define OV2722_MWB_GAIN_G_L 0x5189 145 #define OV2722_MWB_GAIN_B_H 0x518a 146 #define OV2722_MWB_GAIN_B_L 0x518b 147 148 #define OV2722_H_CROP_START_H 0x3800 149 #define OV2722_H_CROP_START_L 0x3801 150 #define OV2722_V_CROP_START_H 0x3802 151 #define OV2722_V_CROP_START_L 0x3803 152 #define OV2722_H_CROP_END_H 0x3804 153 #define OV2722_H_CROP_END_L 0x3805 154 #define OV2722_V_CROP_END_H 0x3806 155 #define OV2722_V_CROP_END_L 0x3807 156 #define OV2722_H_OUTSIZE_H 0x3808 157 #define OV2722_H_OUTSIZE_L 0x3809 158 #define OV2722_V_OUTSIZE_H 0x380a 159 #define OV2722_V_OUTSIZE_L 0x380b 160 161 #define OV2722_START_STREAMING 0x01 162 #define OV2722_STOP_STREAMING 0x00 163 164 struct regval_list { 165 u16 reg_num; 166 u8 value; 167 }; 168 169 struct ov2722_resolution { 170 u8 *desc; 171 const struct ov2722_reg *regs; 172 int res; 173 int width; 174 int height; 175 int fps; 176 int pix_clk_freq; 177 u32 skip_frames; 178 u16 pixels_per_line; 179 u16 lines_per_frame; 180 bool used; 181 int mipi_freq; 182 }; 183 184 struct ov2722_format { 185 u8 *desc; 186 u32 pixelformat; 187 struct ov2722_reg *regs; 188 }; 189 190 /* 191 * ov2722 device structure. 192 */ 193 struct ov2722_device { 194 struct v4l2_subdev sd; 195 struct media_pad pad; 196 struct v4l2_mbus_framefmt format; 197 struct mutex input_lock; 198 struct ov2722_resolution *res; 199 200 struct camera_sensor_platform_data *platform_data; 201 u16 pixels_per_line; 202 u16 lines_per_frame; 203 u8 type; 204 205 struct v4l2_ctrl_handler ctrl_handler; 206 struct v4l2_ctrl *link_freq; 207 }; 208 209 enum ov2722_tok_type { 210 OV2722_8BIT = 0x0001, 211 OV2722_16BIT = 0x0002, 212 OV2722_32BIT = 0x0004, 213 OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ 214 OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ 215 OV2722_TOK_MASK = 0xfff0 216 }; 217 218 /** 219 * struct ov2722_reg - MI sensor register format 220 * @type: type of the register 221 * @reg: 16-bit offset to register 222 * @val: 8/16/32-bit register value 223 * 224 * Define a structure for sensor register initialization values 225 */ 226 struct ov2722_reg { 227 enum ov2722_tok_type type; 228 u16 reg; 229 u32 val; /* @set value for read/mod/write, @mask */ 230 }; 231 232 #define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) 233 234 #define OV2722_MAX_WRITE_BUF_SIZE 30 235 236 struct ov2722_write_buffer { 237 u16 addr; 238 u8 data[OV2722_MAX_WRITE_BUF_SIZE]; 239 }; 240 241 struct ov2722_write_ctrl { 242 int index; 243 struct ov2722_write_buffer buffer; 244 }; 245 246 /* 247 * Register settings for various resolution 248 */ 249 #if 0 250 static struct ov2722_reg const ov2722_QVGA_30fps[] = { 251 {OV2722_8BIT, 0x3718, 0x10}, 252 {OV2722_8BIT, 0x3702, 0x0c}, 253 {OV2722_8BIT, 0x373a, 0x1c}, 254 {OV2722_8BIT, 0x3715, 0x01}, 255 {OV2722_8BIT, 0x3703, 0x0c}, 256 {OV2722_8BIT, 0x3705, 0x06}, 257 {OV2722_8BIT, 0x3730, 0x0e}, 258 {OV2722_8BIT, 0x3704, 0x1c}, 259 {OV2722_8BIT, 0x3f06, 0x00}, 260 {OV2722_8BIT, 0x371c, 0x00}, 261 {OV2722_8BIT, 0x371d, 0x46}, 262 {OV2722_8BIT, 0x371e, 0x00}, 263 {OV2722_8BIT, 0x371f, 0x63}, 264 {OV2722_8BIT, 0x3708, 0x61}, 265 {OV2722_8BIT, 0x3709, 0x12}, 266 {OV2722_8BIT, 0x3800, 0x01}, 267 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 268 {OV2722_8BIT, 0x3802, 0x00}, 269 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ 270 {OV2722_8BIT, 0x3804, 0x06}, 271 {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ 272 {OV2722_8BIT, 0x3806, 0x04}, 273 {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ 274 {OV2722_8BIT, 0x3808, 0x01}, 275 {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ 276 {OV2722_8BIT, 0x380a, 0x01}, 277 {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ 278 279 /* H blank timing */ 280 {OV2722_8BIT, 0x380c, 0x08}, 281 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 282 {OV2722_8BIT, 0x380e, 0x04}, 283 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 284 {OV2722_8BIT, 0x3810, 0x00}, 285 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 286 {OV2722_8BIT, 0x3812, 0x00}, 287 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 288 {OV2722_8BIT, 0x3820, 0xc0}, 289 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 290 {OV2722_8BIT, 0x3814, 0x71}, 291 {OV2722_8BIT, 0x3815, 0x71}, 292 {OV2722_8BIT, 0x3612, 0x49}, 293 {OV2722_8BIT, 0x3618, 0x00}, 294 {OV2722_8BIT, 0x3a08, 0x01}, 295 {OV2722_8BIT, 0x3a09, 0xc3}, 296 {OV2722_8BIT, 0x3a0a, 0x01}, 297 {OV2722_8BIT, 0x3a0b, 0x77}, 298 {OV2722_8BIT, 0x3a0d, 0x00}, 299 {OV2722_8BIT, 0x3a0e, 0x00}, 300 {OV2722_8BIT, 0x4520, 0x09}, 301 {OV2722_8BIT, 0x4837, 0x1b}, 302 {OV2722_8BIT, 0x3000, 0xff}, 303 {OV2722_8BIT, 0x3001, 0xff}, 304 {OV2722_8BIT, 0x3002, 0xf0}, 305 {OV2722_8BIT, 0x3600, 0x08}, 306 {OV2722_8BIT, 0x3621, 0xc0}, 307 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 308 {OV2722_8BIT, 0x3633, 0x63}, 309 {OV2722_8BIT, 0x3634, 0x24}, 310 {OV2722_8BIT, 0x3f01, 0x0c}, 311 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 312 {OV2722_8BIT, 0x3614, 0xf0}, 313 {OV2722_8BIT, 0x3630, 0x2d}, 314 {OV2722_8BIT, 0x370b, 0x62}, 315 {OV2722_8BIT, 0x3706, 0x61}, 316 {OV2722_8BIT, 0x4000, 0x02}, 317 {OV2722_8BIT, 0x4002, 0xc5}, 318 {OV2722_8BIT, 0x4005, 0x08}, 319 {OV2722_8BIT, 0x404f, 0x84}, 320 {OV2722_8BIT, 0x4051, 0x00}, 321 {OV2722_8BIT, 0x5000, 0xff}, 322 {OV2722_8BIT, 0x3a18, 0x00}, 323 {OV2722_8BIT, 0x3a19, 0x80}, 324 {OV2722_8BIT, 0x4521, 0x00}, 325 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 326 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 327 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 328 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 329 {OV2722_8BIT, 0x370c, 0x0c}, 330 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 331 {OV2722_8BIT, 0x3035, 0x00}, 332 {OV2722_8BIT, 0x3036, 0x26}, 333 {OV2722_8BIT, 0x3037, 0xa1}, 334 {OV2722_8BIT, 0x303e, 0x19}, 335 {OV2722_8BIT, 0x3038, 0x06}, 336 {OV2722_8BIT, 0x3018, 0x04}, 337 338 /* Added for power optimization */ 339 {OV2722_8BIT, 0x3000, 0x00}, 340 {OV2722_8BIT, 0x3001, 0x00}, 341 {OV2722_8BIT, 0x3002, 0x00}, 342 {OV2722_8BIT, 0x3a0f, 0x40}, 343 {OV2722_8BIT, 0x3a10, 0x38}, 344 {OV2722_8BIT, 0x3a1b, 0x48}, 345 {OV2722_8BIT, 0x3a1e, 0x30}, 346 {OV2722_8BIT, 0x3a11, 0x90}, 347 {OV2722_8BIT, 0x3a1f, 0x10}, 348 {OV2722_8BIT, 0x3011, 0x22}, 349 {OV2722_8BIT, 0x3a00, 0x58}, 350 {OV2722_8BIT, 0x3503, 0x17}, 351 {OV2722_8BIT, 0x3500, 0x00}, 352 {OV2722_8BIT, 0x3501, 0x46}, 353 {OV2722_8BIT, 0x3502, 0x00}, 354 {OV2722_8BIT, 0x3508, 0x00}, 355 {OV2722_8BIT, 0x3509, 0x10}, 356 {OV2722_TOK_TERM, 0, 0}, 357 358 }; 359 360 static struct ov2722_reg const ov2722_480P_30fps[] = { 361 {OV2722_8BIT, 0x3718, 0x10}, 362 {OV2722_8BIT, 0x3702, 0x18}, 363 {OV2722_8BIT, 0x373a, 0x3c}, 364 {OV2722_8BIT, 0x3715, 0x01}, 365 {OV2722_8BIT, 0x3703, 0x1d}, 366 {OV2722_8BIT, 0x3705, 0x12}, 367 {OV2722_8BIT, 0x3730, 0x1f}, 368 {OV2722_8BIT, 0x3704, 0x3f}, 369 {OV2722_8BIT, 0x3f06, 0x1d}, 370 {OV2722_8BIT, 0x371c, 0x00}, 371 {OV2722_8BIT, 0x371d, 0x83}, 372 {OV2722_8BIT, 0x371e, 0x00}, 373 {OV2722_8BIT, 0x371f, 0xbd}, 374 {OV2722_8BIT, 0x3708, 0x63}, 375 {OV2722_8BIT, 0x3709, 0x52}, 376 {OV2722_8BIT, 0x3800, 0x00}, 377 {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ 378 {OV2722_8BIT, 0x3802, 0x00}, 379 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 380 {OV2722_8BIT, 0x3804, 0x06}, 381 {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ 382 {OV2722_8BIT, 0x3806, 0x04}, 383 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 384 {OV2722_8BIT, 0x3808, 0x02}, 385 {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ 386 {OV2722_8BIT, 0x380a, 0x01}, 387 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 388 389 /* H blank timing */ 390 {OV2722_8BIT, 0x380c, 0x08}, 391 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 392 {OV2722_8BIT, 0x380e, 0x04}, 393 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 394 {OV2722_8BIT, 0x3810, 0x00}, 395 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 396 {OV2722_8BIT, 0x3812, 0x00}, 397 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 398 {OV2722_8BIT, 0x3820, 0x80}, 399 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 400 {OV2722_8BIT, 0x3814, 0x31}, 401 {OV2722_8BIT, 0x3815, 0x31}, 402 {OV2722_8BIT, 0x3612, 0x4b}, 403 {OV2722_8BIT, 0x3618, 0x04}, 404 {OV2722_8BIT, 0x3a08, 0x02}, 405 {OV2722_8BIT, 0x3a09, 0x67}, 406 {OV2722_8BIT, 0x3a0a, 0x02}, 407 {OV2722_8BIT, 0x3a0b, 0x00}, 408 {OV2722_8BIT, 0x3a0d, 0x00}, 409 {OV2722_8BIT, 0x3a0e, 0x00}, 410 {OV2722_8BIT, 0x4520, 0x0a}, 411 {OV2722_8BIT, 0x4837, 0x1b}, 412 {OV2722_8BIT, 0x3000, 0xff}, 413 {OV2722_8BIT, 0x3001, 0xff}, 414 {OV2722_8BIT, 0x3002, 0xf0}, 415 {OV2722_8BIT, 0x3600, 0x08}, 416 {OV2722_8BIT, 0x3621, 0xc0}, 417 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 418 {OV2722_8BIT, 0x3633, 0x63}, 419 {OV2722_8BIT, 0x3634, 0x24}, 420 {OV2722_8BIT, 0x3f01, 0x0c}, 421 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 422 {OV2722_8BIT, 0x3614, 0xf0}, 423 {OV2722_8BIT, 0x3630, 0x2d}, 424 {OV2722_8BIT, 0x370b, 0x62}, 425 {OV2722_8BIT, 0x3706, 0x61}, 426 {OV2722_8BIT, 0x4000, 0x02}, 427 {OV2722_8BIT, 0x4002, 0xc5}, 428 {OV2722_8BIT, 0x4005, 0x08}, 429 {OV2722_8BIT, 0x404f, 0x84}, 430 {OV2722_8BIT, 0x4051, 0x00}, 431 {OV2722_8BIT, 0x5000, 0xff}, 432 {OV2722_8BIT, 0x3a18, 0x00}, 433 {OV2722_8BIT, 0x3a19, 0x80}, 434 {OV2722_8BIT, 0x4521, 0x00}, 435 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 436 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 437 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 438 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 439 {OV2722_8BIT, 0x370c, 0x0c}, 440 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 441 {OV2722_8BIT, 0x3035, 0x00}, 442 {OV2722_8BIT, 0x3036, 0x26}, 443 {OV2722_8BIT, 0x3037, 0xa1}, 444 {OV2722_8BIT, 0x303e, 0x19}, 445 {OV2722_8BIT, 0x3038, 0x06}, 446 {OV2722_8BIT, 0x3018, 0x04}, 447 448 /* Added for power optimization */ 449 {OV2722_8BIT, 0x3000, 0x00}, 450 {OV2722_8BIT, 0x3001, 0x00}, 451 {OV2722_8BIT, 0x3002, 0x00}, 452 {OV2722_8BIT, 0x3a0f, 0x40}, 453 {OV2722_8BIT, 0x3a10, 0x38}, 454 {OV2722_8BIT, 0x3a1b, 0x48}, 455 {OV2722_8BIT, 0x3a1e, 0x30}, 456 {OV2722_8BIT, 0x3a11, 0x90}, 457 {OV2722_8BIT, 0x3a1f, 0x10}, 458 {OV2722_8BIT, 0x3011, 0x22}, 459 {OV2722_8BIT, 0x3a00, 0x58}, 460 {OV2722_8BIT, 0x3503, 0x17}, 461 {OV2722_8BIT, 0x3500, 0x00}, 462 {OV2722_8BIT, 0x3501, 0x46}, 463 {OV2722_8BIT, 0x3502, 0x00}, 464 {OV2722_8BIT, 0x3508, 0x00}, 465 {OV2722_8BIT, 0x3509, 0x10}, 466 {OV2722_TOK_TERM, 0, 0}, 467 }; 468 469 static struct ov2722_reg const ov2722_VGA_30fps[] = { 470 {OV2722_8BIT, 0x3718, 0x10}, 471 {OV2722_8BIT, 0x3702, 0x18}, 472 {OV2722_8BIT, 0x373a, 0x3c}, 473 {OV2722_8BIT, 0x3715, 0x01}, 474 {OV2722_8BIT, 0x3703, 0x1d}, 475 {OV2722_8BIT, 0x3705, 0x12}, 476 {OV2722_8BIT, 0x3730, 0x1f}, 477 {OV2722_8BIT, 0x3704, 0x3f}, 478 {OV2722_8BIT, 0x3f06, 0x1d}, 479 {OV2722_8BIT, 0x371c, 0x00}, 480 {OV2722_8BIT, 0x371d, 0x83}, 481 {OV2722_8BIT, 0x371e, 0x00}, 482 {OV2722_8BIT, 0x371f, 0xbd}, 483 {OV2722_8BIT, 0x3708, 0x63}, 484 {OV2722_8BIT, 0x3709, 0x52}, 485 {OV2722_8BIT, 0x3800, 0x01}, 486 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 487 {OV2722_8BIT, 0x3802, 0x00}, 488 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 489 {OV2722_8BIT, 0x3804, 0x06}, 490 {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ 491 {OV2722_8BIT, 0x3806, 0x04}, 492 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 493 {OV2722_8BIT, 0x3808, 0x02}, 494 {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ 495 {OV2722_8BIT, 0x380a, 0x01}, 496 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 497 498 /* H blank timing */ 499 {OV2722_8BIT, 0x380c, 0x08}, 500 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 501 {OV2722_8BIT, 0x380e, 0x04}, 502 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 503 {OV2722_8BIT, 0x3810, 0x00}, 504 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 505 {OV2722_8BIT, 0x3812, 0x00}, 506 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 507 {OV2722_8BIT, 0x3820, 0x80}, 508 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 509 {OV2722_8BIT, 0x3814, 0x31}, 510 {OV2722_8BIT, 0x3815, 0x31}, 511 {OV2722_8BIT, 0x3612, 0x4b}, 512 {OV2722_8BIT, 0x3618, 0x04}, 513 {OV2722_8BIT, 0x3a08, 0x02}, 514 {OV2722_8BIT, 0x3a09, 0x67}, 515 {OV2722_8BIT, 0x3a0a, 0x02}, 516 {OV2722_8BIT, 0x3a0b, 0x00}, 517 {OV2722_8BIT, 0x3a0d, 0x00}, 518 {OV2722_8BIT, 0x3a0e, 0x00}, 519 {OV2722_8BIT, 0x4520, 0x0a}, 520 {OV2722_8BIT, 0x4837, 0x29}, 521 {OV2722_8BIT, 0x3000, 0xff}, 522 {OV2722_8BIT, 0x3001, 0xff}, 523 {OV2722_8BIT, 0x3002, 0xf0}, 524 {OV2722_8BIT, 0x3600, 0x08}, 525 {OV2722_8BIT, 0x3621, 0xc0}, 526 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 527 {OV2722_8BIT, 0x3633, 0x63}, 528 {OV2722_8BIT, 0x3634, 0x24}, 529 {OV2722_8BIT, 0x3f01, 0x0c}, 530 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 531 {OV2722_8BIT, 0x3614, 0xf0}, 532 {OV2722_8BIT, 0x3630, 0x2d}, 533 {OV2722_8BIT, 0x370b, 0x62}, 534 {OV2722_8BIT, 0x3706, 0x61}, 535 {OV2722_8BIT, 0x4000, 0x02}, 536 {OV2722_8BIT, 0x4002, 0xc5}, 537 {OV2722_8BIT, 0x4005, 0x08}, 538 {OV2722_8BIT, 0x404f, 0x84}, 539 {OV2722_8BIT, 0x4051, 0x00}, 540 {OV2722_8BIT, 0x5000, 0xff}, 541 {OV2722_8BIT, 0x3a18, 0x00}, 542 {OV2722_8BIT, 0x3a19, 0x80}, 543 {OV2722_8BIT, 0x4521, 0x00}, 544 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 545 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 546 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 547 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 548 {OV2722_8BIT, 0x370c, 0x0c}, 549 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 550 {OV2722_8BIT, 0x3035, 0x00}, 551 {OV2722_8BIT, 0x3036, 0x26}, 552 {OV2722_8BIT, 0x3037, 0xa1}, 553 {OV2722_8BIT, 0x303e, 0x19}, 554 {OV2722_8BIT, 0x3038, 0x06}, 555 {OV2722_8BIT, 0x3018, 0x04}, 556 557 /* Added for power optimization */ 558 {OV2722_8BIT, 0x3000, 0x00}, 559 {OV2722_8BIT, 0x3001, 0x00}, 560 {OV2722_8BIT, 0x3002, 0x00}, 561 {OV2722_8BIT, 0x3a0f, 0x40}, 562 {OV2722_8BIT, 0x3a10, 0x38}, 563 {OV2722_8BIT, 0x3a1b, 0x48}, 564 {OV2722_8BIT, 0x3a1e, 0x30}, 565 {OV2722_8BIT, 0x3a11, 0x90}, 566 {OV2722_8BIT, 0x3a1f, 0x10}, 567 {OV2722_8BIT, 0x3011, 0x22}, 568 {OV2722_8BIT, 0x3a00, 0x58}, 569 {OV2722_8BIT, 0x3503, 0x17}, 570 {OV2722_8BIT, 0x3500, 0x00}, 571 {OV2722_8BIT, 0x3501, 0x46}, 572 {OV2722_8BIT, 0x3502, 0x00}, 573 {OV2722_8BIT, 0x3508, 0x00}, 574 {OV2722_8BIT, 0x3509, 0x10}, 575 {OV2722_TOK_TERM, 0, 0}, 576 }; 577 #endif 578 579 static struct ov2722_reg const ov2722_1632_1092_30fps[] = { 580 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 581 a whole frame complete.(vblank) */ 582 {OV2722_8BIT, 0x3718, 0x10}, 583 {OV2722_8BIT, 0x3702, 0x24}, 584 {OV2722_8BIT, 0x373a, 0x60}, 585 {OV2722_8BIT, 0x3715, 0x01}, 586 {OV2722_8BIT, 0x3703, 0x2e}, 587 {OV2722_8BIT, 0x3705, 0x10}, 588 {OV2722_8BIT, 0x3730, 0x30}, 589 {OV2722_8BIT, 0x3704, 0x62}, 590 {OV2722_8BIT, 0x3f06, 0x3a}, 591 {OV2722_8BIT, 0x371c, 0x00}, 592 {OV2722_8BIT, 0x371d, 0xc4}, 593 {OV2722_8BIT, 0x371e, 0x01}, 594 {OV2722_8BIT, 0x371f, 0x0d}, 595 {OV2722_8BIT, 0x3708, 0x61}, 596 {OV2722_8BIT, 0x3709, 0x12}, 597 {OV2722_8BIT, 0x3800, 0x00}, 598 {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ 599 {OV2722_8BIT, 0x3802, 0x00}, 600 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 601 {OV2722_8BIT, 0x3804, 0x07}, 602 {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ 603 {OV2722_8BIT, 0x3806, 0x04}, 604 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 605 606 {OV2722_8BIT, 0x3808, 0x06}, 607 {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ 608 {OV2722_8BIT, 0x380a, 0x04}, 609 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 610 {OV2722_8BIT, 0x380c, 0x08}, 611 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 612 {OV2722_8BIT, 0x380e, 0x04}, 613 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 614 {OV2722_8BIT, 0x3810, 0x00}, 615 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 616 {OV2722_8BIT, 0x3812, 0x00}, 617 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 618 {OV2722_8BIT, 0x3820, 0x80}, 619 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 620 {OV2722_8BIT, 0x3814, 0x11}, 621 {OV2722_8BIT, 0x3815, 0x11}, 622 {OV2722_8BIT, 0x3612, 0x0b}, 623 {OV2722_8BIT, 0x3618, 0x04}, 624 {OV2722_8BIT, 0x3a08, 0x01}, 625 {OV2722_8BIT, 0x3a09, 0x50}, 626 {OV2722_8BIT, 0x3a0a, 0x01}, 627 {OV2722_8BIT, 0x3a0b, 0x18}, 628 {OV2722_8BIT, 0x3a0d, 0x03}, 629 {OV2722_8BIT, 0x3a0e, 0x03}, 630 {OV2722_8BIT, 0x4520, 0x00}, 631 {OV2722_8BIT, 0x4837, 0x1b}, 632 {OV2722_8BIT, 0x3600, 0x08}, 633 {OV2722_8BIT, 0x3621, 0xc0}, 634 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 635 {OV2722_8BIT, 0x3633, 0x23}, 636 {OV2722_8BIT, 0x3634, 0x54}, 637 {OV2722_8BIT, 0x3f01, 0x0c}, 638 {OV2722_8BIT, 0x5001, 0xc1}, 639 {OV2722_8BIT, 0x3614, 0xf0}, 640 {OV2722_8BIT, 0x3630, 0x2d}, 641 {OV2722_8BIT, 0x370b, 0x62}, 642 {OV2722_8BIT, 0x3706, 0x61}, 643 {OV2722_8BIT, 0x4000, 0x02}, 644 {OV2722_8BIT, 0x4002, 0xc5}, 645 {OV2722_8BIT, 0x4005, 0x08}, 646 {OV2722_8BIT, 0x404f, 0x84}, 647 {OV2722_8BIT, 0x4051, 0x00}, 648 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 649 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 650 {OV2722_8BIT, 0x3a18, 0x00}, 651 {OV2722_8BIT, 0x3a19, 0x80}, 652 {OV2722_8BIT, 0x4521, 0x00}, 653 {OV2722_8BIT, 0x5183, 0xb0}, 654 {OV2722_8BIT, 0x5184, 0xb0}, 655 {OV2722_8BIT, 0x5185, 0xb0}, 656 {OV2722_8BIT, 0x370c, 0x0c}, 657 {OV2722_8BIT, 0x3035, 0x00}, 658 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 659 {OV2722_8BIT, 0x3037, 0xa1}, 660 {OV2722_8BIT, 0x303e, 0x19}, 661 {OV2722_8BIT, 0x3038, 0x06}, 662 {OV2722_8BIT, 0x3018, 0x04}, 663 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 664 {OV2722_8BIT, 0x3001, 0x00}, 665 {OV2722_8BIT, 0x3002, 0x00}, 666 {OV2722_8BIT, 0x3a0f, 0x40}, 667 {OV2722_8BIT, 0x3a10, 0x38}, 668 {OV2722_8BIT, 0x3a1b, 0x48}, 669 {OV2722_8BIT, 0x3a1e, 0x30}, 670 {OV2722_8BIT, 0x3a11, 0x90}, 671 {OV2722_8BIT, 0x3a1f, 0x10}, 672 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 673 {OV2722_8BIT, 0x3500, 0x00}, 674 {OV2722_8BIT, 0x3501, 0x3F}, 675 {OV2722_8BIT, 0x3502, 0x00}, 676 {OV2722_8BIT, 0x3508, 0x00}, 677 {OV2722_8BIT, 0x3509, 0x00}, 678 {OV2722_TOK_TERM, 0, 0} 679 }; 680 681 static struct ov2722_reg const ov2722_1452_1092_30fps[] = { 682 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 683 a whole frame complete.(vblank) */ 684 {OV2722_8BIT, 0x3718, 0x10}, 685 {OV2722_8BIT, 0x3702, 0x24}, 686 {OV2722_8BIT, 0x373a, 0x60}, 687 {OV2722_8BIT, 0x3715, 0x01}, 688 {OV2722_8BIT, 0x3703, 0x2e}, 689 {OV2722_8BIT, 0x3705, 0x10}, 690 {OV2722_8BIT, 0x3730, 0x30}, 691 {OV2722_8BIT, 0x3704, 0x62}, 692 {OV2722_8BIT, 0x3f06, 0x3a}, 693 {OV2722_8BIT, 0x371c, 0x00}, 694 {OV2722_8BIT, 0x371d, 0xc4}, 695 {OV2722_8BIT, 0x371e, 0x01}, 696 {OV2722_8BIT, 0x371f, 0x0d}, 697 {OV2722_8BIT, 0x3708, 0x61}, 698 {OV2722_8BIT, 0x3709, 0x12}, 699 {OV2722_8BIT, 0x3800, 0x00}, 700 {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ 701 {OV2722_8BIT, 0x3802, 0x00}, 702 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 703 {OV2722_8BIT, 0x3804, 0x06}, 704 {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ 705 {OV2722_8BIT, 0x3806, 0x04}, 706 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 707 {OV2722_8BIT, 0x3808, 0x05}, 708 {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ 709 {OV2722_8BIT, 0x380a, 0x04}, 710 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 711 {OV2722_8BIT, 0x380c, 0x08}, 712 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 713 {OV2722_8BIT, 0x380e, 0x04}, 714 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 715 {OV2722_8BIT, 0x3810, 0x00}, 716 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 717 {OV2722_8BIT, 0x3812, 0x00}, 718 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 719 {OV2722_8BIT, 0x3820, 0x80}, 720 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 721 {OV2722_8BIT, 0x3814, 0x11}, 722 {OV2722_8BIT, 0x3815, 0x11}, 723 {OV2722_8BIT, 0x3612, 0x0b}, 724 {OV2722_8BIT, 0x3618, 0x04}, 725 {OV2722_8BIT, 0x3a08, 0x01}, 726 {OV2722_8BIT, 0x3a09, 0x50}, 727 {OV2722_8BIT, 0x3a0a, 0x01}, 728 {OV2722_8BIT, 0x3a0b, 0x18}, 729 {OV2722_8BIT, 0x3a0d, 0x03}, 730 {OV2722_8BIT, 0x3a0e, 0x03}, 731 {OV2722_8BIT, 0x4520, 0x00}, 732 {OV2722_8BIT, 0x4837, 0x1b}, 733 {OV2722_8BIT, 0x3600, 0x08}, 734 {OV2722_8BIT, 0x3621, 0xc0}, 735 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 736 {OV2722_8BIT, 0x3633, 0x23}, 737 {OV2722_8BIT, 0x3634, 0x54}, 738 {OV2722_8BIT, 0x3f01, 0x0c}, 739 {OV2722_8BIT, 0x5001, 0xc1}, 740 {OV2722_8BIT, 0x3614, 0xf0}, 741 {OV2722_8BIT, 0x3630, 0x2d}, 742 {OV2722_8BIT, 0x370b, 0x62}, 743 {OV2722_8BIT, 0x3706, 0x61}, 744 {OV2722_8BIT, 0x4000, 0x02}, 745 {OV2722_8BIT, 0x4002, 0xc5}, 746 {OV2722_8BIT, 0x4005, 0x08}, 747 {OV2722_8BIT, 0x404f, 0x84}, 748 {OV2722_8BIT, 0x4051, 0x00}, 749 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 750 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 751 {OV2722_8BIT, 0x3a18, 0x00}, 752 {OV2722_8BIT, 0x3a19, 0x80}, 753 {OV2722_8BIT, 0x4521, 0x00}, 754 {OV2722_8BIT, 0x5183, 0xb0}, 755 {OV2722_8BIT, 0x5184, 0xb0}, 756 {OV2722_8BIT, 0x5185, 0xb0}, 757 {OV2722_8BIT, 0x370c, 0x0c}, 758 {OV2722_8BIT, 0x3035, 0x00}, 759 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 760 {OV2722_8BIT, 0x3037, 0xa1}, 761 {OV2722_8BIT, 0x303e, 0x19}, 762 {OV2722_8BIT, 0x3038, 0x06}, 763 {OV2722_8BIT, 0x3018, 0x04}, 764 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 765 {OV2722_8BIT, 0x3001, 0x00}, 766 {OV2722_8BIT, 0x3002, 0x00}, 767 {OV2722_8BIT, 0x3a0f, 0x40}, 768 {OV2722_8BIT, 0x3a10, 0x38}, 769 {OV2722_8BIT, 0x3a1b, 0x48}, 770 {OV2722_8BIT, 0x3a1e, 0x30}, 771 {OV2722_8BIT, 0x3a11, 0x90}, 772 {OV2722_8BIT, 0x3a1f, 0x10}, 773 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 774 {OV2722_8BIT, 0x3500, 0x00}, 775 {OV2722_8BIT, 0x3501, 0x3F}, 776 {OV2722_8BIT, 0x3502, 0x00}, 777 {OV2722_8BIT, 0x3508, 0x00}, 778 {OV2722_8BIT, 0x3509, 0x00}, 779 {OV2722_TOK_TERM, 0, 0} 780 }; 781 782 #if 0 783 static struct ov2722_reg const ov2722_1M3_30fps[] = { 784 {OV2722_8BIT, 0x3718, 0x10}, 785 {OV2722_8BIT, 0x3702, 0x24}, 786 {OV2722_8BIT, 0x373a, 0x60}, 787 {OV2722_8BIT, 0x3715, 0x01}, 788 {OV2722_8BIT, 0x3703, 0x2e}, 789 {OV2722_8BIT, 0x3705, 0x10}, 790 {OV2722_8BIT, 0x3730, 0x30}, 791 {OV2722_8BIT, 0x3704, 0x62}, 792 {OV2722_8BIT, 0x3f06, 0x3a}, 793 {OV2722_8BIT, 0x371c, 0x00}, 794 {OV2722_8BIT, 0x371d, 0xc4}, 795 {OV2722_8BIT, 0x371e, 0x01}, 796 {OV2722_8BIT, 0x371f, 0x0d}, 797 {OV2722_8BIT, 0x3708, 0x61}, 798 {OV2722_8BIT, 0x3709, 0x12}, 799 {OV2722_8BIT, 0x3800, 0x01}, 800 {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ 801 {OV2722_8BIT, 0x3802, 0x00}, 802 {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ 803 {OV2722_8BIT, 0x3804, 0x06}, 804 {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ 805 {OV2722_8BIT, 0x3806, 0x04}, 806 {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ 807 {OV2722_8BIT, 0x3808, 0x05}, 808 {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ 809 {OV2722_8BIT, 0x380a, 0x04}, 810 {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ 811 812 /* H blank timing */ 813 {OV2722_8BIT, 0x380c, 0x08}, 814 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 815 {OV2722_8BIT, 0x380e, 0x04}, 816 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 817 {OV2722_8BIT, 0x3810, 0x00}, 818 {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ 819 {OV2722_8BIT, 0x3812, 0x00}, 820 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 821 {OV2722_8BIT, 0x3820, 0x80}, 822 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ 823 {OV2722_8BIT, 0x3814, 0x11}, 824 {OV2722_8BIT, 0x3815, 0x11}, 825 {OV2722_8BIT, 0x3612, 0x0b}, 826 {OV2722_8BIT, 0x3618, 0x04}, 827 {OV2722_8BIT, 0x3a08, 0x01}, 828 {OV2722_8BIT, 0x3a09, 0x50}, 829 {OV2722_8BIT, 0x3a0a, 0x01}, 830 {OV2722_8BIT, 0x3a0b, 0x18}, 831 {OV2722_8BIT, 0x3a0d, 0x03}, 832 {OV2722_8BIT, 0x3a0e, 0x03}, 833 {OV2722_8BIT, 0x4520, 0x00}, 834 {OV2722_8BIT, 0x4837, 0x1b}, 835 {OV2722_8BIT, 0x3000, 0xff}, 836 {OV2722_8BIT, 0x3001, 0xff}, 837 {OV2722_8BIT, 0x3002, 0xf0}, 838 {OV2722_8BIT, 0x3600, 0x08}, 839 {OV2722_8BIT, 0x3621, 0xc0}, 840 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 841 {OV2722_8BIT, 0x3633, 0x23}, 842 {OV2722_8BIT, 0x3634, 0x54}, 843 {OV2722_8BIT, 0x3f01, 0x0c}, 844 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 845 {OV2722_8BIT, 0x3614, 0xf0}, 846 {OV2722_8BIT, 0x3630, 0x2d}, 847 {OV2722_8BIT, 0x370b, 0x62}, 848 {OV2722_8BIT, 0x3706, 0x61}, 849 {OV2722_8BIT, 0x4000, 0x02}, 850 {OV2722_8BIT, 0x4002, 0xc5}, 851 {OV2722_8BIT, 0x4005, 0x08}, 852 {OV2722_8BIT, 0x404f, 0x84}, 853 {OV2722_8BIT, 0x4051, 0x00}, 854 {OV2722_8BIT, 0x5000, 0xcf}, 855 {OV2722_8BIT, 0x3a18, 0x00}, 856 {OV2722_8BIT, 0x3a19, 0x80}, 857 {OV2722_8BIT, 0x4521, 0x00}, 858 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 859 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 860 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 861 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 862 {OV2722_8BIT, 0x370c, 0x0c}, 863 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 864 {OV2722_8BIT, 0x3035, 0x00}, 865 {OV2722_8BIT, 0x3036, 0x26}, 866 {OV2722_8BIT, 0x3037, 0xa1}, 867 {OV2722_8BIT, 0x303e, 0x19}, 868 {OV2722_8BIT, 0x3038, 0x06}, 869 {OV2722_8BIT, 0x3018, 0x04}, 870 871 /* Added for power optimization */ 872 {OV2722_8BIT, 0x3000, 0x00}, 873 {OV2722_8BIT, 0x3001, 0x00}, 874 {OV2722_8BIT, 0x3002, 0x00}, 875 {OV2722_8BIT, 0x3a0f, 0x40}, 876 {OV2722_8BIT, 0x3a10, 0x38}, 877 {OV2722_8BIT, 0x3a1b, 0x48}, 878 {OV2722_8BIT, 0x3a1e, 0x30}, 879 {OV2722_8BIT, 0x3a11, 0x90}, 880 {OV2722_8BIT, 0x3a1f, 0x10}, 881 {OV2722_8BIT, 0x3503, 0x17}, 882 {OV2722_8BIT, 0x3500, 0x00}, 883 {OV2722_8BIT, 0x3501, 0x46}, 884 {OV2722_8BIT, 0x3502, 0x00}, 885 {OV2722_8BIT, 0x3508, 0x00}, 886 {OV2722_8BIT, 0x3509, 0x10}, 887 {OV2722_TOK_TERM, 0, 0}, 888 }; 889 #endif 890 891 static struct ov2722_reg const ov2722_1080p_30fps[] = { 892 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole 893 frame complete.(vblank) */ 894 {OV2722_8BIT, 0x3718, 0x10}, 895 {OV2722_8BIT, 0x3702, 0x24}, 896 {OV2722_8BIT, 0x373a, 0x60}, 897 {OV2722_8BIT, 0x3715, 0x01}, 898 {OV2722_8BIT, 0x3703, 0x2e}, 899 {OV2722_8BIT, 0x3705, 0x2b}, 900 {OV2722_8BIT, 0x3730, 0x30}, 901 {OV2722_8BIT, 0x3704, 0x62}, 902 {OV2722_8BIT, 0x3f06, 0x3a}, 903 {OV2722_8BIT, 0x371c, 0x00}, 904 {OV2722_8BIT, 0x371d, 0xc4}, 905 {OV2722_8BIT, 0x371e, 0x01}, 906 {OV2722_8BIT, 0x371f, 0x28}, 907 {OV2722_8BIT, 0x3708, 0x61}, 908 {OV2722_8BIT, 0x3709, 0x12}, 909 {OV2722_8BIT, 0x3800, 0x00}, 910 {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ 911 {OV2722_8BIT, 0x3802, 0x00}, 912 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 913 {OV2722_8BIT, 0x3804, 0x07}, 914 {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ 915 {OV2722_8BIT, 0x3806, 0x04}, 916 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 917 {OV2722_8BIT, 0x3808, 0x07}, 918 {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ 919 {OV2722_8BIT, 0x380a, 0x04}, 920 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 921 {OV2722_8BIT, 0x380c, 0x08}, 922 {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ 923 {OV2722_8BIT, 0x380e, 0x04}, 924 {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ 925 {OV2722_8BIT, 0x3810, 0x00}, 926 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 927 {OV2722_8BIT, 0x3812, 0x00}, 928 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 929 {OV2722_8BIT, 0x3820, 0x80}, 930 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 931 {OV2722_8BIT, 0x3814, 0x11}, 932 {OV2722_8BIT, 0x3815, 0x11}, 933 {OV2722_8BIT, 0x3612, 0x4b}, 934 {OV2722_8BIT, 0x3618, 0x04}, 935 {OV2722_8BIT, 0x3a08, 0x01}, 936 {OV2722_8BIT, 0x3a09, 0x50}, 937 {OV2722_8BIT, 0x3a0a, 0x01}, 938 {OV2722_8BIT, 0x3a0b, 0x18}, 939 {OV2722_8BIT, 0x3a0d, 0x03}, 940 {OV2722_8BIT, 0x3a0e, 0x03}, 941 {OV2722_8BIT, 0x4520, 0x00}, 942 {OV2722_8BIT, 0x4837, 0x1b}, 943 {OV2722_8BIT, 0x3000, 0xff}, 944 {OV2722_8BIT, 0x3001, 0xff}, 945 {OV2722_8BIT, 0x3002, 0xf0}, 946 {OV2722_8BIT, 0x3600, 0x08}, 947 {OV2722_8BIT, 0x3621, 0xc0}, 948 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 949 {OV2722_8BIT, 0x3633, 0x63}, 950 {OV2722_8BIT, 0x3634, 0x24}, 951 {OV2722_8BIT, 0x3f01, 0x0c}, 952 {OV2722_8BIT, 0x5001, 0xc1}, 953 {OV2722_8BIT, 0x3614, 0xf0}, 954 {OV2722_8BIT, 0x3630, 0x2d}, 955 {OV2722_8BIT, 0x370b, 0x62}, 956 {OV2722_8BIT, 0x3706, 0x61}, 957 {OV2722_8BIT, 0x4000, 0x02}, 958 {OV2722_8BIT, 0x4002, 0xc5}, 959 {OV2722_8BIT, 0x4005, 0x08}, 960 {OV2722_8BIT, 0x404f, 0x84}, 961 {OV2722_8BIT, 0x4051, 0x00}, 962 {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ 963 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 964 {OV2722_8BIT, 0x3a18, 0x00}, 965 {OV2722_8BIT, 0x3a19, 0x80}, 966 {OV2722_8BIT, 0x3503, 0x17}, 967 {OV2722_8BIT, 0x4521, 0x00}, 968 {OV2722_8BIT, 0x5183, 0xb0}, 969 {OV2722_8BIT, 0x5184, 0xb0}, 970 {OV2722_8BIT, 0x5185, 0xb0}, 971 {OV2722_8BIT, 0x370c, 0x0c}, 972 {OV2722_8BIT, 0x3035, 0x00}, 973 {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ 974 {OV2722_8BIT, 0x3037, 0xa1}, 975 {OV2722_8BIT, 0x303e, 0x19}, 976 {OV2722_8BIT, 0x3038, 0x06}, 977 {OV2722_8BIT, 0x3018, 0x04}, 978 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 979 {OV2722_8BIT, 0x3001, 0x00}, 980 {OV2722_8BIT, 0x3002, 0x00}, 981 {OV2722_8BIT, 0x3a0f, 0x40}, 982 {OV2722_8BIT, 0x3a10, 0x38}, 983 {OV2722_8BIT, 0x3a1b, 0x48}, 984 {OV2722_8BIT, 0x3a1e, 0x30}, 985 {OV2722_8BIT, 0x3a11, 0x90}, 986 {OV2722_8BIT, 0x3a1f, 0x10}, 987 {OV2722_8BIT, 0x3011, 0x22}, 988 {OV2722_8BIT, 0x3500, 0x00}, 989 {OV2722_8BIT, 0x3501, 0x3F}, 990 {OV2722_8BIT, 0x3502, 0x00}, 991 {OV2722_8BIT, 0x3508, 0x00}, 992 {OV2722_8BIT, 0x3509, 0x00}, 993 {OV2722_TOK_TERM, 0, 0} 994 }; 995 996 #if 0 /* Currently unused */ 997 static struct ov2722_reg const ov2722_720p_30fps[] = { 998 {OV2722_8BIT, 0x3021, 0x03}, 999 {OV2722_8BIT, 0x3718, 0x10}, 1000 {OV2722_8BIT, 0x3702, 0x24}, 1001 {OV2722_8BIT, 0x373a, 0x60}, 1002 {OV2722_8BIT, 0x3715, 0x01}, 1003 {OV2722_8BIT, 0x3703, 0x2e}, 1004 {OV2722_8BIT, 0x3705, 0x10}, 1005 {OV2722_8BIT, 0x3730, 0x30}, 1006 {OV2722_8BIT, 0x3704, 0x62}, 1007 {OV2722_8BIT, 0x3f06, 0x3a}, 1008 {OV2722_8BIT, 0x371c, 0x00}, 1009 {OV2722_8BIT, 0x371d, 0xc4}, 1010 {OV2722_8BIT, 0x371e, 0x01}, 1011 {OV2722_8BIT, 0x371f, 0x0d}, 1012 {OV2722_8BIT, 0x3708, 0x61}, 1013 {OV2722_8BIT, 0x3709, 0x12}, 1014 {OV2722_8BIT, 0x3800, 0x01}, 1015 {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ 1016 {OV2722_8BIT, 0x3802, 0x00}, 1017 {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ 1018 {OV2722_8BIT, 0x3804, 0x06}, 1019 {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ 1020 {OV2722_8BIT, 0x3806, 0x03}, 1021 {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ 1022 {OV2722_8BIT, 0x3808, 0x05}, 1023 {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ 1024 {OV2722_8BIT, 0x380a, 0x02}, 1025 {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ 1026 {OV2722_8BIT, 0x380c, 0x08}, 1027 {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ 1028 {OV2722_8BIT, 0x380e, 0x04}, 1029 {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ 1030 {OV2722_8BIT, 0x3810, 0x00}, 1031 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 1032 {OV2722_8BIT, 0x3812, 0x00}, 1033 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 1034 {OV2722_8BIT, 0x3820, 0x80}, 1035 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 1036 {OV2722_8BIT, 0x3814, 0x11}, 1037 {OV2722_8BIT, 0x3815, 0x11}, 1038 {OV2722_8BIT, 0x3612, 0x0b}, 1039 {OV2722_8BIT, 0x3618, 0x04}, 1040 {OV2722_8BIT, 0x3a08, 0x01}, 1041 {OV2722_8BIT, 0x3a09, 0x50}, 1042 {OV2722_8BIT, 0x3a0a, 0x01}, 1043 {OV2722_8BIT, 0x3a0b, 0x18}, 1044 {OV2722_8BIT, 0x3a0d, 0x03}, 1045 {OV2722_8BIT, 0x3a0e, 0x03}, 1046 {OV2722_8BIT, 0x4520, 0x00}, 1047 {OV2722_8BIT, 0x4837, 0x1b}, 1048 {OV2722_8BIT, 0x3600, 0x08}, 1049 {OV2722_8BIT, 0x3621, 0xc0}, 1050 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 1051 {OV2722_8BIT, 0x3633, 0x23}, 1052 {OV2722_8BIT, 0x3634, 0x54}, 1053 {OV2722_8BIT, 0x3f01, 0x0c}, 1054 {OV2722_8BIT, 0x5001, 0xc1}, 1055 {OV2722_8BIT, 0x3614, 0xf0}, 1056 {OV2722_8BIT, 0x3630, 0x2d}, 1057 {OV2722_8BIT, 0x370b, 0x62}, 1058 {OV2722_8BIT, 0x3706, 0x61}, 1059 {OV2722_8BIT, 0x4000, 0x02}, 1060 {OV2722_8BIT, 0x4002, 0xc5}, 1061 {OV2722_8BIT, 0x4005, 0x08}, 1062 {OV2722_8BIT, 0x404f, 0x84}, 1063 {OV2722_8BIT, 0x4051, 0x00}, 1064 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 1065 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 1066 {OV2722_8BIT, 0x3a18, 0x00}, 1067 {OV2722_8BIT, 0x3a19, 0x80}, 1068 {OV2722_8BIT, 0x4521, 0x00}, 1069 {OV2722_8BIT, 0x5183, 0xb0}, 1070 {OV2722_8BIT, 0x5184, 0xb0}, 1071 {OV2722_8BIT, 0x5185, 0xb0}, 1072 {OV2722_8BIT, 0x370c, 0x0c}, 1073 {OV2722_8BIT, 0x3035, 0x00}, 1074 {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ 1075 {OV2722_8BIT, 0x3037, 0xa1}, 1076 {OV2722_8BIT, 0x303e, 0x19}, 1077 {OV2722_8BIT, 0x3038, 0x06}, 1078 {OV2722_8BIT, 0x3018, 0x04}, 1079 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 1080 {OV2722_8BIT, 0x3001, 0x00}, 1081 {OV2722_8BIT, 0x3002, 0x00}, 1082 {OV2722_8BIT, 0x3a0f, 0x40}, 1083 {OV2722_8BIT, 0x3a10, 0x38}, 1084 {OV2722_8BIT, 0x3a1b, 0x48}, 1085 {OV2722_8BIT, 0x3a1e, 0x30}, 1086 {OV2722_8BIT, 0x3a11, 0x90}, 1087 {OV2722_8BIT, 0x3a1f, 0x10}, 1088 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 1089 {OV2722_8BIT, 0x3500, 0x00}, 1090 {OV2722_8BIT, 0x3501, 0x3F}, 1091 {OV2722_8BIT, 0x3502, 0x00}, 1092 {OV2722_8BIT, 0x3508, 0x00}, 1093 {OV2722_8BIT, 0x3509, 0x00}, 1094 {OV2722_TOK_TERM, 0, 0}, 1095 }; 1096 #endif 1097 1098 static struct ov2722_resolution ov2722_res_preview[] = { 1099 { 1100 .desc = "ov2722_1632_1092_30fps", 1101 .width = 1632, 1102 .height = 1092, 1103 .fps = 30, 1104 .pix_clk_freq = 85, 1105 .used = 0, 1106 .pixels_per_line = 2260, 1107 .lines_per_frame = 1244, 1108 .skip_frames = 3, 1109 .regs = ov2722_1632_1092_30fps, 1110 .mipi_freq = 422400, 1111 }, 1112 { 1113 .desc = "ov2722_1452_1092_30fps", 1114 .width = 1452, 1115 .height = 1092, 1116 .fps = 30, 1117 .pix_clk_freq = 85, 1118 .used = 0, 1119 .pixels_per_line = 2260, 1120 .lines_per_frame = 1244, 1121 .skip_frames = 3, 1122 .regs = ov2722_1452_1092_30fps, 1123 .mipi_freq = 422400, 1124 }, 1125 { 1126 .desc = "ov2722_1080P_30fps", 1127 .width = 1932, 1128 .height = 1092, 1129 .pix_clk_freq = 69, 1130 .fps = 30, 1131 .used = 0, 1132 .pixels_per_line = 2068, 1133 .lines_per_frame = 1114, 1134 .skip_frames = 3, 1135 .regs = ov2722_1080p_30fps, 1136 .mipi_freq = 345600, 1137 }, 1138 }; 1139 1140 #define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) 1141 1142 /* 1143 * Disable non-preview configurations until the configuration selection is 1144 * improved. 1145 */ 1146 #if 0 1147 struct ov2722_resolution ov2722_res_still[] = { 1148 { 1149 .desc = "ov2722_480P_30fps", 1150 .width = 1632, 1151 .height = 1092, 1152 .fps = 30, 1153 .pix_clk_freq = 85, 1154 .used = 0, 1155 .pixels_per_line = 2260, 1156 .lines_per_frame = 1244, 1157 .skip_frames = 3, 1158 .regs = ov2722_1632_1092_30fps, 1159 .mipi_freq = 422400, 1160 }, 1161 { 1162 .desc = "ov2722_1452_1092_30fps", 1163 .width = 1452, 1164 .height = 1092, 1165 .fps = 30, 1166 .pix_clk_freq = 85, 1167 .used = 0, 1168 .pixels_per_line = 2260, 1169 .lines_per_frame = 1244, 1170 .skip_frames = 3, 1171 .regs = ov2722_1452_1092_30fps, 1172 .mipi_freq = 422400, 1173 }, 1174 { 1175 .desc = "ov2722_1080P_30fps", 1176 .width = 1932, 1177 .height = 1092, 1178 .pix_clk_freq = 69, 1179 .fps = 30, 1180 .used = 0, 1181 .pixels_per_line = 2068, 1182 .lines_per_frame = 1114, 1183 .skip_frames = 3, 1184 .regs = ov2722_1080p_30fps, 1185 .mipi_freq = 345600, 1186 }, 1187 }; 1188 1189 #define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) 1190 1191 struct ov2722_resolution ov2722_res_video[] = { 1192 { 1193 .desc = "ov2722_QVGA_30fps", 1194 .width = 336, 1195 .height = 256, 1196 .fps = 30, 1197 .pix_clk_freq = 73, 1198 .used = 0, 1199 .pixels_per_line = 2048, 1200 .lines_per_frame = 1184, 1201 .skip_frames = 3, 1202 .regs = ov2722_QVGA_30fps, 1203 .mipi_freq = 364800, 1204 }, 1205 { 1206 .desc = "ov2722_480P_30fps", 1207 .width = 736, 1208 .height = 496, 1209 .fps = 30, 1210 .pix_clk_freq = 73, 1211 .used = 0, 1212 .pixels_per_line = 2048, 1213 .lines_per_frame = 1184, 1214 .skip_frames = 3, 1215 .regs = ov2722_480P_30fps, 1216 }, 1217 { 1218 .desc = "ov2722_1080P_30fps", 1219 .width = 1932, 1220 .height = 1092, 1221 .pix_clk_freq = 69, 1222 .fps = 30, 1223 .used = 0, 1224 .pixels_per_line = 2068, 1225 .lines_per_frame = 1114, 1226 .skip_frames = 3, 1227 .regs = ov2722_1080p_30fps, 1228 .mipi_freq = 345600, 1229 }, 1230 }; 1231 1232 #define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) 1233 #endif 1234 1235 static struct ov2722_resolution *ov2722_res = ov2722_res_preview; 1236 static unsigned long N_RES = N_RES_PREVIEW; 1237 #endif 1238