1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 idle-states { 57 entry-method = "psci"; 58 59 cpu_sleep_wait: cpu-sleep-wait { 60 compatible = "arm,idle-state"; 61 arm,psci-suspend-param = <0x0010000>; 62 local-timer-stop; 63 entry-latency-us = <100>; 64 exit-latency-us = <50>; 65 min-residency-us = <1000>; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 compatible = "arm,cortex-a7"; 71 device_type = "cpu"; 72 reg = <0>; 73 clock-frequency = <792000000>; 74 clock-latency = <61036>; /* two CLK32 periods */ 75 clocks = <&clks IMX7D_CLK_ARM>; 76 cpu-idle-states = <&cpu_sleep_wait>; 77 }; 78 }; 79 80 ckil: clock-cki { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <32768>; 84 clock-output-names = "ckil"; 85 }; 86 87 osc: clock-osc { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc"; 92 }; 93 94 usbphynop1: usbphynop1 { 95 compatible = "usb-nop-xceiv"; 96 clocks = <&clks IMX7D_USB_PHY1_CLK>; 97 clock-names = "main_clk"; 98 #phy-cells = <0>; 99 }; 100 101 usbphynop3: usbphynop3 { 102 compatible = "usb-nop-xceiv"; 103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 104 clock-names = "main_clk"; 105 #phy-cells = <0>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a7-pmu"; 110 interrupt-parent = <&gpc>; 111 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 112 interrupt-affinity = <&cpu0>; 113 }; 114 115 replicator { 116 /* 117 * non-configurable replicators don't show up on the 118 * AMBA bus. As such no need to add "arm,primecell" 119 */ 120 compatible = "arm,coresight-static-replicator"; 121 122 out-ports { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 /* replicator output ports */ 126 port@0 { 127 reg = <0>; 128 replicator_out_port0: endpoint { 129 remote-endpoint = <&tpiu_in_port>; 130 }; 131 }; 132 133 port@1 { 134 reg = <1>; 135 replicator_out_port1: endpoint { 136 remote-endpoint = <&etr_in_port>; 137 }; 138 }; 139 }; 140 141 in-ports { 142 port { 143 replicator_in_port0: endpoint { 144 remote-endpoint = <&etf_out_port>; 145 }; 146 }; 147 }; 148 }; 149 150 timer { 151 compatible = "arm,armv7-timer"; 152 interrupt-parent = <&intc>; 153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 157 }; 158 159 soc { 160 #address-cells = <1>; 161 #size-cells = <1>; 162 compatible = "simple-bus"; 163 interrupt-parent = <&gpc>; 164 ranges; 165 166 funnel@30041000 { 167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 168 reg = <0x30041000 0x1000>; 169 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 170 clock-names = "apb_pclk"; 171 172 ca_funnel_in_ports: in-ports { 173 port { 174 ca_funnel_in_port0: endpoint { 175 remote-endpoint = <&etm0_out_port>; 176 }; 177 }; 178 179 /* the other input ports are not connect to anything */ 180 }; 181 182 out-ports { 183 port { 184 ca_funnel_out_port0: endpoint { 185 remote-endpoint = <&hugo_funnel_in_port0>; 186 }; 187 }; 188 189 }; 190 }; 191 192 etm@3007c000 { 193 compatible = "arm,coresight-etm3x", "arm,primecell"; 194 reg = <0x3007c000 0x1000>; 195 cpu = <&cpu0>; 196 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 197 clock-names = "apb_pclk"; 198 199 out-ports { 200 port { 201 etm0_out_port: endpoint { 202 remote-endpoint = <&ca_funnel_in_port0>; 203 }; 204 }; 205 }; 206 }; 207 208 funnel@30083000 { 209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 210 reg = <0x30083000 0x1000>; 211 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 212 clock-names = "apb_pclk"; 213 214 in-ports { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 port@0 { 219 reg = <0>; 220 hugo_funnel_in_port0: endpoint { 221 remote-endpoint = <&ca_funnel_out_port0>; 222 }; 223 }; 224 225 port@1 { 226 reg = <1>; 227 hugo_funnel_in_port1: endpoint { 228 /* M4 input */ 229 }; 230 }; 231 /* the other input ports are not connect to anything */ 232 }; 233 234 out-ports { 235 port { 236 hugo_funnel_out_port0: endpoint { 237 remote-endpoint = <&etf_in_port>; 238 }; 239 }; 240 }; 241 }; 242 243 etf@30084000 { 244 compatible = "arm,coresight-tmc", "arm,primecell"; 245 reg = <0x30084000 0x1000>; 246 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 247 clock-names = "apb_pclk"; 248 249 in-ports { 250 port { 251 etf_in_port: endpoint { 252 remote-endpoint = <&hugo_funnel_out_port0>; 253 }; 254 }; 255 }; 256 257 out-ports { 258 port { 259 etf_out_port: endpoint { 260 remote-endpoint = <&replicator_in_port0>; 261 }; 262 }; 263 }; 264 }; 265 266 etr@30086000 { 267 compatible = "arm,coresight-tmc", "arm,primecell"; 268 reg = <0x30086000 0x1000>; 269 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 270 clock-names = "apb_pclk"; 271 272 in-ports { 273 port { 274 etr_in_port: endpoint { 275 remote-endpoint = <&replicator_out_port1>; 276 }; 277 }; 278 }; 279 }; 280 281 tpiu@30087000 { 282 compatible = "arm,coresight-tpiu", "arm,primecell"; 283 reg = <0x30087000 0x1000>; 284 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 285 clock-names = "apb_pclk"; 286 287 in-ports { 288 port { 289 tpiu_in_port: endpoint { 290 remote-endpoint = <&replicator_out_port0>; 291 }; 292 }; 293 }; 294 }; 295 296 intc: interrupt-controller@31001000 { 297 compatible = "arm,cortex-a7-gic"; 298 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 299 #interrupt-cells = <3>; 300 interrupt-controller; 301 interrupt-parent = <&intc>; 302 reg = <0x31001000 0x1000>, 303 <0x31002000 0x2000>, 304 <0x31004000 0x2000>, 305 <0x31006000 0x2000>; 306 }; 307 308 aips1: bus@30000000 { 309 compatible = "fsl,aips-bus", "simple-bus"; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 reg = <0x30000000 0x400000>; 313 ranges; 314 315 gpio1: gpio@30200000 { 316 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 317 reg = <0x30200000 0x10000>; 318 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 319 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 gpio-ranges = <&iomuxc 0 13 32>; 337 }; 338 339 gpio3: gpio@30220000 { 340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 341 reg = <0x30220000 0x10000>; 342 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 gpio-ranges = <&iomuxc 0 45 29>; 349 }; 350 351 gpio4: gpio@30230000 { 352 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 353 reg = <0x30230000 0x10000>; 354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 356 gpio-controller; 357 #gpio-cells = <2>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 gpio-ranges = <&iomuxc 0 74 24>; 361 }; 362 363 gpio5: gpio@30240000 { 364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 365 reg = <0x30240000 0x10000>; 366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 gpio-ranges = <&iomuxc 0 98 18>; 373 }; 374 375 gpio6: gpio@30250000 { 376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 377 reg = <0x30250000 0x10000>; 378 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 gpio-ranges = <&iomuxc 0 116 23>; 385 }; 386 387 gpio7: gpio@30260000 { 388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 389 reg = <0x30260000 0x10000>; 390 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 392 gpio-controller; 393 #gpio-cells = <2>; 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 gpio-ranges = <&iomuxc 0 139 16>; 397 }; 398 399 wdog1: watchdog@30280000 { 400 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 401 reg = <0x30280000 0x10000>; 402 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 404 }; 405 406 wdog2: watchdog@30290000 { 407 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 408 reg = <0x30290000 0x10000>; 409 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 411 status = "disabled"; 412 }; 413 414 wdog3: watchdog@302a0000 { 415 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 416 reg = <0x302a0000 0x10000>; 417 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 419 status = "disabled"; 420 }; 421 422 wdog4: watchdog@302b0000 { 423 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 424 reg = <0x302b0000 0x10000>; 425 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 427 status = "disabled"; 428 }; 429 430 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 431 compatible = "fsl,imx7d-iomuxc-lpsr"; 432 reg = <0x302c0000 0x10000>; 433 fsl,input-sel = <&iomuxc>; 434 }; 435 436 gpt1: timer@302d0000 { 437 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 438 reg = <0x302d0000 0x10000>; 439 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 441 <&clks IMX7D_GPT1_ROOT_CLK>; 442 clock-names = "ipg", "per"; 443 }; 444 445 gpt2: timer@302e0000 { 446 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 447 reg = <0x302e0000 0x10000>; 448 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 450 <&clks IMX7D_GPT2_ROOT_CLK>; 451 clock-names = "ipg", "per"; 452 status = "disabled"; 453 }; 454 455 gpt3: timer@302f0000 { 456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 457 reg = <0x302f0000 0x10000>; 458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 460 <&clks IMX7D_GPT3_ROOT_CLK>; 461 clock-names = "ipg", "per"; 462 status = "disabled"; 463 }; 464 465 gpt4: timer@30300000 { 466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 467 reg = <0x30300000 0x10000>; 468 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 470 <&clks IMX7D_GPT4_ROOT_CLK>; 471 clock-names = "ipg", "per"; 472 status = "disabled"; 473 }; 474 475 kpp: keypad@30320000 { 476 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 477 reg = <0x30320000 0x10000>; 478 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 480 status = "disabled"; 481 }; 482 483 iomuxc: pinctrl@30330000 { 484 compatible = "fsl,imx7d-iomuxc"; 485 reg = <0x30330000 0x10000>; 486 }; 487 488 gpr: iomuxc-gpr@30340000 { 489 compatible = "fsl,imx7d-iomuxc-gpr", 490 "fsl,imx6q-iomuxc-gpr", "syscon", 491 "simple-mfd"; 492 reg = <0x30340000 0x10000>; 493 494 mux: mux-controller { 495 compatible = "mmio-mux"; 496 #mux-control-cells = <0>; 497 mux-reg-masks = <0x14 0x00000010>; 498 }; 499 500 video_mux: csi-mux { 501 compatible = "video-mux"; 502 mux-controls = <&mux 0>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 507 port@0 { 508 reg = <0>; 509 }; 510 511 port@1 { 512 reg = <1>; 513 514 csi_mux_from_mipi_vc0: endpoint { 515 remote-endpoint = <&mipi_vc0_to_csi_mux>; 516 }; 517 }; 518 519 port@2 { 520 reg = <2>; 521 522 csi_mux_to_csi: endpoint { 523 remote-endpoint = <&csi_from_csi_mux>; 524 }; 525 }; 526 }; 527 }; 528 529 ocotp: efuse@30350000 { 530 #address-cells = <1>; 531 #size-cells = <1>; 532 compatible = "fsl,imx7d-ocotp", "syscon"; 533 reg = <0x30350000 0x10000>; 534 clocks = <&clks IMX7D_OCOTP_CLK>; 535 536 tempmon_calib: calib@3c { 537 reg = <0x3c 0x4>; 538 }; 539 540 fuse_grade: fuse-grade@10 { 541 reg = <0x10 0x4>; 542 }; 543 }; 544 545 anatop: anatop@30360000 { 546 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 547 "syscon", "simple-mfd"; 548 reg = <0x30360000 0x10000>; 549 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 551 552 reg_1p0d: regulator-vdd1p0d { 553 compatible = "fsl,anatop-regulator"; 554 regulator-name = "vdd1p0d"; 555 regulator-min-microvolt = <800000>; 556 regulator-max-microvolt = <1200000>; 557 anatop-reg-offset = <0x210>; 558 anatop-vol-bit-shift = <8>; 559 anatop-vol-bit-width = <5>; 560 anatop-min-bit-val = <8>; 561 anatop-min-voltage = <800000>; 562 anatop-max-voltage = <1200000>; 563 anatop-enable-bit = <0>; 564 }; 565 566 reg_1p2: regulator-vdd1p2 { 567 compatible = "fsl,anatop-regulator"; 568 regulator-name = "vdd1p2"; 569 regulator-min-microvolt = <1100000>; 570 regulator-max-microvolt = <1300000>; 571 anatop-reg-offset = <0x220>; 572 anatop-vol-bit-shift = <8>; 573 anatop-vol-bit-width = <5>; 574 anatop-min-bit-val = <0x14>; 575 anatop-min-voltage = <1100000>; 576 anatop-max-voltage = <1300000>; 577 anatop-enable-bit = <0>; 578 }; 579 580 tempmon: tempmon { 581 compatible = "fsl,imx7d-tempmon"; 582 interrupt-parent = <&gpc>; 583 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 584 fsl,tempmon = <&anatop>; 585 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 586 nvmem-cell-names = "calib", "temp_grade"; 587 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 588 }; 589 }; 590 591 snvs: snvs@30370000 { 592 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 593 reg = <0x30370000 0x10000>; 594 595 snvs_rtc: snvs-rtc-lp { 596 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 597 regmap = <&snvs>; 598 offset = <0x34>; 599 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clks IMX7D_SNVS_CLK>; 602 clock-names = "snvs-rtc"; 603 }; 604 605 snvs_pwrkey: snvs-powerkey { 606 compatible = "fsl,sec-v4.0-pwrkey"; 607 regmap = <&snvs>; 608 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&clks IMX7D_SNVS_CLK>; 610 clock-names = "snvs-pwrkey"; 611 linux,keycode = <KEY_POWER>; 612 wakeup-source; 613 status = "disabled"; 614 }; 615 }; 616 617 clks: clock-controller@30380000 { 618 compatible = "fsl,imx7d-ccm"; 619 reg = <0x30380000 0x10000>; 620 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 622 #clock-cells = <1>; 623 clocks = <&ckil>, <&osc>; 624 clock-names = "ckil", "osc"; 625 }; 626 627 src: reset-controller@30390000 { 628 compatible = "fsl,imx7d-src", "syscon"; 629 reg = <0x30390000 0x10000>; 630 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 631 #reset-cells = <1>; 632 }; 633 634 gpc: gpc@303a0000 { 635 compatible = "fsl,imx7d-gpc"; 636 reg = <0x303a0000 0x10000>; 637 interrupt-controller; 638 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 639 #interrupt-cells = <3>; 640 interrupt-parent = <&intc>; 641 #power-domain-cells = <1>; 642 643 pgc { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 pgc_mipi_phy: power-domain@0 { 648 #power-domain-cells = <0>; 649 reg = <0>; 650 power-supply = <®_1p0d>; 651 }; 652 653 pgc_pcie_phy: power-domain@1 { 654 #power-domain-cells = <0>; 655 reg = <1>; 656 power-supply = <®_1p0d>; 657 }; 658 659 pgc_hsic_phy: power-domain@2 { 660 #power-domain-cells = <0>; 661 reg = <2>; 662 power-supply = <®_1p2>; 663 }; 664 }; 665 }; 666 }; 667 668 aips2: bus@30400000 { 669 compatible = "fsl,aips-bus", "simple-bus"; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 reg = <0x30400000 0x400000>; 673 ranges; 674 675 adc1: adc@30610000 { 676 compatible = "fsl,imx7d-adc"; 677 reg = <0x30610000 0x10000>; 678 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 680 clock-names = "adc"; 681 #io-channel-cells = <1>; 682 status = "disabled"; 683 }; 684 685 adc2: adc@30620000 { 686 compatible = "fsl,imx7d-adc"; 687 reg = <0x30620000 0x10000>; 688 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 690 clock-names = "adc"; 691 #io-channel-cells = <1>; 692 status = "disabled"; 693 }; 694 695 ecspi4: spi@30630000 { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 699 reg = <0x30630000 0x10000>; 700 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 702 <&clks IMX7D_ECSPI4_ROOT_CLK>; 703 clock-names = "ipg", "per"; 704 status = "disabled"; 705 }; 706 707 pwm1: pwm@30660000 { 708 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 709 reg = <0x30660000 0x10000>; 710 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 712 <&clks IMX7D_PWM1_ROOT_CLK>; 713 clock-names = "ipg", "per"; 714 #pwm-cells = <3>; 715 status = "disabled"; 716 }; 717 718 pwm2: pwm@30670000 { 719 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 720 reg = <0x30670000 0x10000>; 721 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 723 <&clks IMX7D_PWM2_ROOT_CLK>; 724 clock-names = "ipg", "per"; 725 #pwm-cells = <3>; 726 status = "disabled"; 727 }; 728 729 pwm3: pwm@30680000 { 730 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 731 reg = <0x30680000 0x10000>; 732 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 734 <&clks IMX7D_PWM3_ROOT_CLK>; 735 clock-names = "ipg", "per"; 736 #pwm-cells = <3>; 737 status = "disabled"; 738 }; 739 740 pwm4: pwm@30690000 { 741 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 742 reg = <0x30690000 0x10000>; 743 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 745 <&clks IMX7D_PWM4_ROOT_CLK>; 746 clock-names = "ipg", "per"; 747 #pwm-cells = <3>; 748 status = "disabled"; 749 }; 750 751 csi: csi@30710000 { 752 compatible = "fsl,imx7-csi"; 753 reg = <0x30710000 0x10000>; 754 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clks IMX7D_CLK_DUMMY>, 756 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 757 <&clks IMX7D_CLK_DUMMY>; 758 clock-names = "axi", "mclk", "dcic"; 759 status = "disabled"; 760 761 port { 762 csi_from_csi_mux: endpoint { 763 remote-endpoint = <&csi_mux_to_csi>; 764 }; 765 }; 766 }; 767 768 lcdif: lcdif@30730000 { 769 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 770 reg = <0x30730000 0x10000>; 771 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 773 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 774 clock-names = "pix", "axi"; 775 status = "disabled"; 776 }; 777 778 mipi_csi: mipi-csi@30750000 { 779 compatible = "fsl,imx7-mipi-csi2"; 780 reg = <0x30750000 0x10000>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 785 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 786 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 787 clock-names = "pclk", "wrap", "phy"; 788 power-domains = <&pgc_mipi_phy>; 789 phy-supply = <®_1p0d>; 790 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 791 reset-names = "mrst"; 792 status = "disabled"; 793 794 port@0 { 795 reg = <0>; 796 }; 797 798 port@1 { 799 reg = <1>; 800 801 mipi_vc0_to_csi_mux: endpoint { 802 remote-endpoint = <&csi_mux_from_mipi_vc0>; 803 }; 804 }; 805 }; 806 }; 807 808 aips3: bus@30800000 { 809 compatible = "fsl,aips-bus", "simple-bus"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 reg = <0x30800000 0x400000>; 813 ranges; 814 815 spba-bus@30800000 { 816 compatible = "fsl,spba-bus", "simple-bus"; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 reg = <0x30800000 0x100000>; 820 ranges; 821 822 ecspi1: spi@30820000 { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 826 reg = <0x30820000 0x10000>; 827 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 829 <&clks IMX7D_ECSPI1_ROOT_CLK>; 830 clock-names = "ipg", "per"; 831 status = "disabled"; 832 }; 833 834 ecspi2: spi@30830000 { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 838 reg = <0x30830000 0x10000>; 839 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 841 <&clks IMX7D_ECSPI2_ROOT_CLK>; 842 clock-names = "ipg", "per"; 843 status = "disabled"; 844 }; 845 846 ecspi3: spi@30840000 { 847 #address-cells = <1>; 848 #size-cells = <0>; 849 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 850 reg = <0x30840000 0x10000>; 851 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 853 <&clks IMX7D_ECSPI3_ROOT_CLK>; 854 clock-names = "ipg", "per"; 855 status = "disabled"; 856 }; 857 858 uart1: serial@30860000 { 859 compatible = "fsl,imx7d-uart", 860 "fsl,imx6q-uart"; 861 reg = <0x30860000 0x10000>; 862 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 864 <&clks IMX7D_UART1_ROOT_CLK>; 865 clock-names = "ipg", "per"; 866 status = "disabled"; 867 }; 868 869 uart2: serial@30890000 { 870 compatible = "fsl,imx7d-uart", 871 "fsl,imx6q-uart"; 872 reg = <0x30890000 0x10000>; 873 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 875 <&clks IMX7D_UART2_ROOT_CLK>; 876 clock-names = "ipg", "per"; 877 status = "disabled"; 878 }; 879 880 uart3: serial@30880000 { 881 compatible = "fsl,imx7d-uart", 882 "fsl,imx6q-uart"; 883 reg = <0x30880000 0x10000>; 884 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 886 <&clks IMX7D_UART3_ROOT_CLK>; 887 clock-names = "ipg", "per"; 888 status = "disabled"; 889 }; 890 891 sai1: sai@308a0000 { 892 #sound-dai-cells = <0>; 893 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 894 reg = <0x308a0000 0x10000>; 895 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 897 <&clks IMX7D_SAI1_ROOT_CLK>, 898 <&clks IMX7D_CLK_DUMMY>, 899 <&clks IMX7D_CLK_DUMMY>; 900 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 901 dma-names = "rx", "tx"; 902 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 903 status = "disabled"; 904 }; 905 906 sai2: sai@308b0000 { 907 #sound-dai-cells = <0>; 908 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 909 reg = <0x308b0000 0x10000>; 910 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 912 <&clks IMX7D_SAI2_ROOT_CLK>, 913 <&clks IMX7D_CLK_DUMMY>, 914 <&clks IMX7D_CLK_DUMMY>; 915 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 916 dma-names = "rx", "tx"; 917 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 918 status = "disabled"; 919 }; 920 921 sai3: sai@308c0000 { 922 #sound-dai-cells = <0>; 923 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 924 reg = <0x308c0000 0x10000>; 925 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 927 <&clks IMX7D_SAI3_ROOT_CLK>, 928 <&clks IMX7D_CLK_DUMMY>, 929 <&clks IMX7D_CLK_DUMMY>; 930 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 931 dma-names = "rx", "tx"; 932 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 933 status = "disabled"; 934 }; 935 }; 936 937 crypto: crypto@30900000 { 938 compatible = "fsl,sec-v4.0"; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 reg = <0x30900000 0x40000>; 942 ranges = <0 0x30900000 0x40000>; 943 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&clks IMX7D_CAAM_CLK>, 945 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 946 clock-names = "ipg", "aclk"; 947 948 sec_jr0: jr@1000 { 949 compatible = "fsl,sec-v4.0-job-ring"; 950 reg = <0x1000 0x1000>; 951 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 952 }; 953 954 sec_jr1: jr@2000 { 955 compatible = "fsl,sec-v4.0-job-ring"; 956 reg = <0x2000 0x1000>; 957 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 958 }; 959 960 sec_jr2: jr@3000 { 961 compatible = "fsl,sec-v4.0-job-ring"; 962 reg = <0x3000 0x1000>; 963 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 964 }; 965 }; 966 967 flexcan1: can@30a00000 { 968 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 969 reg = <0x30a00000 0x10000>; 970 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clks IMX7D_CLK_DUMMY>, 972 <&clks IMX7D_CAN1_ROOT_CLK>; 973 clock-names = "ipg", "per"; 974 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 975 status = "disabled"; 976 }; 977 978 flexcan2: can@30a10000 { 979 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 980 reg = <0x30a10000 0x10000>; 981 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clks IMX7D_CLK_DUMMY>, 983 <&clks IMX7D_CAN2_ROOT_CLK>; 984 clock-names = "ipg", "per"; 985 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 986 status = "disabled"; 987 }; 988 989 i2c1: i2c@30a20000 { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 993 reg = <0x30a20000 0x10000>; 994 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 996 status = "disabled"; 997 }; 998 999 i2c2: i2c@30a30000 { 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1003 reg = <0x30a30000 0x10000>; 1004 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1006 status = "disabled"; 1007 }; 1008 1009 i2c3: i2c@30a40000 { 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1013 reg = <0x30a40000 0x10000>; 1014 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c4: i2c@30a50000 { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1023 reg = <0x30a50000 0x10000>; 1024 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1026 status = "disabled"; 1027 }; 1028 1029 uart4: serial@30a60000 { 1030 compatible = "fsl,imx7d-uart", 1031 "fsl,imx6q-uart"; 1032 reg = <0x30a60000 0x10000>; 1033 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1035 <&clks IMX7D_UART4_ROOT_CLK>; 1036 clock-names = "ipg", "per"; 1037 status = "disabled"; 1038 }; 1039 1040 uart5: serial@30a70000 { 1041 compatible = "fsl,imx7d-uart", 1042 "fsl,imx6q-uart"; 1043 reg = <0x30a70000 0x10000>; 1044 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1046 <&clks IMX7D_UART5_ROOT_CLK>; 1047 clock-names = "ipg", "per"; 1048 status = "disabled"; 1049 }; 1050 1051 uart6: serial@30a80000 { 1052 compatible = "fsl,imx7d-uart", 1053 "fsl,imx6q-uart"; 1054 reg = <0x30a80000 0x10000>; 1055 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1057 <&clks IMX7D_UART6_ROOT_CLK>; 1058 clock-names = "ipg", "per"; 1059 status = "disabled"; 1060 }; 1061 1062 uart7: serial@30a90000 { 1063 compatible = "fsl,imx7d-uart", 1064 "fsl,imx6q-uart"; 1065 reg = <0x30a90000 0x10000>; 1066 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1068 <&clks IMX7D_UART7_ROOT_CLK>; 1069 clock-names = "ipg", "per"; 1070 status = "disabled"; 1071 }; 1072 1073 mu0a: mailbox@30aa0000 { 1074 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1075 reg = <0x30aa0000 0x10000>; 1076 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1078 #mbox-cells = <2>; 1079 status = "disabled"; 1080 }; 1081 1082 mu0b: mailbox@30ab0000 { 1083 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1084 reg = <0x30ab0000 0x10000>; 1085 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1087 #mbox-cells = <2>; 1088 fsl,mu-side-b; 1089 status = "disabled"; 1090 }; 1091 1092 usbotg1: usb@30b10000 { 1093 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1094 reg = <0x30b10000 0x200>; 1095 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1097 fsl,usbphy = <&usbphynop1>; 1098 fsl,usbmisc = <&usbmisc1 0>; 1099 phy-clkgate-delay-us = <400>; 1100 status = "disabled"; 1101 }; 1102 1103 usbh: usb@30b30000 { 1104 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1105 reg = <0x30b30000 0x200>; 1106 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&pgc_hsic_phy>; 1108 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1109 fsl,usbphy = <&usbphynop3>; 1110 fsl,usbmisc = <&usbmisc3 0>; 1111 phy_type = "hsic"; 1112 dr_mode = "host"; 1113 phy-clkgate-delay-us = <400>; 1114 status = "disabled"; 1115 }; 1116 1117 usbmisc1: usbmisc@30b10200 { 1118 #index-cells = <1>; 1119 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1120 reg = <0x30b10200 0x200>; 1121 }; 1122 1123 usbmisc3: usbmisc@30b30200 { 1124 #index-cells = <1>; 1125 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1126 reg = <0x30b30200 0x200>; 1127 }; 1128 1129 usdhc1: mmc@30b40000 { 1130 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1131 reg = <0x30b40000 0x10000>; 1132 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1134 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1135 <&clks IMX7D_USDHC1_ROOT_CLK>; 1136 clock-names = "ipg", "ahb", "per"; 1137 bus-width = <4>; 1138 status = "disabled"; 1139 }; 1140 1141 usdhc2: mmc@30b50000 { 1142 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1143 reg = <0x30b50000 0x10000>; 1144 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1146 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1147 <&clks IMX7D_USDHC2_ROOT_CLK>; 1148 clock-names = "ipg", "ahb", "per"; 1149 bus-width = <4>; 1150 status = "disabled"; 1151 }; 1152 1153 usdhc3: mmc@30b60000 { 1154 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1155 reg = <0x30b60000 0x10000>; 1156 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1158 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1159 <&clks IMX7D_USDHC3_ROOT_CLK>; 1160 clock-names = "ipg", "ahb", "per"; 1161 bus-width = <4>; 1162 status = "disabled"; 1163 }; 1164 1165 qspi: spi@30bb0000 { 1166 compatible = "fsl,imx7d-qspi"; 1167 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1168 reg-names = "QuadSPI", "QuadSPI-memory"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1173 <&clks IMX7D_QSPI_ROOT_CLK>; 1174 clock-names = "qspi_en", "qspi"; 1175 status = "disabled"; 1176 }; 1177 1178 sdma: sdma@30bd0000 { 1179 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1180 reg = <0x30bd0000 0x10000>; 1181 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1183 <&clks IMX7D_SDMA_CORE_CLK>; 1184 clock-names = "ipg", "ahb"; 1185 #dma-cells = <3>; 1186 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1187 }; 1188 1189 fec1: ethernet@30be0000 { 1190 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1191 reg = <0x30be0000 0x10000>; 1192 interrupt-names = "int0", "int1", "int2", "pps"; 1193 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1198 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1199 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1200 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1201 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1202 clock-names = "ipg", "ahb", "ptp", 1203 "enet_clk_ref", "enet_out"; 1204 fsl,num-tx-queues = <3>; 1205 fsl,num-rx-queues = <3>; 1206 fsl,stop-mode = <&gpr 0x10 3>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 dma_apbh: dma-apbh@33000000 { 1212 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1213 reg = <0x33000000 0x2000>; 1214 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1218 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1219 #dma-cells = <1>; 1220 dma-channels = <4>; 1221 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1222 }; 1223 1224 gpmi: nand-controller@33002000{ 1225 compatible = "fsl,imx7d-gpmi-nand"; 1226 #address-cells = <1>; 1227 #size-cells = <1>; 1228 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1229 reg-names = "gpmi-nand", "bch"; 1230 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "bch"; 1232 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1233 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1234 clock-names = "gpmi_io", "gpmi_bch_apb"; 1235 dmas = <&dma_apbh 0>; 1236 dma-names = "rx-tx"; 1237 status = "disabled"; 1238 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1240 }; 1241 }; 1242}; 1243