1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
4 * for Intel part #(s):
5 * - AF82MP20 PCH
6 *
7 * Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
8 */
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
14 #include <linux/moduleparam.h>
15 #include <linux/types.h>
16 #include <linux/miscdevice.h>
17 #include <linux/watchdog.h>
18 #include <linux/fs.h>
19 #include <linux/notifier.h>
20 #include <linux/reboot.h>
21 #include <linux/init.h>
22 #include <linux/jiffies.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/io.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/signal.h>
30 #include <linux/sfi.h>
31 #include <asm/irq.h>
32 #include <linux/atomic.h>
33 #include <asm/intel_scu_ipc.h>
34 #include <asm/apb_timer.h>
35 #include <asm/intel-mid.h>
36
37 #include "intel_scu_watchdog.h"
38
39 /* Bounds number of times we will retry loading time count */
40 /* This retry is a work around for a silicon bug. */
41 #define MAX_RETRY 16
42
43 #define IPC_SET_WATCHDOG_TIMER 0xF8
44
45 static int timer_margin = DEFAULT_SOFT_TO_HARD_MARGIN;
46 module_param(timer_margin, int, 0);
47 MODULE_PARM_DESC(timer_margin,
48 "Watchdog timer margin"
49 "Time between interrupt and resetting the system"
50 "The range is from 1 to 160"
51 "This is the time for all keep alives to arrive");
52
53 static int timer_set = DEFAULT_TIME;
54 module_param(timer_set, int, 0);
55 MODULE_PARM_DESC(timer_set,
56 "Default Watchdog timer setting"
57 "Complete cycle time"
58 "The range is from 1 to 170"
59 "This is the time for all keep alives to arrive");
60
61 /* After watchdog device is closed, check force_boot. If:
62 * force_boot == 0, then force boot on next watchdog interrupt after close,
63 * force_boot == 1, then force boot immediately when device is closed.
64 */
65 static int force_boot;
66 module_param(force_boot, int, 0);
67 MODULE_PARM_DESC(force_boot,
68 "A value of 1 means that the driver will reboot"
69 "the system immediately if the /dev/watchdog device is closed"
70 "A value of 0 means that when /dev/watchdog device is closed"
71 "the watchdog timer will be refreshed for one more interval"
72 "of length: timer_set. At the end of this interval, the"
73 "watchdog timer will reset the system."
74 );
75
76 /* there is only one device in the system now; this can be made into
77 * an array in the future if we have more than one device */
78
79 static struct intel_scu_watchdog_dev watchdog_device;
80
81 /* Forces restart, if force_reboot is set */
watchdog_fire(void)82 static void watchdog_fire(void)
83 {
84 if (force_boot) {
85 pr_crit("Initiating system reboot\n");
86 emergency_restart();
87 pr_crit("Reboot didn't ?????\n");
88 }
89
90 else {
91 pr_crit("Immediate Reboot Disabled\n");
92 pr_crit("System will reset when watchdog timer times out!\n");
93 }
94 }
95
check_timer_margin(int new_margin)96 static int check_timer_margin(int new_margin)
97 {
98 if ((new_margin < MIN_TIME_CYCLE) ||
99 (new_margin > MAX_TIME - timer_set)) {
100 pr_debug("value of new_margin %d is out of the range %d to %d\n",
101 new_margin, MIN_TIME_CYCLE, MAX_TIME - timer_set);
102 return -EINVAL;
103 }
104 return 0;
105 }
106
107 /*
108 * IPC operations
109 */
watchdog_set_ipc(int soft_threshold,int threshold)110 static int watchdog_set_ipc(int soft_threshold, int threshold)
111 {
112 u32 *ipc_wbuf;
113 u8 cbuf[16] = { '\0' };
114 int ipc_ret = 0;
115
116 ipc_wbuf = (u32 *)&cbuf;
117 ipc_wbuf[0] = soft_threshold;
118 ipc_wbuf[1] = threshold;
119
120 ipc_ret = intel_scu_ipc_command(
121 IPC_SET_WATCHDOG_TIMER,
122 0,
123 ipc_wbuf,
124 2,
125 NULL,
126 0);
127
128 if (ipc_ret != 0)
129 pr_err("Error setting SCU watchdog timer: %x\n", ipc_ret);
130
131 return ipc_ret;
132 };
133
134 /*
135 * Intel_SCU operations
136 */
137
138 /* timer interrupt handler */
watchdog_timer_interrupt(int irq,void * dev_id)139 static irqreturn_t watchdog_timer_interrupt(int irq, void *dev_id)
140 {
141 int int_status;
142 int_status = ioread32(watchdog_device.timer_interrupt_status_addr);
143
144 pr_debug("irq, int_status: %x\n", int_status);
145
146 if (int_status != 0)
147 return IRQ_NONE;
148
149 /* has the timer been started? If not, then this is spurious */
150 if (watchdog_device.timer_started == 0) {
151 pr_debug("spurious interrupt received\n");
152 return IRQ_HANDLED;
153 }
154
155 /* temporarily disable the timer */
156 iowrite32(0x00000002, watchdog_device.timer_control_addr);
157
158 /* set the timer to the threshold */
159 iowrite32(watchdog_device.threshold,
160 watchdog_device.timer_load_count_addr);
161
162 /* allow the timer to run */
163 iowrite32(0x00000003, watchdog_device.timer_control_addr);
164
165 return IRQ_HANDLED;
166 }
167
intel_scu_keepalive(void)168 static int intel_scu_keepalive(void)
169 {
170
171 /* read eoi register - clears interrupt */
172 ioread32(watchdog_device.timer_clear_interrupt_addr);
173
174 /* temporarily disable the timer */
175 iowrite32(0x00000002, watchdog_device.timer_control_addr);
176
177 /* set the timer to the soft_threshold */
178 iowrite32(watchdog_device.soft_threshold,
179 watchdog_device.timer_load_count_addr);
180
181 /* allow the timer to run */
182 iowrite32(0x00000003, watchdog_device.timer_control_addr);
183
184 return 0;
185 }
186
intel_scu_stop(void)187 static int intel_scu_stop(void)
188 {
189 iowrite32(0, watchdog_device.timer_control_addr);
190 return 0;
191 }
192
intel_scu_set_heartbeat(u32 t)193 static int intel_scu_set_heartbeat(u32 t)
194 {
195 int ipc_ret;
196 int retry_count;
197 u32 soft_value;
198 u32 hw_value;
199
200 watchdog_device.timer_set = t;
201 watchdog_device.threshold =
202 timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
203 watchdog_device.soft_threshold =
204 (watchdog_device.timer_set - timer_margin)
205 * watchdog_device.timer_tbl_ptr->freq_hz;
206
207 pr_debug("set_heartbeat: timer freq is %d\n",
208 watchdog_device.timer_tbl_ptr->freq_hz);
209 pr_debug("set_heartbeat: timer_set is %x (hex)\n",
210 watchdog_device.timer_set);
211 pr_debug("set_heartbeat: timer_margin is %x (hex)\n", timer_margin);
212 pr_debug("set_heartbeat: threshold is %x (hex)\n",
213 watchdog_device.threshold);
214 pr_debug("set_heartbeat: soft_threshold is %x (hex)\n",
215 watchdog_device.soft_threshold);
216
217 /* Adjust thresholds by FREQ_ADJUSTMENT factor, to make the */
218 /* watchdog timing come out right. */
219 watchdog_device.threshold =
220 watchdog_device.threshold / FREQ_ADJUSTMENT;
221 watchdog_device.soft_threshold =
222 watchdog_device.soft_threshold / FREQ_ADJUSTMENT;
223
224 /* temporarily disable the timer */
225 iowrite32(0x00000002, watchdog_device.timer_control_addr);
226
227 /* send the threshold and soft_threshold via IPC to the processor */
228 ipc_ret = watchdog_set_ipc(watchdog_device.soft_threshold,
229 watchdog_device.threshold);
230
231 if (ipc_ret != 0) {
232 /* Make sure the watchdog timer is stopped */
233 intel_scu_stop();
234 return ipc_ret;
235 }
236
237 /* Soft Threshold set loop. Early versions of silicon did */
238 /* not always set this count correctly. This loop checks */
239 /* the value and retries if it was not set correctly. */
240
241 retry_count = 0;
242 soft_value = watchdog_device.soft_threshold & 0xFFFF0000;
243 do {
244
245 /* Make sure timer is stopped */
246 intel_scu_stop();
247
248 if (MAX_RETRY < retry_count++) {
249 /* Unable to set timer value */
250 pr_err("Unable to set timer\n");
251 return -ENODEV;
252 }
253
254 /* set the timer to the soft threshold */
255 iowrite32(watchdog_device.soft_threshold,
256 watchdog_device.timer_load_count_addr);
257
258 /* read count value before starting timer */
259 ioread32(watchdog_device.timer_load_count_addr);
260
261 /* Start the timer */
262 iowrite32(0x00000003, watchdog_device.timer_control_addr);
263
264 /* read the value the time loaded into its count reg */
265 hw_value = ioread32(watchdog_device.timer_load_count_addr);
266 hw_value = hw_value & 0xFFFF0000;
267
268
269 } while (soft_value != hw_value);
270
271 watchdog_device.timer_started = 1;
272
273 return 0;
274 }
275
276 /*
277 * /dev/watchdog handling
278 */
279
intel_scu_open(struct inode * inode,struct file * file)280 static int intel_scu_open(struct inode *inode, struct file *file)
281 {
282
283 /* Set flag to indicate that watchdog device is open */
284 if (test_and_set_bit(0, &watchdog_device.driver_open))
285 return -EBUSY;
286
287 /* Check for reopen of driver. Reopens are not allowed */
288 if (watchdog_device.driver_closed)
289 return -EPERM;
290
291 return stream_open(inode, file);
292 }
293
intel_scu_release(struct inode * inode,struct file * file)294 static int intel_scu_release(struct inode *inode, struct file *file)
295 {
296 /*
297 * This watchdog should not be closed, after the timer
298 * is started with the WDIPC_SETTIMEOUT ioctl
299 * If force_boot is set watchdog_fire() will cause an
300 * immediate reset. If force_boot is not set, the watchdog
301 * timer is refreshed for one more interval. At the end
302 * of that interval, the watchdog timer will reset the system.
303 */
304
305 if (!test_and_clear_bit(0, &watchdog_device.driver_open)) {
306 pr_debug("intel_scu_release, without open\n");
307 return -ENOTTY;
308 }
309
310 if (!watchdog_device.timer_started) {
311 /* Just close, since timer has not been started */
312 pr_debug("closed, without starting timer\n");
313 return 0;
314 }
315
316 pr_crit("Unexpected close of /dev/watchdog!\n");
317
318 /* Since the timer was started, prevent future reopens */
319 watchdog_device.driver_closed = 1;
320
321 /* Refresh the timer for one more interval */
322 intel_scu_keepalive();
323
324 /* Reboot system (if force_boot is set) */
325 watchdog_fire();
326
327 /* We should only reach this point if force_boot is not set */
328 return 0;
329 }
330
intel_scu_write(struct file * file,char const * data,size_t len,loff_t * ppos)331 static ssize_t intel_scu_write(struct file *file,
332 char const *data,
333 size_t len,
334 loff_t *ppos)
335 {
336
337 if (watchdog_device.timer_started)
338 /* Watchdog already started, keep it alive */
339 intel_scu_keepalive();
340 else
341 /* Start watchdog with timer value set by init */
342 intel_scu_set_heartbeat(watchdog_device.timer_set);
343
344 return len;
345 }
346
intel_scu_ioctl(struct file * file,unsigned int cmd,unsigned long arg)347 static long intel_scu_ioctl(struct file *file,
348 unsigned int cmd,
349 unsigned long arg)
350 {
351 void __user *argp = (void __user *)arg;
352 u32 __user *p = argp;
353 u32 new_margin;
354
355
356 static const struct watchdog_info ident = {
357 .options = WDIOF_SETTIMEOUT
358 | WDIOF_KEEPALIVEPING,
359 .firmware_version = 0, /* @todo Get from SCU via
360 ipc_get_scu_fw_version()? */
361 .identity = "Intel_SCU IOH Watchdog" /* len < 32 */
362 };
363
364 switch (cmd) {
365 case WDIOC_GETSUPPORT:
366 return copy_to_user(argp,
367 &ident,
368 sizeof(ident)) ? -EFAULT : 0;
369 case WDIOC_GETSTATUS:
370 case WDIOC_GETBOOTSTATUS:
371 return put_user(0, p);
372 case WDIOC_KEEPALIVE:
373 intel_scu_keepalive();
374
375 return 0;
376 case WDIOC_SETTIMEOUT:
377 if (get_user(new_margin, p))
378 return -EFAULT;
379
380 if (check_timer_margin(new_margin))
381 return -EINVAL;
382
383 if (intel_scu_set_heartbeat(new_margin))
384 return -EINVAL;
385 return 0;
386 case WDIOC_GETTIMEOUT:
387 return put_user(watchdog_device.soft_threshold, p);
388
389 default:
390 return -ENOTTY;
391 }
392 }
393
394 /*
395 * Notifier for system down
396 */
intel_scu_notify_sys(struct notifier_block * this,unsigned long code,void * another_unused)397 static int intel_scu_notify_sys(struct notifier_block *this,
398 unsigned long code,
399 void *another_unused)
400 {
401 if (code == SYS_DOWN || code == SYS_HALT)
402 /* Turn off the watchdog timer. */
403 intel_scu_stop();
404 return NOTIFY_DONE;
405 }
406
407 /*
408 * Kernel Interfaces
409 */
410 static const struct file_operations intel_scu_fops = {
411 .owner = THIS_MODULE,
412 .llseek = no_llseek,
413 .write = intel_scu_write,
414 .unlocked_ioctl = intel_scu_ioctl,
415 .compat_ioctl = compat_ptr_ioctl,
416 .open = intel_scu_open,
417 .release = intel_scu_release,
418 };
419
intel_scu_watchdog_init(void)420 static int __init intel_scu_watchdog_init(void)
421 {
422 int ret;
423 u32 __iomem *tmp_addr;
424
425 /*
426 * We don't really need to check this as the SFI timer get will fail
427 * but if we do so we can exit with a clearer reason and no noise.
428 *
429 * If it isn't an intel MID device then it doesn't have this watchdog
430 */
431 if (!intel_mid_identify_cpu())
432 return -ENODEV;
433
434 /* Check boot parameters to verify that their initial values */
435 /* are in range. */
436 /* Check value of timer_set boot parameter */
437 if ((timer_set < MIN_TIME_CYCLE) ||
438 (timer_set > MAX_TIME - MIN_TIME_CYCLE)) {
439 pr_err("value of timer_set %x (hex) is out of range from %x to %x (hex)\n",
440 timer_set, MIN_TIME_CYCLE, MAX_TIME - MIN_TIME_CYCLE);
441 return -EINVAL;
442 }
443
444 /* Check value of timer_margin boot parameter */
445 if (check_timer_margin(timer_margin))
446 return -EINVAL;
447
448 watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);
449
450 if (watchdog_device.timer_tbl_ptr == NULL) {
451 pr_debug("timer is not available\n");
452 return -ENODEV;
453 }
454 /* make sure the timer exists */
455 if (watchdog_device.timer_tbl_ptr->phys_addr == 0) {
456 pr_debug("timer %d does not have valid physical memory\n",
457 sfi_mtimer_num);
458 return -ENODEV;
459 }
460
461 if (watchdog_device.timer_tbl_ptr->irq == 0) {
462 pr_debug("timer %d invalid irq\n", sfi_mtimer_num);
463 return -ENODEV;
464 }
465
466 tmp_addr = ioremap(watchdog_device.timer_tbl_ptr->phys_addr,
467 20);
468
469 if (tmp_addr == NULL) {
470 pr_debug("timer unable to ioremap\n");
471 return -ENOMEM;
472 }
473
474 watchdog_device.timer_load_count_addr = tmp_addr++;
475 watchdog_device.timer_current_value_addr = tmp_addr++;
476 watchdog_device.timer_control_addr = tmp_addr++;
477 watchdog_device.timer_clear_interrupt_addr = tmp_addr++;
478 watchdog_device.timer_interrupt_status_addr = tmp_addr++;
479
480 /* Set the default time values in device structure */
481
482 watchdog_device.timer_set = timer_set;
483 watchdog_device.threshold =
484 timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
485 watchdog_device.soft_threshold =
486 (watchdog_device.timer_set - timer_margin)
487 * watchdog_device.timer_tbl_ptr->freq_hz;
488
489
490 watchdog_device.intel_scu_notifier.notifier_call =
491 intel_scu_notify_sys;
492
493 ret = register_reboot_notifier(&watchdog_device.intel_scu_notifier);
494 if (ret) {
495 pr_err("cannot register notifier %d)\n", ret);
496 goto register_reboot_error;
497 }
498
499 watchdog_device.miscdev.minor = WATCHDOG_MINOR;
500 watchdog_device.miscdev.name = "watchdog";
501 watchdog_device.miscdev.fops = &intel_scu_fops;
502
503 ret = misc_register(&watchdog_device.miscdev);
504 if (ret) {
505 pr_err("cannot register miscdev %d err =%d\n",
506 WATCHDOG_MINOR, ret);
507 goto misc_register_error;
508 }
509
510 ret = request_irq((unsigned int)watchdog_device.timer_tbl_ptr->irq,
511 watchdog_timer_interrupt,
512 IRQF_SHARED, "watchdog",
513 &watchdog_device.timer_load_count_addr);
514 if (ret) {
515 pr_err("error requesting irq %d\n", ret);
516 goto request_irq_error;
517 }
518 /* Make sure timer is disabled before returning */
519 intel_scu_stop();
520 return 0;
521
522 /* error cleanup */
523
524 request_irq_error:
525 misc_deregister(&watchdog_device.miscdev);
526 misc_register_error:
527 unregister_reboot_notifier(&watchdog_device.intel_scu_notifier);
528 register_reboot_error:
529 intel_scu_stop();
530 iounmap(watchdog_device.timer_load_count_addr);
531 return ret;
532 }
533 late_initcall(intel_scu_watchdog_init);
534