1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for CPM (SCC/SMC) serial ports; core driver
4 *
5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
6 * Based on ppc8xx.c by Thomas Gleixner
7 * Based on drivers/serial/amba.c by Russell King
8 *
9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
10 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 *
12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
13 * (C) 2004 Intracom, S.A.
14 * (C) 2005-2006 MontaVista Software, Inc.
15 * Vitaly Bordug <vbordug@ru.mvista.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/ioport.h>
22 #include <linux/init.h>
23 #include <linux/serial.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/device.h>
27 #include <linux/memblock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fs_uart_pd.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/clk.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/delay.h>
39 #include <asm/fs_pd.h>
40 #include <asm/udbg.h>
41
42 #include <linux/serial_core.h>
43 #include <linux/kernel.h>
44
45 #include "cpm_uart.h"
46
47
48 /**************************************************************/
49
50 static int cpm_uart_tx_pump(struct uart_port *port);
51 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
52 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
53 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
54
55 /**************************************************************/
56
57 #define HW_BUF_SPD_THRESHOLD 2400
58
59 /*
60 * Check, if transmit buffers are processed
61 */
cpm_uart_tx_empty(struct uart_port * port)62 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
63 {
64 struct uart_cpm_port *pinfo =
65 container_of(port, struct uart_cpm_port, port);
66 cbd_t __iomem *bdp = pinfo->tx_bd_base;
67 int ret = 0;
68
69 while (1) {
70 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
71 break;
72
73 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
74 ret = TIOCSER_TEMT;
75 break;
76 }
77 bdp++;
78 }
79
80 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
81
82 return ret;
83 }
84
cpm_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)85 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
86 {
87 struct uart_cpm_port *pinfo =
88 container_of(port, struct uart_cpm_port, port);
89
90 if (pinfo->gpios[GPIO_RTS])
91 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
92
93 if (pinfo->gpios[GPIO_DTR])
94 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
95 }
96
cpm_uart_get_mctrl(struct uart_port * port)97 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
98 {
99 struct uart_cpm_port *pinfo =
100 container_of(port, struct uart_cpm_port, port);
101 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
102
103 if (pinfo->gpios[GPIO_CTS]) {
104 if (gpiod_get_value(pinfo->gpios[GPIO_CTS]))
105 mctrl &= ~TIOCM_CTS;
106 }
107
108 if (pinfo->gpios[GPIO_DSR]) {
109 if (gpiod_get_value(pinfo->gpios[GPIO_DSR]))
110 mctrl &= ~TIOCM_DSR;
111 }
112
113 if (pinfo->gpios[GPIO_DCD]) {
114 if (gpiod_get_value(pinfo->gpios[GPIO_DCD]))
115 mctrl &= ~TIOCM_CAR;
116 }
117
118 if (pinfo->gpios[GPIO_RI]) {
119 if (!gpiod_get_value(pinfo->gpios[GPIO_RI]))
120 mctrl |= TIOCM_RNG;
121 }
122
123 return mctrl;
124 }
125
126 /*
127 * Stop transmitter
128 */
cpm_uart_stop_tx(struct uart_port * port)129 static void cpm_uart_stop_tx(struct uart_port *port)
130 {
131 struct uart_cpm_port *pinfo =
132 container_of(port, struct uart_cpm_port, port);
133 smc_t __iomem *smcp = pinfo->smcp;
134 scc_t __iomem *sccp = pinfo->sccp;
135
136 pr_debug("CPM uart[%d]:stop tx\n", port->line);
137
138 if (IS_SMC(pinfo))
139 clrbits8(&smcp->smc_smcm, SMCM_TX);
140 else
141 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
142 }
143
144 /*
145 * Start transmitter
146 */
cpm_uart_start_tx(struct uart_port * port)147 static void cpm_uart_start_tx(struct uart_port *port)
148 {
149 struct uart_cpm_port *pinfo =
150 container_of(port, struct uart_cpm_port, port);
151 smc_t __iomem *smcp = pinfo->smcp;
152 scc_t __iomem *sccp = pinfo->sccp;
153
154 pr_debug("CPM uart[%d]:start tx\n", port->line);
155
156 if (IS_SMC(pinfo)) {
157 if (in_8(&smcp->smc_smcm) & SMCM_TX)
158 return;
159 } else {
160 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
161 return;
162 }
163
164 if (cpm_uart_tx_pump(port) != 0) {
165 if (IS_SMC(pinfo)) {
166 setbits8(&smcp->smc_smcm, SMCM_TX);
167 } else {
168 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
169 }
170 }
171 }
172
173 /*
174 * Stop receiver
175 */
cpm_uart_stop_rx(struct uart_port * port)176 static void cpm_uart_stop_rx(struct uart_port *port)
177 {
178 struct uart_cpm_port *pinfo =
179 container_of(port, struct uart_cpm_port, port);
180 smc_t __iomem *smcp = pinfo->smcp;
181 scc_t __iomem *sccp = pinfo->sccp;
182
183 pr_debug("CPM uart[%d]:stop rx\n", port->line);
184
185 if (IS_SMC(pinfo))
186 clrbits8(&smcp->smc_smcm, SMCM_RX);
187 else
188 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
189 }
190
191 /*
192 * Generate a break.
193 */
cpm_uart_break_ctl(struct uart_port * port,int break_state)194 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
195 {
196 struct uart_cpm_port *pinfo =
197 container_of(port, struct uart_cpm_port, port);
198
199 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
200 break_state);
201
202 if (break_state)
203 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
204 else
205 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
206 }
207
208 /*
209 * Transmit characters, refill buffer descriptor, if possible
210 */
cpm_uart_int_tx(struct uart_port * port)211 static void cpm_uart_int_tx(struct uart_port *port)
212 {
213 pr_debug("CPM uart[%d]:TX INT\n", port->line);
214
215 cpm_uart_tx_pump(port);
216 }
217
218 #ifdef CONFIG_CONSOLE_POLL
219 static int serial_polled;
220 #endif
221
222 /*
223 * Receive characters
224 */
cpm_uart_int_rx(struct uart_port * port)225 static void cpm_uart_int_rx(struct uart_port *port)
226 {
227 int i;
228 unsigned char ch;
229 u8 *cp;
230 struct tty_port *tport = &port->state->port;
231 struct uart_cpm_port *pinfo =
232 container_of(port, struct uart_cpm_port, port);
233 cbd_t __iomem *bdp;
234 u16 status;
235 unsigned int flg;
236
237 pr_debug("CPM uart[%d]:RX INT\n", port->line);
238
239 /* Just loop through the closed BDs and copy the characters into
240 * the buffer.
241 */
242 bdp = pinfo->rx_cur;
243 for (;;) {
244 #ifdef CONFIG_CONSOLE_POLL
245 if (unlikely(serial_polled)) {
246 serial_polled = 0;
247 return;
248 }
249 #endif
250 /* get status */
251 status = in_be16(&bdp->cbd_sc);
252 /* If this one is empty, return happy */
253 if (status & BD_SC_EMPTY)
254 break;
255
256 /* get number of characters, and check spce in flip-buffer */
257 i = in_be16(&bdp->cbd_datlen);
258
259 /* If we have not enough room in tty flip buffer, then we try
260 * later, which will be the next rx-interrupt or a timeout
261 */
262 if (tty_buffer_request_room(tport, i) < i) {
263 printk(KERN_WARNING "No room in flip buffer\n");
264 return;
265 }
266
267 /* get pointer */
268 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
269
270 /* loop through the buffer */
271 while (i-- > 0) {
272 ch = *cp++;
273 port->icount.rx++;
274 flg = TTY_NORMAL;
275
276 if (status &
277 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
278 goto handle_error;
279 if (uart_handle_sysrq_char(port, ch))
280 continue;
281 #ifdef CONFIG_CONSOLE_POLL
282 if (unlikely(serial_polled)) {
283 serial_polled = 0;
284 return;
285 }
286 #endif
287 error_return:
288 tty_insert_flip_char(tport, ch, flg);
289
290 } /* End while (i--) */
291
292 /* This BD is ready to be used again. Clear status. get next */
293 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
294 BD_SC_OV | BD_SC_ID);
295 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
296
297 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
298 bdp = pinfo->rx_bd_base;
299 else
300 bdp++;
301
302 } /* End for (;;) */
303
304 /* Write back buffer pointer */
305 pinfo->rx_cur = bdp;
306
307 /* activate BH processing */
308 tty_flip_buffer_push(tport);
309
310 return;
311
312 /* Error processing */
313
314 handle_error:
315 /* Statistics */
316 if (status & BD_SC_BR)
317 port->icount.brk++;
318 if (status & BD_SC_PR)
319 port->icount.parity++;
320 if (status & BD_SC_FR)
321 port->icount.frame++;
322 if (status & BD_SC_OV)
323 port->icount.overrun++;
324
325 /* Mask out ignored conditions */
326 status &= port->read_status_mask;
327
328 /* Handle the remaining ones */
329 if (status & BD_SC_BR)
330 flg = TTY_BREAK;
331 else if (status & BD_SC_PR)
332 flg = TTY_PARITY;
333 else if (status & BD_SC_FR)
334 flg = TTY_FRAME;
335
336 /* overrun does not affect the current character ! */
337 if (status & BD_SC_OV) {
338 ch = 0;
339 flg = TTY_OVERRUN;
340 /* We skip this buffer */
341 /* CHECK: Is really nothing senseful there */
342 /* ASSUMPTION: it contains nothing valid */
343 i = 0;
344 }
345 port->sysrq = 0;
346 goto error_return;
347 }
348
349 /*
350 * Asynchron mode interrupt handler
351 */
cpm_uart_int(int irq,void * data)352 static irqreturn_t cpm_uart_int(int irq, void *data)
353 {
354 u8 events;
355 struct uart_port *port = data;
356 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
357 smc_t __iomem *smcp = pinfo->smcp;
358 scc_t __iomem *sccp = pinfo->sccp;
359
360 pr_debug("CPM uart[%d]:IRQ\n", port->line);
361
362 if (IS_SMC(pinfo)) {
363 events = in_8(&smcp->smc_smce);
364 out_8(&smcp->smc_smce, events);
365 if (events & SMCM_BRKE)
366 uart_handle_break(port);
367 if (events & SMCM_RX)
368 cpm_uart_int_rx(port);
369 if (events & SMCM_TX)
370 cpm_uart_int_tx(port);
371 } else {
372 events = in_be16(&sccp->scc_scce);
373 out_be16(&sccp->scc_scce, events);
374 if (events & UART_SCCM_BRKE)
375 uart_handle_break(port);
376 if (events & UART_SCCM_RX)
377 cpm_uart_int_rx(port);
378 if (events & UART_SCCM_TX)
379 cpm_uart_int_tx(port);
380 }
381 return (events) ? IRQ_HANDLED : IRQ_NONE;
382 }
383
cpm_uart_startup(struct uart_port * port)384 static int cpm_uart_startup(struct uart_port *port)
385 {
386 int retval;
387 struct uart_cpm_port *pinfo =
388 container_of(port, struct uart_cpm_port, port);
389
390 pr_debug("CPM uart[%d]:startup\n", port->line);
391
392 /* If the port is not the console, make sure rx is disabled. */
393 if (!(pinfo->flags & FLAG_CONSOLE)) {
394 /* Disable UART rx */
395 if (IS_SMC(pinfo)) {
396 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
397 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
398 } else {
399 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
400 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
401 }
402 cpm_uart_initbd(pinfo);
403 if (IS_SMC(pinfo)) {
404 out_be32(&pinfo->smcup->smc_rstate, 0);
405 out_be32(&pinfo->smcup->smc_tstate, 0);
406 out_be16(&pinfo->smcup->smc_rbptr,
407 in_be16(&pinfo->smcup->smc_rbase));
408 out_be16(&pinfo->smcup->smc_tbptr,
409 in_be16(&pinfo->smcup->smc_tbase));
410 } else {
411 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
412 }
413 }
414 /* Install interrupt handler. */
415 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
416 if (retval)
417 return retval;
418
419 /* Startup rx-int */
420 if (IS_SMC(pinfo)) {
421 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
422 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
423 } else {
424 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
425 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
426 }
427
428 return 0;
429 }
430
cpm_uart_wait_until_send(struct uart_cpm_port * pinfo)431 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
432 {
433 set_current_state(TASK_UNINTERRUPTIBLE);
434 schedule_timeout(pinfo->wait_closing);
435 }
436
437 /*
438 * Shutdown the uart
439 */
cpm_uart_shutdown(struct uart_port * port)440 static void cpm_uart_shutdown(struct uart_port *port)
441 {
442 struct uart_cpm_port *pinfo =
443 container_of(port, struct uart_cpm_port, port);
444
445 pr_debug("CPM uart[%d]:shutdown\n", port->line);
446
447 /* free interrupt handler */
448 free_irq(port->irq, port);
449
450 /* If the port is not the console, disable Rx and Tx. */
451 if (!(pinfo->flags & FLAG_CONSOLE)) {
452 /* Wait for all the BDs marked sent */
453 while(!cpm_uart_tx_empty(port)) {
454 set_current_state(TASK_UNINTERRUPTIBLE);
455 schedule_timeout(2);
456 }
457
458 if (pinfo->wait_closing)
459 cpm_uart_wait_until_send(pinfo);
460
461 /* Stop uarts */
462 if (IS_SMC(pinfo)) {
463 smc_t __iomem *smcp = pinfo->smcp;
464 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
465 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
466 } else {
467 scc_t __iomem *sccp = pinfo->sccp;
468 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
469 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
470 }
471
472 /* Shut them really down and reinit buffer descriptors */
473 if (IS_SMC(pinfo)) {
474 out_be16(&pinfo->smcup->smc_brkcr, 0);
475 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
476 } else {
477 out_be16(&pinfo->sccup->scc_brkcr, 0);
478 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
479 }
480
481 cpm_uart_initbd(pinfo);
482 }
483 }
484
cpm_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)485 static void cpm_uart_set_termios(struct uart_port *port,
486 struct ktermios *termios,
487 struct ktermios *old)
488 {
489 int baud;
490 unsigned long flags;
491 u16 cval, scval, prev_mode;
492 int bits, sbits;
493 struct uart_cpm_port *pinfo =
494 container_of(port, struct uart_cpm_port, port);
495 smc_t __iomem *smcp = pinfo->smcp;
496 scc_t __iomem *sccp = pinfo->sccp;
497 int maxidl;
498
499 pr_debug("CPM uart[%d]:set_termios\n", port->line);
500
501 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
502 if (baud < HW_BUF_SPD_THRESHOLD ||
503 (pinfo->port.state && pinfo->port.state->port.low_latency))
504 pinfo->rx_fifosize = 1;
505 else
506 pinfo->rx_fifosize = RX_BUF_SIZE;
507
508 /* MAXIDL is the timeout after which a receive buffer is closed
509 * when not full if no more characters are received.
510 * We calculate it from the baudrate so that the duration is
511 * always the same at standard rates: about 4ms.
512 */
513 maxidl = baud / 2400;
514 if (maxidl < 1)
515 maxidl = 1;
516 if (maxidl > 0x10)
517 maxidl = 0x10;
518
519 /* Character length programmed into the mode register is the
520 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
521 * 1 or 2 stop bits, minus 1.
522 * The value 'bits' counts this for us.
523 */
524 cval = 0;
525 scval = 0;
526
527 /* byte size */
528 switch (termios->c_cflag & CSIZE) {
529 case CS5:
530 bits = 5;
531 break;
532 case CS6:
533 bits = 6;
534 break;
535 case CS7:
536 bits = 7;
537 break;
538 case CS8:
539 bits = 8;
540 break;
541 /* Never happens, but GCC is too dumb to figure it out */
542 default:
543 bits = 8;
544 break;
545 }
546 sbits = bits - 5;
547
548 if (termios->c_cflag & CSTOPB) {
549 cval |= SMCMR_SL; /* Two stops */
550 scval |= SCU_PSMR_SL;
551 bits++;
552 }
553
554 if (termios->c_cflag & PARENB) {
555 cval |= SMCMR_PEN;
556 scval |= SCU_PSMR_PEN;
557 bits++;
558 if (!(termios->c_cflag & PARODD)) {
559 cval |= SMCMR_PM_EVEN;
560 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
561 }
562 }
563
564 /*
565 * Update the timeout
566 */
567 uart_update_timeout(port, termios->c_cflag, baud);
568
569 /*
570 * Set up parity check flag
571 */
572 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
573 if (termios->c_iflag & INPCK)
574 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
575 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
576 port->read_status_mask |= BD_SC_BR;
577
578 /*
579 * Characters to ignore
580 */
581 port->ignore_status_mask = 0;
582 if (termios->c_iflag & IGNPAR)
583 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
584 if (termios->c_iflag & IGNBRK) {
585 port->ignore_status_mask |= BD_SC_BR;
586 /*
587 * If we're ignore parity and break indicators, ignore
588 * overruns too. (For real raw support).
589 */
590 if (termios->c_iflag & IGNPAR)
591 port->ignore_status_mask |= BD_SC_OV;
592 }
593 /*
594 * !!! ignore all characters if CREAD is not set
595 */
596 if ((termios->c_cflag & CREAD) == 0)
597 port->read_status_mask &= ~BD_SC_EMPTY;
598
599 spin_lock_irqsave(&port->lock, flags);
600
601 /* Start bit has not been added (so don't, because we would just
602 * subtract it later), and we need to add one for the number of
603 * stops bits (there is always at least one).
604 */
605 bits++;
606 if (IS_SMC(pinfo)) {
607 /*
608 * MRBLR can be changed while an SMC/SCC is operating only
609 * if it is done in a single bus cycle with one 16-bit move
610 * (not two 8-bit bus cycles back-to-back). This occurs when
611 * the cp shifts control to the next RxBD, so the change does
612 * not take effect immediately. To guarantee the exact RxBD
613 * on which the change occurs, change MRBLR only while the
614 * SMC/SCC receiver is disabled.
615 */
616 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
617 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
618
619 /* Set the mode register. We want to keep a copy of the
620 * enables, because we want to put them back if they were
621 * present.
622 */
623 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
624 /* Output in *one* operation, so we don't interrupt RX/TX if they
625 * were already enabled. */
626 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
627 SMCMR_SM_UART | prev_mode);
628 } else {
629 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
630 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
631 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
632 }
633
634 if (pinfo->clk)
635 clk_set_rate(pinfo->clk, baud);
636 else
637 cpm_set_brg(pinfo->brg - 1, baud);
638 spin_unlock_irqrestore(&port->lock, flags);
639 }
640
cpm_uart_type(struct uart_port * port)641 static const char *cpm_uart_type(struct uart_port *port)
642 {
643 pr_debug("CPM uart[%d]:uart_type\n", port->line);
644
645 return port->type == PORT_CPM ? "CPM UART" : NULL;
646 }
647
648 /*
649 * verify the new serial_struct (for TIOCSSERIAL).
650 */
cpm_uart_verify_port(struct uart_port * port,struct serial_struct * ser)651 static int cpm_uart_verify_port(struct uart_port *port,
652 struct serial_struct *ser)
653 {
654 int ret = 0;
655
656 pr_debug("CPM uart[%d]:verify_port\n", port->line);
657
658 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
659 ret = -EINVAL;
660 if (ser->irq < 0 || ser->irq >= nr_irqs)
661 ret = -EINVAL;
662 if (ser->baud_base < 9600)
663 ret = -EINVAL;
664 return ret;
665 }
666
667 /*
668 * Transmit characters, refill buffer descriptor, if possible
669 */
cpm_uart_tx_pump(struct uart_port * port)670 static int cpm_uart_tx_pump(struct uart_port *port)
671 {
672 cbd_t __iomem *bdp;
673 u8 *p;
674 int count;
675 struct uart_cpm_port *pinfo =
676 container_of(port, struct uart_cpm_port, port);
677 struct circ_buf *xmit = &port->state->xmit;
678
679 /* Handle xon/xoff */
680 if (port->x_char) {
681 /* Pick next descriptor and fill from buffer */
682 bdp = pinfo->tx_cur;
683
684 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
685
686 *p++ = port->x_char;
687
688 out_be16(&bdp->cbd_datlen, 1);
689 setbits16(&bdp->cbd_sc, BD_SC_READY);
690 /* Get next BD. */
691 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
692 bdp = pinfo->tx_bd_base;
693 else
694 bdp++;
695 pinfo->tx_cur = bdp;
696
697 port->icount.tx++;
698 port->x_char = 0;
699 return 1;
700 }
701
702 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
703 cpm_uart_stop_tx(port);
704 return 0;
705 }
706
707 /* Pick next descriptor and fill from buffer */
708 bdp = pinfo->tx_cur;
709
710 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
711 xmit->tail != xmit->head) {
712 count = 0;
713 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
714 while (count < pinfo->tx_fifosize) {
715 *p++ = xmit->buf[xmit->tail];
716 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
717 port->icount.tx++;
718 count++;
719 if (xmit->head == xmit->tail)
720 break;
721 }
722 out_be16(&bdp->cbd_datlen, count);
723 setbits16(&bdp->cbd_sc, BD_SC_READY);
724 /* Get next BD. */
725 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
726 bdp = pinfo->tx_bd_base;
727 else
728 bdp++;
729 }
730 pinfo->tx_cur = bdp;
731
732 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
733 uart_write_wakeup(port);
734
735 if (uart_circ_empty(xmit)) {
736 cpm_uart_stop_tx(port);
737 return 0;
738 }
739
740 return 1;
741 }
742
743 /*
744 * init buffer descriptors
745 */
cpm_uart_initbd(struct uart_cpm_port * pinfo)746 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
747 {
748 int i;
749 u8 *mem_addr;
750 cbd_t __iomem *bdp;
751
752 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
753
754 /* Set the physical address of the host memory
755 * buffers in the buffer descriptors, and the
756 * virtual address for us to work with.
757 */
758 mem_addr = pinfo->mem_addr;
759 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
760 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
761 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
762 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
763 mem_addr += pinfo->rx_fifosize;
764 }
765
766 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
767 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
768
769 /* Set the physical address of the host memory
770 * buffers in the buffer descriptors, and the
771 * virtual address for us to work with.
772 */
773 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
774 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
775 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
776 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
777 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
778 mem_addr += pinfo->tx_fifosize;
779 }
780
781 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
782 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
783 }
784
cpm_uart_init_scc(struct uart_cpm_port * pinfo)785 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
786 {
787 scc_t __iomem *scp;
788 scc_uart_t __iomem *sup;
789
790 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
791
792 scp = pinfo->sccp;
793 sup = pinfo->sccup;
794
795 /* Store address */
796 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
797 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
798 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
799 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
800
801 /* Set up the uart parameters in the
802 * parameter ram.
803 */
804
805 cpm_set_scc_fcr(sup);
806
807 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
808 out_be16(&sup->scc_maxidl, 0x10);
809 out_be16(&sup->scc_brkcr, 1);
810 out_be16(&sup->scc_parec, 0);
811 out_be16(&sup->scc_frmec, 0);
812 out_be16(&sup->scc_nosec, 0);
813 out_be16(&sup->scc_brkec, 0);
814 out_be16(&sup->scc_uaddr1, 0);
815 out_be16(&sup->scc_uaddr2, 0);
816 out_be16(&sup->scc_toseq, 0);
817 out_be16(&sup->scc_char1, 0x8000);
818 out_be16(&sup->scc_char2, 0x8000);
819 out_be16(&sup->scc_char3, 0x8000);
820 out_be16(&sup->scc_char4, 0x8000);
821 out_be16(&sup->scc_char5, 0x8000);
822 out_be16(&sup->scc_char6, 0x8000);
823 out_be16(&sup->scc_char7, 0x8000);
824 out_be16(&sup->scc_char8, 0x8000);
825 out_be16(&sup->scc_rccm, 0xc0ff);
826
827 /* Send the CPM an initialize command.
828 */
829 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
830
831 /* Set UART mode, 8 bit, no parity, one stop.
832 * Enable receive and transmit.
833 */
834 out_be32(&scp->scc_gsmrh, 0);
835 out_be32(&scp->scc_gsmrl,
836 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
837
838 /* Enable rx interrupts and clear all pending events. */
839 out_be16(&scp->scc_sccm, 0);
840 out_be16(&scp->scc_scce, 0xffff);
841 out_be16(&scp->scc_dsr, 0x7e7e);
842 out_be16(&scp->scc_psmr, 0x3000);
843
844 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
845 }
846
cpm_uart_init_smc(struct uart_cpm_port * pinfo)847 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
848 {
849 smc_t __iomem *sp;
850 smc_uart_t __iomem *up;
851
852 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
853
854 sp = pinfo->smcp;
855 up = pinfo->smcup;
856
857 /* Store address */
858 out_be16(&pinfo->smcup->smc_rbase,
859 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
860 out_be16(&pinfo->smcup->smc_tbase,
861 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
862
863 /*
864 * In case SMC is being relocated...
865 */
866 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
867 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
868 out_be32(&up->smc_rstate, 0);
869 out_be32(&up->smc_tstate, 0);
870 out_be16(&up->smc_brkcr, 1); /* number of break chars */
871 out_be16(&up->smc_brkec, 0);
872
873 /* Set up the uart parameters in the
874 * parameter ram.
875 */
876 cpm_set_smc_fcr(up);
877
878 /* Using idle character time requires some additional tuning. */
879 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
880 out_be16(&up->smc_maxidl, 0x10);
881 out_be16(&up->smc_brklen, 0);
882 out_be16(&up->smc_brkec, 0);
883 out_be16(&up->smc_brkcr, 1);
884
885 /* Set UART mode, 8 bit, no parity, one stop.
886 * Enable receive and transmit.
887 */
888 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
889
890 /* Enable only rx interrupts clear all pending events. */
891 out_8(&sp->smc_smcm, 0);
892 out_8(&sp->smc_smce, 0xff);
893
894 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
895 }
896
897 /*
898 * Initialize port. This is called from early_console stuff
899 * so we have to be careful here !
900 */
cpm_uart_request_port(struct uart_port * port)901 static int cpm_uart_request_port(struct uart_port *port)
902 {
903 struct uart_cpm_port *pinfo =
904 container_of(port, struct uart_cpm_port, port);
905 int ret;
906
907 pr_debug("CPM uart[%d]:request port\n", port->line);
908
909 if (pinfo->flags & FLAG_CONSOLE)
910 return 0;
911
912 if (IS_SMC(pinfo)) {
913 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
914 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
915 } else {
916 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
917 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
918 }
919
920 ret = cpm_uart_allocbuf(pinfo, 0);
921
922 if (ret)
923 return ret;
924
925 cpm_uart_initbd(pinfo);
926 if (IS_SMC(pinfo))
927 cpm_uart_init_smc(pinfo);
928 else
929 cpm_uart_init_scc(pinfo);
930
931 return 0;
932 }
933
cpm_uart_release_port(struct uart_port * port)934 static void cpm_uart_release_port(struct uart_port *port)
935 {
936 struct uart_cpm_port *pinfo =
937 container_of(port, struct uart_cpm_port, port);
938
939 if (!(pinfo->flags & FLAG_CONSOLE))
940 cpm_uart_freebuf(pinfo);
941 }
942
943 /*
944 * Configure/autoconfigure the port.
945 */
cpm_uart_config_port(struct uart_port * port,int flags)946 static void cpm_uart_config_port(struct uart_port *port, int flags)
947 {
948 pr_debug("CPM uart[%d]:config_port\n", port->line);
949
950 if (flags & UART_CONFIG_TYPE) {
951 port->type = PORT_CPM;
952 cpm_uart_request_port(port);
953 }
954 }
955
956 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
957 /*
958 * Write a string to the serial port
959 * Note that this is called with interrupts already disabled
960 */
cpm_uart_early_write(struct uart_cpm_port * pinfo,const char * string,u_int count,bool handle_linefeed)961 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
962 const char *string, u_int count, bool handle_linefeed)
963 {
964 unsigned int i;
965 cbd_t __iomem *bdp, *bdbase;
966 unsigned char *cpm_outp_addr;
967
968 /* Get the address of the host memory buffer.
969 */
970 bdp = pinfo->tx_cur;
971 bdbase = pinfo->tx_bd_base;
972
973 /*
974 * Now, do each character. This is not as bad as it looks
975 * since this is a holding FIFO and not a transmitting FIFO.
976 * We could add the complexity of filling the entire transmit
977 * buffer, but we would just wait longer between accesses......
978 */
979 for (i = 0; i < count; i++, string++) {
980 /* Wait for transmitter fifo to empty.
981 * Ready indicates output is ready, and xmt is doing
982 * that, not that it is ready for us to send.
983 */
984 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
985 ;
986
987 /* Send the character out.
988 * If the buffer address is in the CPM DPRAM, don't
989 * convert it.
990 */
991 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
992 pinfo);
993 *cpm_outp_addr = *string;
994
995 out_be16(&bdp->cbd_datlen, 1);
996 setbits16(&bdp->cbd_sc, BD_SC_READY);
997
998 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
999 bdp = bdbase;
1000 else
1001 bdp++;
1002
1003 /* if a LF, also do CR... */
1004 if (handle_linefeed && *string == 10) {
1005 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1006 ;
1007
1008 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1009 pinfo);
1010 *cpm_outp_addr = 13;
1011
1012 out_be16(&bdp->cbd_datlen, 1);
1013 setbits16(&bdp->cbd_sc, BD_SC_READY);
1014
1015 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1016 bdp = bdbase;
1017 else
1018 bdp++;
1019 }
1020 }
1021
1022 /*
1023 * Finally, Wait for transmitter & holding register to empty
1024 * and restore the IER
1025 */
1026 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1027 ;
1028
1029 pinfo->tx_cur = bdp;
1030 }
1031 #endif
1032
1033 #ifdef CONFIG_CONSOLE_POLL
1034 /* Serial polling routines for writing and reading from the uart while
1035 * in an interrupt or debug context.
1036 */
1037
1038 #define GDB_BUF_SIZE 512 /* power of 2, please */
1039
1040 static char poll_buf[GDB_BUF_SIZE];
1041 static char *pollp;
1042 static int poll_chars;
1043
poll_wait_key(char * obuf,struct uart_cpm_port * pinfo)1044 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1045 {
1046 u_char c, *cp;
1047 volatile cbd_t *bdp;
1048 int i;
1049
1050 /* Get the address of the host memory buffer.
1051 */
1052 bdp = pinfo->rx_cur;
1053 if (bdp->cbd_sc & BD_SC_EMPTY)
1054 return NO_POLL_CHAR;
1055
1056 /* If the buffer address is in the CPM DPRAM, don't
1057 * convert it.
1058 */
1059 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1060
1061 if (obuf) {
1062 i = c = bdp->cbd_datlen;
1063 while (i-- > 0)
1064 *obuf++ = *cp++;
1065 } else
1066 c = *cp;
1067 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1068 bdp->cbd_sc |= BD_SC_EMPTY;
1069
1070 if (bdp->cbd_sc & BD_SC_WRAP)
1071 bdp = pinfo->rx_bd_base;
1072 else
1073 bdp++;
1074 pinfo->rx_cur = (cbd_t *)bdp;
1075
1076 return (int)c;
1077 }
1078
cpm_get_poll_char(struct uart_port * port)1079 static int cpm_get_poll_char(struct uart_port *port)
1080 {
1081 struct uart_cpm_port *pinfo =
1082 container_of(port, struct uart_cpm_port, port);
1083
1084 if (!serial_polled) {
1085 serial_polled = 1;
1086 poll_chars = 0;
1087 }
1088 if (poll_chars <= 0) {
1089 int ret = poll_wait_key(poll_buf, pinfo);
1090
1091 if (ret == NO_POLL_CHAR)
1092 return ret;
1093 poll_chars = ret;
1094 pollp = poll_buf;
1095 }
1096 poll_chars--;
1097 return *pollp++;
1098 }
1099
cpm_put_poll_char(struct uart_port * port,unsigned char c)1100 static void cpm_put_poll_char(struct uart_port *port,
1101 unsigned char c)
1102 {
1103 struct uart_cpm_port *pinfo =
1104 container_of(port, struct uart_cpm_port, port);
1105 static char ch[2];
1106
1107 ch[0] = (char)c;
1108 cpm_uart_early_write(pinfo, ch, 1, false);
1109 }
1110 #endif /* CONFIG_CONSOLE_POLL */
1111
1112 static const struct uart_ops cpm_uart_pops = {
1113 .tx_empty = cpm_uart_tx_empty,
1114 .set_mctrl = cpm_uart_set_mctrl,
1115 .get_mctrl = cpm_uart_get_mctrl,
1116 .stop_tx = cpm_uart_stop_tx,
1117 .start_tx = cpm_uart_start_tx,
1118 .stop_rx = cpm_uart_stop_rx,
1119 .break_ctl = cpm_uart_break_ctl,
1120 .startup = cpm_uart_startup,
1121 .shutdown = cpm_uart_shutdown,
1122 .set_termios = cpm_uart_set_termios,
1123 .type = cpm_uart_type,
1124 .release_port = cpm_uart_release_port,
1125 .request_port = cpm_uart_request_port,
1126 .config_port = cpm_uart_config_port,
1127 .verify_port = cpm_uart_verify_port,
1128 #ifdef CONFIG_CONSOLE_POLL
1129 .poll_get_char = cpm_get_poll_char,
1130 .poll_put_char = cpm_put_poll_char,
1131 #endif
1132 };
1133
1134 struct uart_cpm_port cpm_uart_ports[UART_NR];
1135
cpm_uart_init_port(struct device_node * np,struct uart_cpm_port * pinfo)1136 static int cpm_uart_init_port(struct device_node *np,
1137 struct uart_cpm_port *pinfo)
1138 {
1139 const u32 *data;
1140 void __iomem *mem, *pram;
1141 struct device *dev = pinfo->port.dev;
1142 int len;
1143 int ret;
1144 int i;
1145
1146 data = of_get_property(np, "clock", NULL);
1147 if (data) {
1148 struct clk *clk = clk_get(NULL, (const char*)data);
1149 if (!IS_ERR(clk))
1150 pinfo->clk = clk;
1151 }
1152 if (!pinfo->clk) {
1153 data = of_get_property(np, "fsl,cpm-brg", &len);
1154 if (!data || len != 4) {
1155 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1156 "fsl,cpm-brg property.\n", np);
1157 return -EINVAL;
1158 }
1159 pinfo->brg = *data;
1160 }
1161
1162 data = of_get_property(np, "fsl,cpm-command", &len);
1163 if (!data || len != 4) {
1164 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1165 "fsl,cpm-command property.\n", np);
1166 return -EINVAL;
1167 }
1168 pinfo->command = *data;
1169
1170 mem = of_iomap(np, 0);
1171 if (!mem)
1172 return -ENOMEM;
1173
1174 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1175 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1176 pinfo->sccp = mem;
1177 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1178 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1179 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1180 pinfo->flags |= FLAG_SMC;
1181 pinfo->smcp = mem;
1182 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1183 } else {
1184 ret = -ENODEV;
1185 goto out_mem;
1186 }
1187
1188 if (!pram) {
1189 ret = -ENOMEM;
1190 goto out_mem;
1191 }
1192
1193 pinfo->tx_nrfifos = TX_NUM_FIFO;
1194 pinfo->tx_fifosize = TX_BUF_SIZE;
1195 pinfo->rx_nrfifos = RX_NUM_FIFO;
1196 pinfo->rx_fifosize = RX_BUF_SIZE;
1197
1198 pinfo->port.uartclk = ppc_proc_freq;
1199 pinfo->port.mapbase = (unsigned long)mem;
1200 pinfo->port.type = PORT_CPM;
1201 pinfo->port.ops = &cpm_uart_pops;
1202 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE);
1203 pinfo->port.iotype = UPIO_MEM;
1204 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1205 spin_lock_init(&pinfo->port.lock);
1206
1207 pinfo->port.irq = irq_of_parse_and_map(np, 0);
1208 if (pinfo->port.irq == NO_IRQ) {
1209 ret = -EINVAL;
1210 goto out_pram;
1211 }
1212
1213 for (i = 0; i < NUM_GPIOS; i++) {
1214 struct gpio_desc *gpiod;
1215
1216 pinfo->gpios[i] = NULL;
1217
1218 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS);
1219
1220 if (IS_ERR(gpiod)) {
1221 ret = PTR_ERR(gpiod);
1222 goto out_irq;
1223 }
1224
1225 if (gpiod) {
1226 if (i == GPIO_RTS || i == GPIO_DTR)
1227 ret = gpiod_direction_output(gpiod, 0);
1228 else
1229 ret = gpiod_direction_input(gpiod);
1230 if (ret) {
1231 pr_err("can't set direction for gpio #%d: %d\n",
1232 i, ret);
1233 continue;
1234 }
1235 pinfo->gpios[i] = gpiod;
1236 }
1237 }
1238
1239 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1240 udbg_putc = NULL;
1241 #endif
1242
1243 return cpm_uart_request_port(&pinfo->port);
1244
1245 out_irq:
1246 irq_dispose_mapping(pinfo->port.irq);
1247 out_pram:
1248 cpm_uart_unmap_pram(pinfo, pram);
1249 out_mem:
1250 iounmap(mem);
1251 return ret;
1252 }
1253
1254 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1255 /*
1256 * Print a string to the serial port trying not to disturb
1257 * any possible real use of the port...
1258 *
1259 * Note that this is called with interrupts already disabled
1260 */
cpm_uart_console_write(struct console * co,const char * s,u_int count)1261 static void cpm_uart_console_write(struct console *co, const char *s,
1262 u_int count)
1263 {
1264 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1265 unsigned long flags;
1266 int nolock = oops_in_progress;
1267
1268 if (unlikely(nolock)) {
1269 local_irq_save(flags);
1270 } else {
1271 spin_lock_irqsave(&pinfo->port.lock, flags);
1272 }
1273
1274 cpm_uart_early_write(pinfo, s, count, true);
1275
1276 if (unlikely(nolock)) {
1277 local_irq_restore(flags);
1278 } else {
1279 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1280 }
1281 }
1282
1283
cpm_uart_console_setup(struct console * co,char * options)1284 static int __init cpm_uart_console_setup(struct console *co, char *options)
1285 {
1286 int baud = 38400;
1287 int bits = 8;
1288 int parity = 'n';
1289 int flow = 'n';
1290 int ret;
1291 struct uart_cpm_port *pinfo;
1292 struct uart_port *port;
1293
1294 struct device_node *np;
1295 int i = 0;
1296
1297 if (co->index >= UART_NR) {
1298 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1299 co->index);
1300 return -ENODEV;
1301 }
1302
1303 for_each_node_by_type(np, "serial") {
1304 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1305 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1306 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1307 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1308 continue;
1309
1310 if (i++ == co->index)
1311 break;
1312 }
1313
1314 if (!np)
1315 return -ENODEV;
1316
1317 pinfo = &cpm_uart_ports[co->index];
1318
1319 pinfo->flags |= FLAG_CONSOLE;
1320 port = &pinfo->port;
1321
1322 ret = cpm_uart_init_port(np, pinfo);
1323 of_node_put(np);
1324 if (ret)
1325 return ret;
1326
1327 if (options) {
1328 uart_parse_options(options, &baud, &parity, &bits, &flow);
1329 } else {
1330 if ((baud = uart_baudrate()) == -1)
1331 baud = 9600;
1332 }
1333
1334 if (IS_SMC(pinfo)) {
1335 out_be16(&pinfo->smcup->smc_brkcr, 0);
1336 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1337 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1338 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1339 } else {
1340 out_be16(&pinfo->sccup->scc_brkcr, 0);
1341 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1342 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1343 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1344 }
1345
1346 ret = cpm_uart_allocbuf(pinfo, 1);
1347
1348 if (ret)
1349 return ret;
1350
1351 cpm_uart_initbd(pinfo);
1352
1353 if (IS_SMC(pinfo))
1354 cpm_uart_init_smc(pinfo);
1355 else
1356 cpm_uart_init_scc(pinfo);
1357
1358 uart_set_options(port, co, baud, parity, bits, flow);
1359 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1360
1361 return 0;
1362 }
1363
1364 static struct uart_driver cpm_reg;
1365 static struct console cpm_scc_uart_console = {
1366 .name = "ttyCPM",
1367 .write = cpm_uart_console_write,
1368 .device = uart_console_device,
1369 .setup = cpm_uart_console_setup,
1370 .flags = CON_PRINTBUFFER,
1371 .index = -1,
1372 .data = &cpm_reg,
1373 };
1374
cpm_uart_console_init(void)1375 static int __init cpm_uart_console_init(void)
1376 {
1377 cpm_muram_init();
1378 register_console(&cpm_scc_uart_console);
1379 return 0;
1380 }
1381
1382 console_initcall(cpm_uart_console_init);
1383
1384 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1385 #else
1386 #define CPM_UART_CONSOLE NULL
1387 #endif
1388
1389 static struct uart_driver cpm_reg = {
1390 .owner = THIS_MODULE,
1391 .driver_name = "ttyCPM",
1392 .dev_name = "ttyCPM",
1393 .major = SERIAL_CPM_MAJOR,
1394 .minor = SERIAL_CPM_MINOR,
1395 .cons = CPM_UART_CONSOLE,
1396 .nr = UART_NR,
1397 };
1398
1399 static int probe_index;
1400
cpm_uart_probe(struct platform_device * ofdev)1401 static int cpm_uart_probe(struct platform_device *ofdev)
1402 {
1403 int index = probe_index++;
1404 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1405 int ret;
1406
1407 pinfo->port.line = index;
1408
1409 if (index >= UART_NR)
1410 return -ENODEV;
1411
1412 platform_set_drvdata(ofdev, pinfo);
1413
1414 /* initialize the device pointer for the port */
1415 pinfo->port.dev = &ofdev->dev;
1416
1417 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1418 if (ret)
1419 return ret;
1420
1421 return uart_add_one_port(&cpm_reg, &pinfo->port);
1422 }
1423
cpm_uart_remove(struct platform_device * ofdev)1424 static int cpm_uart_remove(struct platform_device *ofdev)
1425 {
1426 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1427 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1428 }
1429
1430 static const struct of_device_id cpm_uart_match[] = {
1431 {
1432 .compatible = "fsl,cpm1-smc-uart",
1433 },
1434 {
1435 .compatible = "fsl,cpm1-scc-uart",
1436 },
1437 {
1438 .compatible = "fsl,cpm2-smc-uart",
1439 },
1440 {
1441 .compatible = "fsl,cpm2-scc-uart",
1442 },
1443 {}
1444 };
1445 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1446
1447 static struct platform_driver cpm_uart_driver = {
1448 .driver = {
1449 .name = "cpm_uart",
1450 .of_match_table = cpm_uart_match,
1451 },
1452 .probe = cpm_uart_probe,
1453 .remove = cpm_uart_remove,
1454 };
1455
cpm_uart_init(void)1456 static int __init cpm_uart_init(void)
1457 {
1458 int ret = uart_register_driver(&cpm_reg);
1459 if (ret)
1460 return ret;
1461
1462 ret = platform_driver_register(&cpm_uart_driver);
1463 if (ret)
1464 uart_unregister_driver(&cpm_reg);
1465
1466 return ret;
1467 }
1468
cpm_uart_exit(void)1469 static void __exit cpm_uart_exit(void)
1470 {
1471 platform_driver_unregister(&cpm_uart_driver);
1472 uart_unregister_driver(&cpm_reg);
1473 }
1474
1475 module_init(cpm_uart_init);
1476 module_exit(cpm_uart_exit);
1477
1478 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1479 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1480 MODULE_LICENSE("GPL");
1481 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1482