1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for OmniVision OV2680 5M camera sensor. 4 * 5 * Copyright (c) 2013 Intel Corporation. All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License version 9 * 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 */ 18 19 #ifndef __OV2680_H__ 20 #define __OV2680_H__ 21 #include <linux/kernel.h> 22 #include <linux/types.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/spinlock.h> 27 #include <media/v4l2-subdev.h> 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-ctrls.h> 30 #include <linux/v4l2-mediabus.h> 31 #include <media/media-entity.h> 32 33 #include "../include/linux/atomisp_platform.h" 34 35 /* Defines for register writes and register array processing */ 36 #define I2C_MSG_LENGTH 0x2 37 #define I2C_RETRY_COUNT 5 38 39 #define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/ 40 #define OV2680_FOCAL_LENGTH_DEM 100 41 #define OV2680_F_NUMBER_DEFAULT_NUM 24 42 #define OV2680_F_NUMBER_DEM 10 43 44 #define OV2680_BIN_FACTOR_MAX 4 45 46 #define MAX_FMTS 1 47 48 /* sensor_mode_data read_mode adaptation */ 49 #define OV2680_READ_MODE_BINNING_ON 0x0400 50 #define OV2680_READ_MODE_BINNING_OFF 0x00 51 #define OV2680_INTEGRATION_TIME_MARGIN 8 52 53 #define OV2680_MAX_EXPOSURE_VALUE 0xFFF1 54 #define OV2680_MAX_GAIN_VALUE 0xFF 55 56 /* 57 * focal length bits definition: 58 * bits 31-16: numerator, bits 15-0: denominator 59 */ 60 #define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064 61 62 /* 63 * current f-number bits definition: 64 * bits 31-16: numerator, bits 15-0: denominator 65 */ 66 #define OV2680_F_NUMBER_DEFAULT 0x18000a 67 68 /* 69 * f-number range bits definition: 70 * bits 31-24: max f-number numerator 71 * bits 23-16: max f-number denominator 72 * bits 15-8: min f-number numerator 73 * bits 7-0: min f-number denominator 74 */ 75 #define OV2680_F_NUMBER_RANGE 0x180a180a 76 #define OV2680_ID 0x2680 77 78 #define OV2680_FINE_INTG_TIME_MIN 0 79 #define OV2680_FINE_INTG_TIME_MAX_MARGIN 0 80 #define OV2680_COARSE_INTG_TIME_MIN 1 81 #define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6 82 83 /* 84 * OV2680 System control registers 85 */ 86 #define OV2680_SW_SLEEP 0x0100 87 #define OV2680_SW_RESET 0x0103 88 #define OV2680_SW_STREAM 0x0100 89 90 #define OV2680_SC_CMMN_CHIP_ID_H 0x300A 91 #define OV2680_SC_CMMN_CHIP_ID_L 0x300B 92 #define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/ 93 #define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/ 94 95 #define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/ 96 97 #define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/ 98 #define OV2680_EXPOSURE_M 0x3501 99 #define OV2680_EXPOSURE_L 0x3502 100 #define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/ 101 #define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/ 102 103 #define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ 104 #define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ 105 #define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ 106 #define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ 107 #define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ 108 #define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ 109 #define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ 110 #define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ 111 #define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ 112 #define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ 113 #define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ 114 #define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ 115 #define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/ 116 #define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/ 117 #define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/ 118 #define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/ 119 #define OV2680_FRAME_OFF_NUM 0x4202 120 121 /*Flip/Mirror*/ 122 #define OV2680_FLIP_REG 0x3820 123 #define OV2680_MIRROR_REG 0x3821 124 #define OV2680_FLIP_BIT 1 125 #define OV2680_MIRROR_BIT 2 126 #define OV2680_FLIP_MIRROR_BIT_ENABLE 4 127 128 #define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/ 129 #define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/ 130 #define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/ 131 #define OV2680_MWB_GAIN_MAX 0x0fff 132 133 #define OV2680_START_STREAMING 0x01 134 #define OV2680_STOP_STREAMING 0x00 135 136 #define OV2680_INVALID_CONFIG 0xffffffff 137 138 struct regval_list { 139 u16 reg_num; 140 u8 value; 141 }; 142 143 struct ov2680_resolution { 144 u8 *desc; 145 const struct ov2680_reg *regs; 146 int res; 147 int width; 148 int height; 149 int fps; 150 int pix_clk_freq; 151 u32 skip_frames; 152 u16 pixels_per_line; 153 u16 lines_per_frame; 154 u8 bin_factor_x; 155 u8 bin_factor_y; 156 u8 bin_mode; 157 bool used; 158 }; 159 160 struct ov2680_format { 161 u8 *desc; 162 u32 pixelformat; 163 struct ov2680_reg *regs; 164 }; 165 166 /* 167 * ov2680 device structure. 168 */ 169 struct ov2680_device { 170 struct v4l2_subdev sd; 171 struct media_pad pad; 172 struct v4l2_mbus_framefmt format; 173 struct mutex input_lock; 174 struct v4l2_ctrl_handler ctrl_handler; 175 struct camera_sensor_platform_data *platform_data; 176 int vt_pix_clk_freq_mhz; 177 int fmt_idx; 178 int run_mode; 179 u8 res; 180 u8 type; 181 }; 182 183 /** 184 * struct ov2680_reg - MI sensor register format 185 * @type: type of the register 186 * @reg: 16-bit offset to register 187 * @val: 8/16/32-bit register value 188 * 189 * Define a structure for sensor register initialization values 190 */ 191 struct ov2680_reg { 192 u16 reg; 193 u32 val; /* @set value for read/mod/write, @mask */ 194 }; 195 196 #define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd) 197 198 #define OV2680_MAX_WRITE_BUF_SIZE 30 199 200 struct ov2680_write_buffer { 201 u16 addr; 202 u8 data[OV2680_MAX_WRITE_BUF_SIZE]; 203 }; 204 205 struct ov2680_write_ctrl { 206 int index; 207 struct ov2680_write_buffer buffer; 208 }; 209 210 static struct ov2680_reg const ov2680_global_setting[] = { 211 {0x0103, 0x01}, 212 {0x3002, 0x00}, 213 {0x3016, 0x1c}, 214 {0x3018, 0x44}, 215 {0x3020, 0x00}, 216 {0x3080, 0x02}, 217 {0x3082, 0x45}, 218 {0x3084, 0x09}, 219 {0x3085, 0x04}, 220 {0x3503, 0x03}, 221 {0x350b, 0x36}, 222 {0x3600, 0xb4}, 223 {0x3603, 0x39}, 224 {0x3604, 0x24}, 225 {0x3605, 0x00}, 226 {0x3620, 0x26}, 227 {0x3621, 0x37}, 228 {0x3622, 0x04}, 229 {0x3628, 0x00}, 230 {0x3705, 0x3c}, 231 {0x370c, 0x50}, 232 {0x370d, 0xc0}, 233 {0x3718, 0x88}, 234 {0x3720, 0x00}, 235 {0x3721, 0x00}, 236 {0x3722, 0x00}, 237 {0x3723, 0x00}, 238 {0x3738, 0x00}, 239 {0x3717, 0x58}, 240 {0x3781, 0x80}, 241 {0x3789, 0x60}, 242 {0x3800, 0x00}, 243 {0x3819, 0x04}, 244 {0x4000, 0x81}, 245 {0x4001, 0x40}, 246 {0x4602, 0x02}, 247 {0x481f, 0x36}, 248 {0x4825, 0x36}, 249 {0x4837, 0x18}, 250 {0x5002, 0x30}, 251 {0x5004, 0x04},//manual awb 1x 252 {0x5005, 0x00}, 253 {0x5006, 0x04}, 254 {0x5007, 0x00}, 255 {0x5008, 0x04}, 256 {0x5009, 0x00}, 257 {0x5080, 0x00}, 258 {0x3701, 0x64}, //add on 14/05/13 259 {0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13 260 {0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 261 {0x5781, 0x0f}, 262 {0x5782, 0x04}, 263 {0x5783, 0x02}, 264 {0x5784, 0x01}, 265 {0x5785, 0x01}, 266 {0x5786, 0x00}, 267 {0x5787, 0x04}, 268 {0x5788, 0x02}, 269 {0x5789, 0x00}, 270 {0x578a, 0x01}, 271 {0x578b, 0x02}, 272 {0x578c, 0x03}, 273 {0x578d, 0x03}, 274 {0x578e, 0x08}, 275 {0x578f, 0x0c}, 276 {0x5790, 0x08}, 277 {0x5791, 0x04}, 278 {0x5792, 0x00}, 279 {0x5793, 0x00}, 280 {0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 281 {0x0100, 0x00}, //stream off 282 283 {} 284 }; 285 286 #if 0 /* None of the definitions below are used currently */ 287 /* 288 * 176x144 30fps VBlanking 1lane 10Bit (binning) 289 */ 290 static struct ov2680_reg const ov2680_QCIF_30fps[] = { 291 {0x3086, 0x01}, 292 {0x3501, 0x24}, 293 {0x3502, 0x40}, 294 {0x370a, 0x23}, 295 {0x3801, 0xa0}, 296 {0x3802, 0x00}, 297 {0x3803, 0x78}, 298 {0x3804, 0x05}, 299 {0x3805, 0xaf}, 300 {0x3806, 0x04}, 301 {0x3807, 0x47}, 302 {0x3808, 0x00}, 303 {0x3809, 0xC0}, 304 {0x380a, 0x00}, 305 {0x380b, 0xa0}, 306 {0x380c, 0x06}, 307 {0x380d, 0xb0}, 308 {0x380e, 0x02}, 309 {0x380f, 0x84}, 310 {0x3810, 0x00}, 311 {0x3811, 0x04}, 312 {0x3812, 0x00}, 313 {0x3813, 0x04}, 314 {0x3814, 0x31}, 315 {0x3815, 0x31}, 316 {0x4000, 0x81}, 317 {0x4001, 0x40}, 318 {0x4008, 0x00}, 319 {0x4009, 0x03}, 320 {0x5081, 0x41}, 321 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 322 {0x5704, 0x10}, 323 {0x5705, 0xa0}, 324 {0x5706, 0x0c}, 325 {0x5707, 0x78}, 326 {0x3820, 0xc2}, 327 {0x3821, 0x01}, 328 // {0x5090, 0x0c}, 329 {} 330 }; 331 332 /* 333 * 352x288 30fps VBlanking 1lane 10Bit (binning) 334 */ 335 static struct ov2680_reg const ov2680_CIF_30fps[] = { 336 {0x3086, 0x01}, 337 {0x3501, 0x24}, 338 {0x3502, 0x40}, 339 {0x370a, 0x23}, 340 {0x3801, 0xa0}, 341 {0x3802, 0x00}, 342 {0x3803, 0x78}, 343 {0x3804, 0x03}, 344 {0x3805, 0x8f}, 345 {0x3806, 0x02}, 346 {0x3807, 0xe7}, 347 {0x3808, 0x01}, 348 {0x3809, 0x70}, 349 {0x380a, 0x01}, 350 {0x380b, 0x30}, 351 {0x380c, 0x06}, 352 {0x380d, 0xb0}, 353 {0x380e, 0x02}, 354 {0x380f, 0x84}, 355 {0x3810, 0x00}, 356 {0x3811, 0x04}, 357 {0x3812, 0x00}, 358 {0x3813, 0x04}, 359 {0x3814, 0x31}, 360 {0x3815, 0x31}, 361 {0x4008, 0x00}, 362 {0x4009, 0x03}, 363 {0x5081, 0x41}, 364 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 365 {0x5704, 0x10}, 366 {0x5705, 0xa0}, 367 {0x5706, 0x0c}, 368 {0x5707, 0x78}, 369 {0x3820, 0xc2}, 370 {0x3821, 0x01}, 371 // {0x5090, 0x0c}, 372 {} 373 }; 374 375 /* 376 * 336x256 30fps VBlanking 1lane 10Bit (binning) 377 */ 378 static struct ov2680_reg const ov2680_QVGA_30fps[] = { 379 {0x3086, 0x01}, 380 {0x3501, 0x24}, 381 {0x3502, 0x40}, 382 {0x370a, 0x23}, 383 {0x3801, 0xa0}, 384 {0x3802, 0x00}, 385 {0x3803, 0x78}, 386 {0x3804, 0x03}, 387 {0x3805, 0x4f}, 388 {0x3806, 0x02}, 389 {0x3807, 0x87}, 390 {0x3808, 0x01}, 391 {0x3809, 0x50}, 392 {0x380a, 0x01}, 393 {0x380b, 0x00}, 394 {0x380c, 0x06}, 395 {0x380d, 0xb0}, 396 {0x380e, 0x02}, 397 {0x380f, 0x84}, 398 {0x3810, 0x00}, 399 {0x3811, 0x04}, 400 {0x3812, 0x00}, 401 {0x3813, 0x04}, 402 {0x3814, 0x31}, 403 {0x3815, 0x31}, 404 {0x4008, 0x00}, 405 {0x4009, 0x03}, 406 {0x5081, 0x41}, 407 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 408 {0x5704, 0x10}, 409 {0x5705, 0xa0}, 410 {0x5706, 0x0c}, 411 {0x5707, 0x78}, 412 {0x3820, 0xc2}, 413 {0x3821, 0x01}, 414 // {0x5090, 0x0c}, 415 {} 416 }; 417 418 /* 419 * 656x496 30fps VBlanking 1lane 10Bit (binning) 420 */ 421 static struct ov2680_reg const ov2680_656x496_30fps[] = { 422 {0x3086, 0x01}, 423 {0x3501, 0x24}, 424 {0x3502, 0x40}, 425 {0x370a, 0x23}, 426 {0x3801, 0xa0}, 427 {0x3802, 0x00}, 428 {0x3803, 0x78}, 429 {0x3804, 0x05}, 430 {0x3805, 0xcf}, 431 {0x3806, 0x04}, 432 {0x3807, 0x67}, 433 {0x3808, 0x02}, 434 {0x3809, 0x90}, 435 {0x380a, 0x01}, 436 {0x380b, 0xf0}, 437 {0x380c, 0x06}, 438 {0x380d, 0xb0}, 439 {0x380e, 0x02}, 440 {0x380f, 0x84}, 441 {0x3810, 0x00}, 442 {0x3811, 0x04}, 443 {0x3812, 0x00}, 444 {0x3813, 0x04}, 445 {0x3814, 0x31}, 446 {0x3815, 0x31}, 447 {0x4008, 0x00}, 448 {0x4009, 0x03}, 449 {0x5081, 0x41}, 450 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 451 {0x5704, 0x10}, 452 {0x5705, 0xa0}, 453 {0x5706, 0x0c}, 454 {0x5707, 0x78}, 455 {0x3820, 0xc2}, 456 {0x3821, 0x01}, 457 // {0x5090, 0x0c}, 458 {} 459 }; 460 461 /* 462 * 800x600 30fps VBlanking 1lane 10Bit (binning) 463 */ 464 static struct ov2680_reg const ov2680_720x592_30fps[] = { 465 {0x3086, 0x01}, 466 {0x3501, 0x26}, 467 {0x3502, 0x40}, 468 {0x370a, 0x23}, 469 {0x3801, 0x00}, // X_ADDR_START; 470 {0x3802, 0x00}, 471 {0x3803, 0x00}, // Y_ADDR_START; 472 {0x3804, 0x05}, 473 {0x3805, 0xaf}, // X_ADDR_END; 474 {0x3806, 0x04}, 475 {0x3807, 0xaf}, // Y_ADDR_END; 476 {0x3808, 0x02}, 477 {0x3809, 0xd0}, // X_OUTPUT_SIZE; 478 {0x380a, 0x02}, 479 {0x380b, 0x50}, // Y_OUTPUT_SIZE; 480 {0x380c, 0x06}, 481 {0x380d, 0xac}, // HTS; 482 {0x380e, 0x02}, 483 {0x380f, 0x84}, // VTS; 484 {0x3810, 0x00}, 485 {0x3811, 0x00}, 486 {0x3812, 0x00}, 487 {0x3813, 0x00}, 488 {0x3814, 0x31}, 489 {0x3815, 0x31}, 490 {0x4008, 0x00}, 491 {0x4009, 0x03}, 492 {0x5708, 0x00}, 493 {0x5704, 0x02}, 494 {0x5705, 0xd0}, // X_WIN; 495 {0x5706, 0x02}, 496 {0x5707, 0x50}, // Y_WIN; 497 {0x3820, 0xc2}, // FLIP_FORMAT; 498 {0x3821, 0x01}, // MIRROR_FORMAT; 499 {0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C; 500 // BIT[3]: Mirror order, BG or GB; 501 // BIT[2]: Flip order, BR or RB; 502 {0x5081, 0x41}, 503 {} 504 }; 505 506 /* 507 * 800x600 30fps VBlanking 1lane 10Bit (binning) 508 */ 509 static struct ov2680_reg const ov2680_800x600_30fps[] = { 510 {0x3086, 0x01}, 511 {0x3501, 0x26}, 512 {0x3502, 0x40}, 513 {0x370a, 0x23}, 514 {0x3801, 0x00}, 515 {0x3802, 0x00}, 516 {0x3803, 0x00}, 517 {0x3804, 0x06}, 518 {0x3805, 0x4f}, 519 {0x3806, 0x04}, 520 {0x3807, 0xbf}, 521 {0x3808, 0x03}, 522 {0x3809, 0x20}, 523 {0x380a, 0x02}, 524 {0x380b, 0x58}, 525 {0x380c, 0x06}, 526 {0x380d, 0xac}, 527 {0x380e, 0x02}, 528 {0x380f, 0x84}, 529 {0x3810, 0x00}, 530 {0x3811, 0x00}, 531 {0x3812, 0x00}, 532 {0x3813, 0x00}, 533 {0x3814, 0x31}, 534 {0x3815, 0x31}, 535 {0x5708, 0x00}, 536 {0x5704, 0x03}, 537 {0x5705, 0x20}, 538 {0x5706, 0x02}, 539 {0x5707, 0x58}, 540 {0x3820, 0xc2}, 541 {0x3821, 0x01}, 542 {0x5090, 0x00}, 543 {0x4008, 0x00}, 544 {0x4009, 0x03}, 545 {0x5081, 0x41}, 546 {} 547 }; 548 549 /* 550 * 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling) 551 */ 552 static struct ov2680_reg const ov2680_720p_30fps[] = { 553 {0x3086, 0x00}, 554 {0x3501, 0x48}, 555 {0x3502, 0xe0}, 556 {0x370a, 0x21}, 557 {0x3801, 0xa0}, 558 {0x3802, 0x00}, 559 {0x3803, 0xf2}, 560 {0x3804, 0x05}, 561 {0x3805, 0xbf}, 562 {0x3806, 0x03}, 563 {0x3807, 0xdd}, 564 {0x3808, 0x05}, 565 {0x3809, 0x10}, 566 {0x380a, 0x02}, 567 {0x380b, 0xe0}, 568 {0x380c, 0x06}, 569 {0x380d, 0xa8}, 570 {0x380e, 0x05}, 571 {0x380f, 0x0e}, 572 {0x3810, 0x00}, 573 {0x3811, 0x08}, 574 {0x3812, 0x00}, 575 {0x3813, 0x06}, 576 {0x3814, 0x11}, 577 {0x3815, 0x11}, 578 {0x4008, 0x02}, 579 {0x4009, 0x09}, 580 {0x5081, 0x41}, 581 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 582 {0x5704, 0x10}, 583 {0x5705, 0xa0}, 584 {0x5706, 0x0c}, 585 {0x5707, 0x78}, 586 {0x3820, 0xc0}, 587 {0x3821, 0x00}, 588 // {0x5090, 0x0c}, 589 {} 590 }; 591 592 /* 593 * 1296x976 30fps VBlanking 1lane 10Bit(no-scaling) 594 */ 595 static struct ov2680_reg const ov2680_1296x976_30fps[] = { 596 {0x3086, 0x00}, 597 {0x3501, 0x48}, 598 {0x3502, 0xe0}, 599 {0x370a, 0x21}, 600 {0x3801, 0xa0}, 601 {0x3802, 0x00}, 602 {0x3803, 0x78}, 603 {0x3804, 0x05}, 604 {0x3805, 0xbf}, 605 {0x3806, 0x04}, 606 {0x3807, 0x57}, 607 {0x3808, 0x05}, 608 {0x3809, 0x10}, 609 {0x380a, 0x03}, 610 {0x380b, 0xd0}, 611 {0x380c, 0x06}, 612 {0x380d, 0xa8}, 613 {0x380e, 0x05}, 614 {0x380f, 0x0e}, 615 {0x3810, 0x00}, 616 {0x3811, 0x08}, 617 {0x3812, 0x00}, 618 {0x3813, 0x08}, 619 {0x3814, 0x11}, 620 {0x3815, 0x11}, 621 {0x4008, 0x02}, 622 {0x4009, 0x09}, 623 {0x5081, 0x41}, 624 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 625 {0x5704, 0x10}, 626 {0x5705, 0xa0}, 627 {0x5706, 0x0c}, 628 {0x5707, 0x78}, 629 {0x3820, 0xc0}, 630 {0x3821, 0x00}, //miror/flip 631 // {0x5090, 0x0c}, 632 {} 633 }; 634 635 /* 636 * 1456*1096 30fps VBlanking 1lane 10bit(no-scaling) 637 */ 638 static struct ov2680_reg const ov2680_1456x1096_30fps[] = { 639 {0x3086, 0x00}, 640 {0x3501, 0x48}, 641 {0x3502, 0xe0}, 642 {0x370a, 0x21}, 643 {0x3801, 0x90}, 644 {0x3802, 0x00}, 645 {0x3803, 0x78}, 646 {0x3804, 0x06}, 647 {0x3805, 0x4f}, 648 {0x3806, 0x04}, 649 {0x3807, 0xC0}, 650 {0x3808, 0x05}, 651 {0x3809, 0xb0}, 652 {0x380a, 0x04}, 653 {0x380b, 0x48}, 654 {0x380c, 0x06}, 655 {0x380d, 0xa8}, 656 {0x380e, 0x05}, 657 {0x380f, 0x0e}, 658 {0x3810, 0x00}, 659 {0x3811, 0x08}, 660 {0x3812, 0x00}, 661 {0x3813, 0x00}, 662 {0x3814, 0x11}, 663 {0x3815, 0x11}, 664 {0x4008, 0x02}, 665 {0x4009, 0x09}, 666 {0x5081, 0x41}, 667 {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 668 {0x5704, 0x10}, 669 {0x5705, 0xa0}, 670 {0x5706, 0x0c}, 671 {0x5707, 0x78}, 672 {0x3820, 0xc0}, 673 {0x3821, 0x00}, 674 // {0x5090, 0x0c}, 675 {} 676 }; 677 #endif 678 679 /* 680 *1616x916 30fps VBlanking 1lane 10bit 681 */ 682 683 static struct ov2680_reg const ov2680_1616x916_30fps[] = { 684 {0x3086, 0x00}, 685 {0x3501, 0x48}, 686 {0x3502, 0xe0}, 687 {0x370a, 0x21}, 688 {0x3801, 0x00}, 689 {0x3802, 0x00}, 690 {0x3803, 0x96}, 691 {0x3804, 0x06}, 692 {0x3805, 0x4f}, 693 {0x3806, 0x04}, 694 {0x3807, 0x39}, 695 {0x3808, 0x06}, 696 {0x3809, 0x50}, 697 {0x380a, 0x03}, 698 {0x380b, 0x94}, 699 {0x380c, 0x06}, 700 {0x380d, 0xa8}, 701 {0x380e, 0x05}, 702 {0x380f, 0x0e}, 703 {0x3810, 0x00}, 704 {0x3811, 0x00}, 705 {0x3812, 0x00}, 706 {0x3813, 0x08}, 707 {0x3814, 0x11}, 708 {0x3815, 0x11}, 709 {0x4008, 0x02}, 710 {0x4009, 0x09}, 711 {0x5081, 0x41}, 712 {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 713 {0x5704, 0x06}, 714 {0x5705, 0x50}, 715 {0x5706, 0x03}, 716 {0x5707, 0x94}, 717 {0x3820, 0xc0}, 718 {0x3821, 0x00}, 719 // {0x5090, 0x0C}, 720 {} 721 }; 722 723 /* 724 * 1612x1212 30fps VBlanking 1lane 10Bit 725 */ 726 #if 0 727 static struct ov2680_reg const ov2680_1616x1082_30fps[] = { 728 {0x3086, 0x00}, 729 {0x3501, 0x48}, 730 {0x3502, 0xe0}, 731 {0x370a, 0x21}, 732 {0x3801, 0x00}, 733 {0x3802, 0x00}, 734 {0x3803, 0x86}, 735 {0x3804, 0x06}, 736 {0x3805, 0x4f}, 737 {0x3806, 0x04}, 738 {0x3807, 0xbf}, 739 {0x3808, 0x06}, 740 {0x3809, 0x50}, 741 {0x380a, 0x04}, 742 {0x380b, 0x3a}, 743 {0x380c, 0x06}, 744 {0x380d, 0xa8}, 745 {0x380e, 0x05}, 746 {0x380f, 0x0e}, 747 {0x3810, 0x00}, 748 {0x3811, 0x00}, 749 {0x3812, 0x00}, 750 {0x3813, 0x00}, 751 {0x3814, 0x11}, 752 {0x3815, 0x11}, 753 {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 754 {0x5704, 0x06}, 755 {0x5705, 0x50}, 756 {0x5706, 0x04}, 757 {0x5707, 0x3a}, 758 {0x3820, 0xc0}, 759 {0x3821, 0x00}, 760 // {0x5090, 0x0C}, 761 {0x4008, 0x02}, 762 {0x4009, 0x09}, 763 {0x5081, 0x41}, 764 {} 765 }; 766 #endif 767 /* 768 * 1616x1216 30fps VBlanking 1lane 10Bit 769 */ 770 static struct ov2680_reg const ov2680_1616x1216_30fps[] = { 771 {0x3086, 0x00}, 772 {0x3501, 0x48}, 773 {0x3502, 0xe0}, 774 {0x370a, 0x21}, 775 {0x3801, 0x00}, 776 {0x3802, 0x00}, 777 {0x3803, 0x00}, 778 {0x3804, 0x06}, 779 {0x3805, 0x4f}, 780 {0x3806, 0x04}, 781 {0x3807, 0xbf}, 782 {0x3808, 0x06}, 783 {0x3809, 0x50},//50},//4line for mirror and flip 784 {0x380a, 0x04}, 785 {0x380b, 0xc0},//c0}, 786 {0x380c, 0x06}, 787 {0x380d, 0xa8}, 788 {0x380e, 0x05}, 789 {0x380f, 0x0e}, 790 {0x3810, 0x00}, 791 {0x3811, 0x00}, 792 {0x3812, 0x00}, 793 {0x3813, 0x00}, 794 {0x3814, 0x11}, 795 {0x3815, 0x11}, 796 {0x4008, 0x00}, 797 {0x4009, 0x0b}, 798 {0x5081, 0x01}, 799 {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 800 {0x5704, 0x06}, 801 {0x5705, 0x50}, 802 {0x5706, 0x04}, 803 {0x5707, 0xcc}, 804 {0x3820, 0xc0}, 805 {0x3821, 0x00}, 806 // {0x5090, 0x0C}, 807 {} 808 }; 809 810 static struct ov2680_resolution ov2680_res_preview[] = { 811 { 812 .desc = "ov2680_1616x1216_30fps", 813 .width = 1616, 814 .height = 1216, 815 .pix_clk_freq = 66, 816 .fps = 30, 817 .used = 0, 818 .pixels_per_line = 1698,//1704, 819 .lines_per_frame = 1294, 820 .bin_factor_x = 0, 821 .bin_factor_y = 0, 822 .bin_mode = 0, 823 .skip_frames = 3, 824 .regs = ov2680_1616x1216_30fps, 825 }, 826 { 827 .desc = "ov2680_1616x916_30fps", 828 .width = 1616, 829 .height = 916, 830 .fps = 30, 831 .pix_clk_freq = 66, 832 .used = 0, 833 .pixels_per_line = 1698,//1704, 834 .lines_per_frame = 1294, 835 .bin_factor_x = 0, 836 .bin_factor_y = 0, 837 .bin_mode = 0, 838 .skip_frames = 3, 839 .regs = ov2680_1616x916_30fps, 840 }, 841 }; 842 843 #define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview)) 844 845 static struct ov2680_resolution *ov2680_res = ov2680_res_preview; 846 static unsigned long N_RES = N_RES_PREVIEW; 847 848 #endif 849