1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77950 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 */
7
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10
11 #include "core.h"
12 #include "sh_pfc.h"
13
14 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
15
16 #define CPU_ALL_GP(fn, sfx) \
17 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29
30 #define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
32 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75
76 /*
77 * F_() : just information
78 * FM() : macro for FN_xxx / xxx_MARK
79 */
80
81 /* GPSR0 */
82 #define GPSR0_15 F_(D15, IP7_11_8)
83 #define GPSR0_14 F_(D14, IP7_7_4)
84 #define GPSR0_13 F_(D13, IP7_3_0)
85 #define GPSR0_12 F_(D12, IP6_31_28)
86 #define GPSR0_11 F_(D11, IP6_27_24)
87 #define GPSR0_10 F_(D10, IP6_23_20)
88 #define GPSR0_9 F_(D9, IP6_19_16)
89 #define GPSR0_8 F_(D8, IP6_15_12)
90 #define GPSR0_7 F_(D7, IP6_11_8)
91 #define GPSR0_6 F_(D6, IP6_7_4)
92 #define GPSR0_5 F_(D5, IP6_3_0)
93 #define GPSR0_4 F_(D4, IP5_31_28)
94 #define GPSR0_3 F_(D3, IP5_27_24)
95 #define GPSR0_2 F_(D2, IP5_23_20)
96 #define GPSR0_1 F_(D1, IP5_19_16)
97 #define GPSR0_0 F_(D0, IP5_15_12)
98
99 /* GPSR1 */
100 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
101 #define GPSR1_26 F_(WE1_N, IP5_7_4)
102 #define GPSR1_25 F_(WE0_N, IP5_3_0)
103 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
104 #define GPSR1_23 F_(RD_N, IP4_27_24)
105 #define GPSR1_22 F_(BS_N, IP4_23_20)
106 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
107 #define GPSR1_20 F_(CS0_N, IP4_15_12)
108 #define GPSR1_19 F_(A19, IP4_11_8)
109 #define GPSR1_18 F_(A18, IP4_7_4)
110 #define GPSR1_17 F_(A17, IP4_3_0)
111 #define GPSR1_16 F_(A16, IP3_31_28)
112 #define GPSR1_15 F_(A15, IP3_27_24)
113 #define GPSR1_14 F_(A14, IP3_23_20)
114 #define GPSR1_13 F_(A13, IP3_19_16)
115 #define GPSR1_12 F_(A12, IP3_15_12)
116 #define GPSR1_11 F_(A11, IP3_11_8)
117 #define GPSR1_10 F_(A10, IP3_7_4)
118 #define GPSR1_9 F_(A9, IP3_3_0)
119 #define GPSR1_8 F_(A8, IP2_31_28)
120 #define GPSR1_7 F_(A7, IP2_27_24)
121 #define GPSR1_6 F_(A6, IP2_23_20)
122 #define GPSR1_5 F_(A5, IP2_19_16)
123 #define GPSR1_4 F_(A4, IP2_15_12)
124 #define GPSR1_3 F_(A3, IP2_11_8)
125 #define GPSR1_2 F_(A2, IP2_7_4)
126 #define GPSR1_1 F_(A1, IP2_3_0)
127 #define GPSR1_0 F_(A0, IP1_31_28)
128
129 /* GPSR2 */
130 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
131 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
132 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
133 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
134 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
135 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
136 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
137 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
138 #define GPSR2_6 F_(PWM0, IP1_19_16)
139 #define GPSR2_5 F_(IRQ5, IP1_15_12)
140 #define GPSR2_4 F_(IRQ4, IP1_11_8)
141 #define GPSR2_3 F_(IRQ3, IP1_7_4)
142 #define GPSR2_2 F_(IRQ2, IP1_3_0)
143 #define GPSR2_1 F_(IRQ1, IP0_31_28)
144 #define GPSR2_0 F_(IRQ0, IP0_27_24)
145
146 /* GPSR3 */
147 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
148 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
149 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
150 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
151 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
152 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
153 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
154 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
155 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
156 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
157 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
158 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
159 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
160 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
161 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
162 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
163
164 /* GPSR4 */
165 #define GPSR4_17 FM(SD3_DS)
166 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
167 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
168 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
169 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
170 #define GPSR4_12 FM(SD3_DAT3)
171 #define GPSR4_11 FM(SD3_DAT2)
172 #define GPSR4_10 FM(SD3_DAT1)
173 #define GPSR4_9 FM(SD3_DAT0)
174 #define GPSR4_8 FM(SD3_CMD)
175 #define GPSR4_7 FM(SD3_CLK)
176 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
177 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
178 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
179 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
180 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
181 #define GPSR4_1 FM(SD2_CMD)
182 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
183
184 /* GPSR5 */
185 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
186 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
187 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
188 #define GPSR5_22 FM(MSIOF0_RXD)
189 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
190 #define GPSR5_20 FM(MSIOF0_TXD)
191 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
192 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
193 #define GPSR5_17 FM(MSIOF0_SCK)
194 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
195 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
196 #define GPSR5_14 F_(HTX0, IP12_19_16)
197 #define GPSR5_13 F_(HRX0, IP12_15_12)
198 #define GPSR5_12 F_(HSCK0, IP12_11_8)
199 #define GPSR5_11 F_(RX2_A, IP12_7_4)
200 #define GPSR5_10 F_(TX2_A, IP12_3_0)
201 #define GPSR5_9 F_(SCK2, IP11_31_28)
202 #define GPSR5_8 F_(RTS1_N, IP11_27_24)
203 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
204 #define GPSR5_6 F_(TX1_A, IP11_19_16)
205 #define GPSR5_5 F_(RX1_A, IP11_15_12)
206 #define GPSR5_4 F_(RTS0_N, IP11_11_8)
207 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
208 #define GPSR5_2 F_(TX0, IP11_3_0)
209 #define GPSR5_1 F_(RX0, IP10_31_28)
210 #define GPSR5_0 F_(SCK0, IP10_27_24)
211
212 /* GPSR6 */
213 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
214 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
215 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
216 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
217 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
218 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
219 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
220 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
221 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
222 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
223 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
224 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
225 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
226 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
227 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
228 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
229 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
230 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
231 #define GPSR6_13 FM(SSI_SDATA5)
232 #define GPSR6_12 FM(SSI_WS5)
233 #define GPSR6_11 FM(SSI_SCK5)
234 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
235 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
236 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
237 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
238 #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
239 #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
240 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
241 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
242 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
243 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
244 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
245
246 /* GPSR7 */
247 #define GPSR7_3 FM(GP7_03)
248 #define GPSR7_2 FM(GP7_02)
249 #define GPSR7_1 FM(AVS2)
250 #define GPSR7_0 FM(AVS1)
251
252
253 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
254 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273
274 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
275 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361
362 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
363 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398
399 #define PINMUX_GPSR \
400 \
401 GPSR6_31 \
402 GPSR6_30 \
403 GPSR6_29 \
404 GPSR6_28 \
405 GPSR1_27 GPSR6_27 \
406 GPSR1_26 GPSR6_26 \
407 GPSR1_25 GPSR5_25 GPSR6_25 \
408 GPSR1_24 GPSR5_24 GPSR6_24 \
409 GPSR1_23 GPSR5_23 GPSR6_23 \
410 GPSR1_22 GPSR5_22 GPSR6_22 \
411 GPSR1_21 GPSR5_21 GPSR6_21 \
412 GPSR1_20 GPSR5_20 GPSR6_20 \
413 GPSR1_19 GPSR5_19 GPSR6_19 \
414 GPSR1_18 GPSR5_18 GPSR6_18 \
415 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
416 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
417 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
418 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
419 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
420 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
421 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
422 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
423 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
424 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
425 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
426 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
427 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
428 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
429 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
430 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
431 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
432 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
433
434 #define PINMUX_IPSR \
435 \
436 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
437 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
438 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
439 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
440 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
441 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
442 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
443 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
444 \
445 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
446 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
447 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
448 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
449 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
450 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
451 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
452 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
453 \
454 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
455 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
456 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
457 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
458 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
459 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
460 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
461 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
462 \
463 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
464 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
465 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
466 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
467 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
468 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
469 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
470 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
471 \
472 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
473 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
474 FM(IP16_11_8) IP16_11_8 \
475 FM(IP16_15_12) IP16_15_12 \
476 FM(IP16_19_16) IP16_19_16 \
477 FM(IP16_23_20) IP16_23_20 \
478 FM(IP16_27_24) IP16_27_24 \
479 FM(IP16_31_28) IP16_31_28
480
481 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
482 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
483 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
484 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
485 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
486 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
487 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
488 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
489 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
490 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
491 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
492 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
493 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
494 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
495 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
496 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
497 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
498 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
499 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
500 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
501 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
502 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
503
504 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
505 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
506 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
507 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
508 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
509 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
510 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
511 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
512 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
513 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
514 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
515 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
516 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
517 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
518 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
519 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
520 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
521 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
522 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
523 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
524 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
525 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
526 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
527
528 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
529 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
530 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
531 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
532 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
533
534 #define PINMUX_MOD_SELS\
535 \
536 MOD_SEL1_31_30 MOD_SEL2_31 \
537 MOD_SEL0_30_29 MOD_SEL2_30 \
538 MOD_SEL1_29_28_27 MOD_SEL2_29 \
539 MOD_SEL0_28_27 \
540 \
541 MOD_SEL0_26_25_24 MOD_SEL1_26 \
542 MOD_SEL1_25_24 \
543 \
544 MOD_SEL0_23 MOD_SEL1_23_22_21 \
545 MOD_SEL0_22 \
546 MOD_SEL0_21_20 \
547 MOD_SEL1_20 \
548 MOD_SEL0_19 MOD_SEL1_19 \
549 MOD_SEL0_18 MOD_SEL1_18_17 \
550 MOD_SEL0_17 \
551 MOD_SEL0_16_15 MOD_SEL1_16 \
552 MOD_SEL1_15_14 \
553 MOD_SEL0_14 \
554 MOD_SEL0_13 MOD_SEL1_13 \
555 MOD_SEL0_12 MOD_SEL1_12 \
556 MOD_SEL0_11 MOD_SEL1_11 \
557 MOD_SEL0_10 MOD_SEL1_10 \
558 MOD_SEL0_9 MOD_SEL1_9 \
559 MOD_SEL0_8 \
560 MOD_SEL0_7_6 \
561 MOD_SEL1_6 \
562 MOD_SEL0_5_4 MOD_SEL1_5 \
563 MOD_SEL1_4 \
564 MOD_SEL0_3 MOD_SEL1_3 \
565 MOD_SEL0_2_1 MOD_SEL1_2 \
566 MOD_SEL1_1 \
567 MOD_SEL1_0 MOD_SEL2_0
568
569 /*
570 * These pins are not able to be muxed but have other properties
571 * that can be set, such as drive-strength or pull-up/pull-down enable.
572 */
573 #define PINMUX_STATIC \
574 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
575 FM(QSPI0_IO2) FM(QSPI0_IO3) \
576 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
577 FM(QSPI1_IO2) FM(QSPI1_IO3) \
578 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
579 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
580 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
581 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
582 FM(CLKOUT) FM(PRESETOUT) \
583 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
584 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
585
586 #define PINMUX_PHYS \
587 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
588
589 enum {
590 PINMUX_RESERVED = 0,
591
592 PINMUX_DATA_BEGIN,
593 GP_ALL(DATA),
594 PINMUX_DATA_END,
595
596 #define F_(x, y)
597 #define FM(x) FN_##x,
598 PINMUX_FUNCTION_BEGIN,
599 GP_ALL(FN),
600 PINMUX_GPSR
601 PINMUX_IPSR
602 PINMUX_MOD_SELS
603 PINMUX_FUNCTION_END,
604 #undef F_
605 #undef FM
606
607 #define F_(x, y)
608 #define FM(x) x##_MARK,
609 PINMUX_MARK_BEGIN,
610 PINMUX_GPSR
611 PINMUX_IPSR
612 PINMUX_MOD_SELS
613 PINMUX_STATIC
614 PINMUX_PHYS
615 PINMUX_MARK_END,
616 #undef F_
617 #undef FM
618 };
619
620 static const u16 pinmux_data[] = {
621 PINMUX_DATA_GP_ALL(),
622
623 PINMUX_SINGLE(AVS1),
624 PINMUX_SINGLE(AVS2),
625 PINMUX_SINGLE(GP7_02),
626 PINMUX_SINGLE(GP7_03),
627 PINMUX_SINGLE(MSIOF0_RXD),
628 PINMUX_SINGLE(MSIOF0_SCK),
629 PINMUX_SINGLE(MSIOF0_TXD),
630 PINMUX_SINGLE(SD2_CMD),
631 PINMUX_SINGLE(SD3_CLK),
632 PINMUX_SINGLE(SD3_CMD),
633 PINMUX_SINGLE(SD3_DAT0),
634 PINMUX_SINGLE(SD3_DAT1),
635 PINMUX_SINGLE(SD3_DAT2),
636 PINMUX_SINGLE(SD3_DAT3),
637 PINMUX_SINGLE(SD3_DS),
638 PINMUX_SINGLE(SSI_SCK5),
639 PINMUX_SINGLE(SSI_SDATA5),
640 PINMUX_SINGLE(SSI_WS5),
641
642 /* IPSR0 */
643 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
644 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
645
646 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
647 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
648 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
649
650 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
651 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
652 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
653
654 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
655 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
656 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
657
658 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
659 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
660 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
661 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
662
663 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
664 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
665 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
666 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
667
668 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
669 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
670 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
671 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
673 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
674
675 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
676 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
677 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
678 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
680 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
681
682 /* IPSR1 */
683 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
684 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
685 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
686 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
687 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
688
689 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
690 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
691 PINMUX_IPSR_GPSR(IP1_7_4, A25),
692 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
693 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
694 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
695
696 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
697 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
698 PINMUX_IPSR_GPSR(IP1_11_8, A24),
699 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
700 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
702
703 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
704 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
705 PINMUX_IPSR_GPSR(IP1_15_12, A23),
706 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
707 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
709
710 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
711 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
712 PINMUX_IPSR_GPSR(IP1_19_16, A22),
713 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
714 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
715
716 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
717 PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
718 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
719 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
720 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
721 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
722
723 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
724 PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
725 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
726 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
727 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
728
729 PINMUX_IPSR_GPSR(IP1_31_28, A0),
730 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
731 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
733 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
734 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
735
736 /* IPSR2 */
737 PINMUX_IPSR_GPSR(IP2_3_0, A1),
738 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
739 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
740 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
741 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
742 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
743
744 PINMUX_IPSR_GPSR(IP2_7_4, A2),
745 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
746 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
747 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
748 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
749 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
750
751 PINMUX_IPSR_GPSR(IP2_11_8, A3),
752 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
753 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
754 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
755 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
756 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
757
758 PINMUX_IPSR_GPSR(IP2_15_12, A4),
759 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
760 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
761 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
762 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
763 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
764
765 PINMUX_IPSR_GPSR(IP2_19_16, A5),
766 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
767 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
768 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
769 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
770 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
771 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
772
773 PINMUX_IPSR_GPSR(IP2_23_20, A6),
774 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
775 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
776 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
777 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
778 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
779 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
780
781 PINMUX_IPSR_GPSR(IP2_27_24, A7),
782 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
783 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
784 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
785 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
786 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
787 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
788
789 PINMUX_IPSR_GPSR(IP2_31_28, A8),
790 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
791 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
792 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
793 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
794 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
795 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
796
797 /* IPSR3 */
798 PINMUX_IPSR_GPSR(IP3_3_0, A9),
799 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
800 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
801 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
802
803 PINMUX_IPSR_GPSR(IP3_7_4, A10),
804 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
806 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
807
808 PINMUX_IPSR_GPSR(IP3_11_8, A11),
809 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
810 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
811 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
812 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
813 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
814 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
815 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
816 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
817
818 PINMUX_IPSR_GPSR(IP3_15_12, A12),
819 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
820 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
821 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
822 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
823 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
824
825 PINMUX_IPSR_GPSR(IP3_19_16, A13),
826 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
827 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
828 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
829 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
830 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
831
832 PINMUX_IPSR_GPSR(IP3_23_20, A14),
833 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
834 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
835 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
836 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
837 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
838
839 PINMUX_IPSR_GPSR(IP3_27_24, A15),
840 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
841 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
842 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
843 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
844 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
845
846 PINMUX_IPSR_GPSR(IP3_31_28, A16),
847 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
848 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
849 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
850
851 /* IPSR4 */
852 PINMUX_IPSR_GPSR(IP4_3_0, A17),
853 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
854 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
855 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
856
857 PINMUX_IPSR_GPSR(IP4_7_4, A18),
858 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
859 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
860 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
861
862 PINMUX_IPSR_GPSR(IP4_11_8, A19),
863 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
864 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
865 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
866
867 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
868 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
869
870 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
871 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
872 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
873
874 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
875 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
876 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
877 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
878 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
879 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
880 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
881 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
882
883 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
884 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
885 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
886 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
887 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
888 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
889
890 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
891 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
894 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
895 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
896
897 /* IPSR5 */
898 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
899 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
900 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
901 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
902 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
903 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
904 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
905
906 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
907 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
908 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
909 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
910 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
911 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
912 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
913 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
914
915 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
916 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
917 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
918 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
919
920 PINMUX_IPSR_GPSR(IP5_15_12, D0),
921 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
923 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
924 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
925
926 PINMUX_IPSR_GPSR(IP5_19_16, D1),
927 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
928 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
929 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
930 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
931
932 PINMUX_IPSR_GPSR(IP5_23_20, D2),
933 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
934 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
935 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
936
937 PINMUX_IPSR_GPSR(IP5_27_24, D3),
938 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
939 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
940 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
941
942 PINMUX_IPSR_GPSR(IP5_31_28, D4),
943 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
944 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
945 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
946
947 /* IPSR6 */
948 PINMUX_IPSR_GPSR(IP6_3_0, D5),
949 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
950 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
951 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
952
953 PINMUX_IPSR_GPSR(IP6_7_4, D6),
954 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
955 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
956 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
957
958 PINMUX_IPSR_GPSR(IP6_11_8, D7),
959 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
960 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
961 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
962
963 PINMUX_IPSR_GPSR(IP6_15_12, D8),
964 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
965 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
966 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
967 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
968 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
969
970 PINMUX_IPSR_GPSR(IP6_19_16, D9),
971 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
972 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
973 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
974 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
975
976 PINMUX_IPSR_GPSR(IP6_23_20, D10),
977 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
978 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
979 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
980 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
981 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
982 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
983
984 PINMUX_IPSR_GPSR(IP6_27_24, D11),
985 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
986 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
987 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
988 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
989 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
990 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
991
992 PINMUX_IPSR_GPSR(IP6_31_28, D12),
993 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
994 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
995 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
996 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
997 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
998
999 /* IPSR7 */
1000 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1001 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1002 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1003 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1004 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1005 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1006
1007 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1008 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1009 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1010 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1011 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1012 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1013 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1014
1015 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1016 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1017 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1018 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1019 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1020 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1021 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1022
1023 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
1024
1025 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1026 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1027 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1028
1029 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1030 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1031 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1032
1033 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1034 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1035 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1036 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1037
1038 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1039 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1041 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1042
1043 /* IPSR8 */
1044 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1045 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1046 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1047 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1048
1049 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1050 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1053
1054 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1055 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1056 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1057
1058 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1059 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1060 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1061 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1062
1063 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1064 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1065 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1066 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1067 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1068
1069 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1070 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1071 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1072 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1073 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1074
1075 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1076 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1077 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1078 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1079 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1080
1081 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1082 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1083 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1084 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1085 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1086
1087 /* IPSR9 */
1088 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1089
1090 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1091
1092 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1093
1094 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1095
1096 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1097
1098 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1099 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1100
1101 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1102 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1103
1104 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1106
1107 /* IPSR10 */
1108 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1110
1111 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1112 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1113
1114 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1115 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1120
1121 PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
1122 PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1123 PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
1124
1125 PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
1126 PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1127 PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
1128
1129 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1133 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1138
1139 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1140 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1141 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1142 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1143 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1144
1145 /* IPSR11 */
1146 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1147 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1148 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1149 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1150 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1151
1152 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1153 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1154 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1155 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1156 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1157 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1158 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1159 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1160
1161 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
1162 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1163 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1164 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1165 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1166 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1167 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1168 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1169
1170 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1171 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1172 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1173 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1174 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1175
1176 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1177 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1178 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1179 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1180 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1181
1182 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1183 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1184 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1185 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1186 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1187 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1188 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1189
1190 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1191 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1192 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1193 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1194 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1195 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1196 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1197
1198 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1199 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1200 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1201 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1203 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1204 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1205
1206 /* IPSR12 */
1207 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1208 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1209 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1210 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1211 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1212 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1213
1214 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1215 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1216 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1217 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1218 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1219 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1220
1221 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1222 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1223 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1224 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1225 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1226 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1227 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1228
1229 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1230 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1231 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1232 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1233 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1234 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1235
1236 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1237 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1238 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1239 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1240 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1241 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1242
1243 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1244 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1245 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1246 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1247 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1248 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1249 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1250 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1251
1252 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1253 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1254 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1255 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1256 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1257 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1258 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1259
1260 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1261 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1262
1263 /* IPSR13 */
1264 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1265 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1266 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1267 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1268 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1269 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1270 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1271
1272 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1273 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1274 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1275 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1276 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1278 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1279 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1280
1281 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1282 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1283 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1284
1285 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1286 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1291 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1293
1294 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1295 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1296
1297 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1298 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1301 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1302
1303 /* IPSR14 */
1304 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1305
1306 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1307 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1308
1309 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
1310 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1311 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1312
1313 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
1314 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1315 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1317
1318 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1319 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1322 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1323 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1324 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1325
1326 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1327 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1330 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1331 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1332 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1333
1334 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1335 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1336 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1337 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1338 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1339 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1340 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1341
1342 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1343 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1344 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1345 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1346 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1347 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1348 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1349
1350 /* IPSR15 */
1351 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1352 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1353 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1354
1355 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1356 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1357 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1358
1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1360 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1361 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1362
1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1364 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1366 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1367 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1368 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1369 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1370
1371 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1372 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1373 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1374 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1375 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1376 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1377 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1378
1379 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1380 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1381 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1382 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1383 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1384 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1387
1388 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1389 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1395
1396 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1397 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1398 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1399 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1400 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1401 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1402 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1403 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1404
1405 /* IPSR16 */
1406 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1407
1408 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1409 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1410 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1411 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1412 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1413
1414 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1415 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1416 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1417 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1418 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1419 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1420
1421 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1422 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1423 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1424 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1425 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1426
1427 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1428 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1431 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1432 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1433 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1434 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1435
1436 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1437 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1438 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1440 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1441 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1443 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1444
1445 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1446 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1447 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1448 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1449 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1452 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1453 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1454
1455 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1456 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1457 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1459 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1462 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1463 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1464
1465 /* IPSR17 */
1466 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1467 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1468 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1469 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1470 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1471 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1472 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1473
1474 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1475 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1476 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1477 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1478 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1479 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1480 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1481
1482 /*
1483 * Static pins can not be muxed between different functions but
1484 * still need mark entries in the pinmux list. Add each static
1485 * pin to the list without an associated function. The sh-pfc
1486 * core will do the right thing and skip trying to mux the pin
1487 * while still applying configuration to it.
1488 */
1489 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1490 PINMUX_STATIC
1491 #undef FM
1492 };
1493
1494 /*
1495 * Pins not associated with a GPIO port.
1496 */
1497 enum {
1498 GP_ASSIGN_LAST(),
1499 NOGP_ALL(),
1500 };
1501
1502 static const struct sh_pfc_pin pinmux_pins[] = {
1503 PINMUX_GPIO_GP_ALL(),
1504 PINMUX_NOGP_ALL(),
1505 };
1506
1507 /* - AUDIO CLOCK ------------------------------------------------------------ */
1508 static const unsigned int audio_clk_a_a_pins[] = {
1509 /* CLK A */
1510 RCAR_GP_PIN(6, 22),
1511 };
1512 static const unsigned int audio_clk_a_a_mux[] = {
1513 AUDIO_CLKA_A_MARK,
1514 };
1515 static const unsigned int audio_clk_a_b_pins[] = {
1516 /* CLK A */
1517 RCAR_GP_PIN(5, 4),
1518 };
1519 static const unsigned int audio_clk_a_b_mux[] = {
1520 AUDIO_CLKA_B_MARK,
1521 };
1522 static const unsigned int audio_clk_a_c_pins[] = {
1523 /* CLK A */
1524 RCAR_GP_PIN(5, 19),
1525 };
1526 static const unsigned int audio_clk_a_c_mux[] = {
1527 AUDIO_CLKA_C_MARK,
1528 };
1529 static const unsigned int audio_clk_b_a_pins[] = {
1530 /* CLK B */
1531 RCAR_GP_PIN(5, 12),
1532 };
1533 static const unsigned int audio_clk_b_a_mux[] = {
1534 AUDIO_CLKB_A_MARK,
1535 };
1536 static const unsigned int audio_clk_b_b_pins[] = {
1537 /* CLK B */
1538 RCAR_GP_PIN(6, 23),
1539 };
1540 static const unsigned int audio_clk_b_b_mux[] = {
1541 AUDIO_CLKB_B_MARK,
1542 };
1543 static const unsigned int audio_clk_c_a_pins[] = {
1544 /* CLK C */
1545 RCAR_GP_PIN(5, 21),
1546 };
1547 static const unsigned int audio_clk_c_a_mux[] = {
1548 AUDIO_CLKC_A_MARK,
1549 };
1550 static const unsigned int audio_clk_c_b_pins[] = {
1551 /* CLK C */
1552 RCAR_GP_PIN(5, 0),
1553 };
1554 static const unsigned int audio_clk_c_b_mux[] = {
1555 AUDIO_CLKC_B_MARK,
1556 };
1557 static const unsigned int audio_clkout_a_pins[] = {
1558 /* CLKOUT */
1559 RCAR_GP_PIN(5, 18),
1560 };
1561 static const unsigned int audio_clkout_a_mux[] = {
1562 AUDIO_CLKOUT_A_MARK,
1563 };
1564 static const unsigned int audio_clkout_b_pins[] = {
1565 /* CLKOUT */
1566 RCAR_GP_PIN(6, 28),
1567 };
1568 static const unsigned int audio_clkout_b_mux[] = {
1569 AUDIO_CLKOUT_B_MARK,
1570 };
1571 static const unsigned int audio_clkout_c_pins[] = {
1572 /* CLKOUT */
1573 RCAR_GP_PIN(5, 3),
1574 };
1575 static const unsigned int audio_clkout_c_mux[] = {
1576 AUDIO_CLKOUT_C_MARK,
1577 };
1578 static const unsigned int audio_clkout_d_pins[] = {
1579 /* CLKOUT */
1580 RCAR_GP_PIN(5, 21),
1581 };
1582 static const unsigned int audio_clkout_d_mux[] = {
1583 AUDIO_CLKOUT_D_MARK,
1584 };
1585 static const unsigned int audio_clkout1_a_pins[] = {
1586 /* CLKOUT1 */
1587 RCAR_GP_PIN(5, 15),
1588 };
1589 static const unsigned int audio_clkout1_a_mux[] = {
1590 AUDIO_CLKOUT1_A_MARK,
1591 };
1592 static const unsigned int audio_clkout1_b_pins[] = {
1593 /* CLKOUT1 */
1594 RCAR_GP_PIN(6, 29),
1595 };
1596 static const unsigned int audio_clkout1_b_mux[] = {
1597 AUDIO_CLKOUT1_B_MARK,
1598 };
1599 static const unsigned int audio_clkout2_a_pins[] = {
1600 /* CLKOUT2 */
1601 RCAR_GP_PIN(5, 16),
1602 };
1603 static const unsigned int audio_clkout2_a_mux[] = {
1604 AUDIO_CLKOUT2_A_MARK,
1605 };
1606 static const unsigned int audio_clkout2_b_pins[] = {
1607 /* CLKOUT2 */
1608 RCAR_GP_PIN(6, 30),
1609 };
1610 static const unsigned int audio_clkout2_b_mux[] = {
1611 AUDIO_CLKOUT2_B_MARK,
1612 };
1613
1614 static const unsigned int audio_clkout3_a_pins[] = {
1615 /* CLKOUT3 */
1616 RCAR_GP_PIN(5, 19),
1617 };
1618 static const unsigned int audio_clkout3_a_mux[] = {
1619 AUDIO_CLKOUT3_A_MARK,
1620 };
1621 static const unsigned int audio_clkout3_b_pins[] = {
1622 /* CLKOUT3 */
1623 RCAR_GP_PIN(6, 31),
1624 };
1625 static const unsigned int audio_clkout3_b_mux[] = {
1626 AUDIO_CLKOUT3_B_MARK,
1627 };
1628
1629 /* - EtherAVB --------------------------------------------------------------- */
1630 static const unsigned int avb_link_pins[] = {
1631 /* AVB_LINK */
1632 RCAR_GP_PIN(2, 12),
1633 };
1634 static const unsigned int avb_link_mux[] = {
1635 AVB_LINK_MARK,
1636 };
1637 static const unsigned int avb_magic_pins[] = {
1638 /* AVB_MAGIC_ */
1639 RCAR_GP_PIN(2, 10),
1640 };
1641 static const unsigned int avb_magic_mux[] = {
1642 AVB_MAGIC_MARK,
1643 };
1644 static const unsigned int avb_phy_int_pins[] = {
1645 /* AVB_PHY_INT */
1646 RCAR_GP_PIN(2, 11),
1647 };
1648 static const unsigned int avb_phy_int_mux[] = {
1649 AVB_PHY_INT_MARK,
1650 };
1651 static const unsigned int avb_mdio_pins[] = {
1652 /* AVB_MDC, AVB_MDIO */
1653 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1654 };
1655 static const unsigned int avb_mdio_mux[] = {
1656 AVB_MDC_MARK, AVB_MDIO_MARK,
1657 };
1658 static const unsigned int avb_mii_pins[] = {
1659 /*
1660 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1661 * AVB_TD1, AVB_TD2, AVB_TD3,
1662 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1663 * AVB_RD1, AVB_RD2, AVB_RD3,
1664 * AVB_TXCREFCLK
1665 */
1666 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1667 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1668 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1669 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1670 PIN_AVB_TXCREFCLK,
1671
1672 };
1673 static const unsigned int avb_mii_mux[] = {
1674 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1675 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1676 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1677 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1678 AVB_TXCREFCLK_MARK,
1679 };
1680 static const unsigned int avb_avtp_pps_pins[] = {
1681 /* AVB_AVTP_PPS */
1682 RCAR_GP_PIN(2, 6),
1683 };
1684 static const unsigned int avb_avtp_pps_mux[] = {
1685 AVB_AVTP_PPS_MARK,
1686 };
1687 static const unsigned int avb_avtp_match_a_pins[] = {
1688 /* AVB_AVTP_MATCH_A */
1689 RCAR_GP_PIN(2, 13),
1690 };
1691 static const unsigned int avb_avtp_match_a_mux[] = {
1692 AVB_AVTP_MATCH_A_MARK,
1693 };
1694 static const unsigned int avb_avtp_capture_a_pins[] = {
1695 /* AVB_AVTP_CAPTURE_A */
1696 RCAR_GP_PIN(2, 14),
1697 };
1698 static const unsigned int avb_avtp_capture_a_mux[] = {
1699 AVB_AVTP_CAPTURE_A_MARK,
1700 };
1701 static const unsigned int avb_avtp_match_b_pins[] = {
1702 /* AVB_AVTP_MATCH_B */
1703 RCAR_GP_PIN(1, 8),
1704 };
1705 static const unsigned int avb_avtp_match_b_mux[] = {
1706 AVB_AVTP_MATCH_B_MARK,
1707 };
1708 static const unsigned int avb_avtp_capture_b_pins[] = {
1709 /* AVB_AVTP_CAPTURE_B */
1710 RCAR_GP_PIN(1, 11),
1711 };
1712 static const unsigned int avb_avtp_capture_b_mux[] = {
1713 AVB_AVTP_CAPTURE_B_MARK,
1714 };
1715
1716 /* - CAN ------------------------------------------------------------------ */
1717 static const unsigned int can0_data_a_pins[] = {
1718 /* TX, RX */
1719 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1720 };
1721 static const unsigned int can0_data_a_mux[] = {
1722 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1723 };
1724 static const unsigned int can0_data_b_pins[] = {
1725 /* TX, RX */
1726 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1727 };
1728 static const unsigned int can0_data_b_mux[] = {
1729 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1730 };
1731 static const unsigned int can1_data_pins[] = {
1732 /* TX, RX */
1733 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1734 };
1735 static const unsigned int can1_data_mux[] = {
1736 CAN1_TX_MARK, CAN1_RX_MARK,
1737 };
1738
1739 /* - CAN Clock -------------------------------------------------------------- */
1740 static const unsigned int can_clk_pins[] = {
1741 /* CLK */
1742 RCAR_GP_PIN(1, 25),
1743 };
1744 static const unsigned int can_clk_mux[] = {
1745 CAN_CLK_MARK,
1746 };
1747
1748 /* - CAN FD --------------------------------------------------------------- */
1749 static const unsigned int canfd0_data_a_pins[] = {
1750 /* TX, RX */
1751 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1752 };
1753 static const unsigned int canfd0_data_a_mux[] = {
1754 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1755 };
1756 static const unsigned int canfd0_data_b_pins[] = {
1757 /* TX, RX */
1758 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1759 };
1760 static const unsigned int canfd0_data_b_mux[] = {
1761 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1762 };
1763 static const unsigned int canfd1_data_pins[] = {
1764 /* TX, RX */
1765 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1766 };
1767 static const unsigned int canfd1_data_mux[] = {
1768 CANFD1_TX_MARK, CANFD1_RX_MARK,
1769 };
1770
1771 /* - DRIF0 --------------------------------------------------------------- */
1772 static const unsigned int drif0_ctrl_a_pins[] = {
1773 /* CLK, SYNC */
1774 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1775 };
1776 static const unsigned int drif0_ctrl_a_mux[] = {
1777 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1778 };
1779 static const unsigned int drif0_data0_a_pins[] = {
1780 /* D0 */
1781 RCAR_GP_PIN(6, 10),
1782 };
1783 static const unsigned int drif0_data0_a_mux[] = {
1784 RIF0_D0_A_MARK,
1785 };
1786 static const unsigned int drif0_data1_a_pins[] = {
1787 /* D1 */
1788 RCAR_GP_PIN(6, 7),
1789 };
1790 static const unsigned int drif0_data1_a_mux[] = {
1791 RIF0_D1_A_MARK,
1792 };
1793 static const unsigned int drif0_ctrl_b_pins[] = {
1794 /* CLK, SYNC */
1795 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1796 };
1797 static const unsigned int drif0_ctrl_b_mux[] = {
1798 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1799 };
1800 static const unsigned int drif0_data0_b_pins[] = {
1801 /* D0 */
1802 RCAR_GP_PIN(5, 1),
1803 };
1804 static const unsigned int drif0_data0_b_mux[] = {
1805 RIF0_D0_B_MARK,
1806 };
1807 static const unsigned int drif0_data1_b_pins[] = {
1808 /* D1 */
1809 RCAR_GP_PIN(5, 2),
1810 };
1811 static const unsigned int drif0_data1_b_mux[] = {
1812 RIF0_D1_B_MARK,
1813 };
1814 static const unsigned int drif0_ctrl_c_pins[] = {
1815 /* CLK, SYNC */
1816 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1817 };
1818 static const unsigned int drif0_ctrl_c_mux[] = {
1819 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1820 };
1821 static const unsigned int drif0_data0_c_pins[] = {
1822 /* D0 */
1823 RCAR_GP_PIN(5, 13),
1824 };
1825 static const unsigned int drif0_data0_c_mux[] = {
1826 RIF0_D0_C_MARK,
1827 };
1828 static const unsigned int drif0_data1_c_pins[] = {
1829 /* D1 */
1830 RCAR_GP_PIN(5, 14),
1831 };
1832 static const unsigned int drif0_data1_c_mux[] = {
1833 RIF0_D1_C_MARK,
1834 };
1835 /* - DRIF1 --------------------------------------------------------------- */
1836 static const unsigned int drif1_ctrl_a_pins[] = {
1837 /* CLK, SYNC */
1838 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1839 };
1840 static const unsigned int drif1_ctrl_a_mux[] = {
1841 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1842 };
1843 static const unsigned int drif1_data0_a_pins[] = {
1844 /* D0 */
1845 RCAR_GP_PIN(6, 19),
1846 };
1847 static const unsigned int drif1_data0_a_mux[] = {
1848 RIF1_D0_A_MARK,
1849 };
1850 static const unsigned int drif1_data1_a_pins[] = {
1851 /* D1 */
1852 RCAR_GP_PIN(6, 20),
1853 };
1854 static const unsigned int drif1_data1_a_mux[] = {
1855 RIF1_D1_A_MARK,
1856 };
1857 static const unsigned int drif1_ctrl_b_pins[] = {
1858 /* CLK, SYNC */
1859 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1860 };
1861 static const unsigned int drif1_ctrl_b_mux[] = {
1862 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1863 };
1864 static const unsigned int drif1_data0_b_pins[] = {
1865 /* D0 */
1866 RCAR_GP_PIN(5, 7),
1867 };
1868 static const unsigned int drif1_data0_b_mux[] = {
1869 RIF1_D0_B_MARK,
1870 };
1871 static const unsigned int drif1_data1_b_pins[] = {
1872 /* D1 */
1873 RCAR_GP_PIN(5, 8),
1874 };
1875 static const unsigned int drif1_data1_b_mux[] = {
1876 RIF1_D1_B_MARK,
1877 };
1878 static const unsigned int drif1_ctrl_c_pins[] = {
1879 /* CLK, SYNC */
1880 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1881 };
1882 static const unsigned int drif1_ctrl_c_mux[] = {
1883 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1884 };
1885 static const unsigned int drif1_data0_c_pins[] = {
1886 /* D0 */
1887 RCAR_GP_PIN(5, 6),
1888 };
1889 static const unsigned int drif1_data0_c_mux[] = {
1890 RIF1_D0_C_MARK,
1891 };
1892 static const unsigned int drif1_data1_c_pins[] = {
1893 /* D1 */
1894 RCAR_GP_PIN(5, 10),
1895 };
1896 static const unsigned int drif1_data1_c_mux[] = {
1897 RIF1_D1_C_MARK,
1898 };
1899 /* - DRIF2 --------------------------------------------------------------- */
1900 static const unsigned int drif2_ctrl_a_pins[] = {
1901 /* CLK, SYNC */
1902 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1903 };
1904 static const unsigned int drif2_ctrl_a_mux[] = {
1905 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1906 };
1907 static const unsigned int drif2_data0_a_pins[] = {
1908 /* D0 */
1909 RCAR_GP_PIN(6, 7),
1910 };
1911 static const unsigned int drif2_data0_a_mux[] = {
1912 RIF2_D0_A_MARK,
1913 };
1914 static const unsigned int drif2_data1_a_pins[] = {
1915 /* D1 */
1916 RCAR_GP_PIN(6, 10),
1917 };
1918 static const unsigned int drif2_data1_a_mux[] = {
1919 RIF2_D1_A_MARK,
1920 };
1921 static const unsigned int drif2_ctrl_b_pins[] = {
1922 /* CLK, SYNC */
1923 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1924 };
1925 static const unsigned int drif2_ctrl_b_mux[] = {
1926 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1927 };
1928 static const unsigned int drif2_data0_b_pins[] = {
1929 /* D0 */
1930 RCAR_GP_PIN(6, 30),
1931 };
1932 static const unsigned int drif2_data0_b_mux[] = {
1933 RIF2_D0_B_MARK,
1934 };
1935 static const unsigned int drif2_data1_b_pins[] = {
1936 /* D1 */
1937 RCAR_GP_PIN(6, 31),
1938 };
1939 static const unsigned int drif2_data1_b_mux[] = {
1940 RIF2_D1_B_MARK,
1941 };
1942 /* - DRIF3 --------------------------------------------------------------- */
1943 static const unsigned int drif3_ctrl_a_pins[] = {
1944 /* CLK, SYNC */
1945 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1946 };
1947 static const unsigned int drif3_ctrl_a_mux[] = {
1948 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1949 };
1950 static const unsigned int drif3_data0_a_pins[] = {
1951 /* D0 */
1952 RCAR_GP_PIN(6, 19),
1953 };
1954 static const unsigned int drif3_data0_a_mux[] = {
1955 RIF3_D0_A_MARK,
1956 };
1957 static const unsigned int drif3_data1_a_pins[] = {
1958 /* D1 */
1959 RCAR_GP_PIN(6, 20),
1960 };
1961 static const unsigned int drif3_data1_a_mux[] = {
1962 RIF3_D1_A_MARK,
1963 };
1964 static const unsigned int drif3_ctrl_b_pins[] = {
1965 /* CLK, SYNC */
1966 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1967 };
1968 static const unsigned int drif3_ctrl_b_mux[] = {
1969 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1970 };
1971 static const unsigned int drif3_data0_b_pins[] = {
1972 /* D0 */
1973 RCAR_GP_PIN(6, 28),
1974 };
1975 static const unsigned int drif3_data0_b_mux[] = {
1976 RIF3_D0_B_MARK,
1977 };
1978 static const unsigned int drif3_data1_b_pins[] = {
1979 /* D1 */
1980 RCAR_GP_PIN(6, 29),
1981 };
1982 static const unsigned int drif3_data1_b_mux[] = {
1983 RIF3_D1_B_MARK,
1984 };
1985
1986 /* - DU --------------------------------------------------------------------- */
1987 static const unsigned int du_rgb666_pins[] = {
1988 /* R[7:2], G[7:2], B[7:2] */
1989 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1990 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1991 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1992 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1993 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1994 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1995 };
1996 static const unsigned int du_rgb666_mux[] = {
1997 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1998 DU_DR3_MARK, DU_DR2_MARK,
1999 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2000 DU_DG3_MARK, DU_DG2_MARK,
2001 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2002 DU_DB3_MARK, DU_DB2_MARK,
2003 };
2004 static const unsigned int du_rgb888_pins[] = {
2005 /* R[7:0], G[7:0], B[7:0] */
2006 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2007 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2008 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2009 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2010 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2011 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2012 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2013 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2014 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2015 };
2016 static const unsigned int du_rgb888_mux[] = {
2017 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2018 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2019 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2020 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2021 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2022 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2023 };
2024 static const unsigned int du_clk_out_0_pins[] = {
2025 /* CLKOUT */
2026 RCAR_GP_PIN(1, 27),
2027 };
2028 static const unsigned int du_clk_out_0_mux[] = {
2029 DU_DOTCLKOUT0_MARK
2030 };
2031 static const unsigned int du_clk_out_1_pins[] = {
2032 /* CLKOUT */
2033 RCAR_GP_PIN(2, 3),
2034 };
2035 static const unsigned int du_clk_out_1_mux[] = {
2036 DU_DOTCLKOUT1_MARK
2037 };
2038 static const unsigned int du_sync_pins[] = {
2039 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2040 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2041 };
2042 static const unsigned int du_sync_mux[] = {
2043 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2044 };
2045 static const unsigned int du_oddf_pins[] = {
2046 /* EXDISP/EXODDF/EXCDE */
2047 RCAR_GP_PIN(2, 2),
2048 };
2049 static const unsigned int du_oddf_mux[] = {
2050 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2051 };
2052 static const unsigned int du_cde_pins[] = {
2053 /* CDE */
2054 RCAR_GP_PIN(2, 0),
2055 };
2056 static const unsigned int du_cde_mux[] = {
2057 DU_CDE_MARK,
2058 };
2059 static const unsigned int du_disp_pins[] = {
2060 /* DISP */
2061 RCAR_GP_PIN(2, 1),
2062 };
2063 static const unsigned int du_disp_mux[] = {
2064 DU_DISP_MARK,
2065 };
2066 /* - HSCIF0 ----------------------------------------------------------------- */
2067 static const unsigned int hscif0_data_pins[] = {
2068 /* RX, TX */
2069 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2070 };
2071 static const unsigned int hscif0_data_mux[] = {
2072 HRX0_MARK, HTX0_MARK,
2073 };
2074 static const unsigned int hscif0_clk_pins[] = {
2075 /* SCK */
2076 RCAR_GP_PIN(5, 12),
2077 };
2078 static const unsigned int hscif0_clk_mux[] = {
2079 HSCK0_MARK,
2080 };
2081 static const unsigned int hscif0_ctrl_pins[] = {
2082 /* RTS, CTS */
2083 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2084 };
2085 static const unsigned int hscif0_ctrl_mux[] = {
2086 HRTS0_N_MARK, HCTS0_N_MARK,
2087 };
2088 /* - HSCIF1 ----------------------------------------------------------------- */
2089 static const unsigned int hscif1_data_a_pins[] = {
2090 /* RX, TX */
2091 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2092 };
2093 static const unsigned int hscif1_data_a_mux[] = {
2094 HRX1_A_MARK, HTX1_A_MARK,
2095 };
2096 static const unsigned int hscif1_clk_a_pins[] = {
2097 /* SCK */
2098 RCAR_GP_PIN(6, 21),
2099 };
2100 static const unsigned int hscif1_clk_a_mux[] = {
2101 HSCK1_A_MARK,
2102 };
2103 static const unsigned int hscif1_ctrl_a_pins[] = {
2104 /* RTS, CTS */
2105 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2106 };
2107 static const unsigned int hscif1_ctrl_a_mux[] = {
2108 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2109 };
2110
2111 static const unsigned int hscif1_data_b_pins[] = {
2112 /* RX, TX */
2113 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2114 };
2115 static const unsigned int hscif1_data_b_mux[] = {
2116 HRX1_B_MARK, HTX1_B_MARK,
2117 };
2118 static const unsigned int hscif1_clk_b_pins[] = {
2119 /* SCK */
2120 RCAR_GP_PIN(5, 0),
2121 };
2122 static const unsigned int hscif1_clk_b_mux[] = {
2123 HSCK1_B_MARK,
2124 };
2125 static const unsigned int hscif1_ctrl_b_pins[] = {
2126 /* RTS, CTS */
2127 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2128 };
2129 static const unsigned int hscif1_ctrl_b_mux[] = {
2130 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2131 };
2132 /* - HSCIF2 ----------------------------------------------------------------- */
2133 static const unsigned int hscif2_data_a_pins[] = {
2134 /* RX, TX */
2135 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2136 };
2137 static const unsigned int hscif2_data_a_mux[] = {
2138 HRX2_A_MARK, HTX2_A_MARK,
2139 };
2140 static const unsigned int hscif2_clk_a_pins[] = {
2141 /* SCK */
2142 RCAR_GP_PIN(6, 10),
2143 };
2144 static const unsigned int hscif2_clk_a_mux[] = {
2145 HSCK2_A_MARK,
2146 };
2147 static const unsigned int hscif2_ctrl_a_pins[] = {
2148 /* RTS, CTS */
2149 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2150 };
2151 static const unsigned int hscif2_ctrl_a_mux[] = {
2152 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2153 };
2154
2155 static const unsigned int hscif2_data_b_pins[] = {
2156 /* RX, TX */
2157 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2158 };
2159 static const unsigned int hscif2_data_b_mux[] = {
2160 HRX2_B_MARK, HTX2_B_MARK,
2161 };
2162 static const unsigned int hscif2_clk_b_pins[] = {
2163 /* SCK */
2164 RCAR_GP_PIN(6, 21),
2165 };
2166 static const unsigned int hscif2_clk_b_mux[] = {
2167 HSCK2_B_MARK,
2168 };
2169 static const unsigned int hscif2_ctrl_b_pins[] = {
2170 /* RTS, CTS */
2171 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2172 };
2173 static const unsigned int hscif2_ctrl_b_mux[] = {
2174 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2175 };
2176 /* - HSCIF3 ----------------------------------------------------------------- */
2177 static const unsigned int hscif3_data_a_pins[] = {
2178 /* RX, TX */
2179 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2180 };
2181 static const unsigned int hscif3_data_a_mux[] = {
2182 HRX3_A_MARK, HTX3_A_MARK,
2183 };
2184 static const unsigned int hscif3_clk_pins[] = {
2185 /* SCK */
2186 RCAR_GP_PIN(1, 22),
2187 };
2188 static const unsigned int hscif3_clk_mux[] = {
2189 HSCK3_MARK,
2190 };
2191 static const unsigned int hscif3_ctrl_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2194 };
2195 static const unsigned int hscif3_ctrl_mux[] = {
2196 HRTS3_N_MARK, HCTS3_N_MARK,
2197 };
2198
2199 static const unsigned int hscif3_data_b_pins[] = {
2200 /* RX, TX */
2201 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2202 };
2203 static const unsigned int hscif3_data_b_mux[] = {
2204 HRX3_B_MARK, HTX3_B_MARK,
2205 };
2206 static const unsigned int hscif3_data_c_pins[] = {
2207 /* RX, TX */
2208 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2209 };
2210 static const unsigned int hscif3_data_c_mux[] = {
2211 HRX3_C_MARK, HTX3_C_MARK,
2212 };
2213 static const unsigned int hscif3_data_d_pins[] = {
2214 /* RX, TX */
2215 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2216 };
2217 static const unsigned int hscif3_data_d_mux[] = {
2218 HRX3_D_MARK, HTX3_D_MARK,
2219 };
2220 /* - HSCIF4 ----------------------------------------------------------------- */
2221 static const unsigned int hscif4_data_a_pins[] = {
2222 /* RX, TX */
2223 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2224 };
2225 static const unsigned int hscif4_data_a_mux[] = {
2226 HRX4_A_MARK, HTX4_A_MARK,
2227 };
2228 static const unsigned int hscif4_clk_pins[] = {
2229 /* SCK */
2230 RCAR_GP_PIN(1, 11),
2231 };
2232 static const unsigned int hscif4_clk_mux[] = {
2233 HSCK4_MARK,
2234 };
2235 static const unsigned int hscif4_ctrl_pins[] = {
2236 /* RTS, CTS */
2237 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2238 };
2239 static const unsigned int hscif4_ctrl_mux[] = {
2240 HRTS4_N_MARK, HCTS4_N_MARK,
2241 };
2242
2243 static const unsigned int hscif4_data_b_pins[] = {
2244 /* RX, TX */
2245 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2246 };
2247 static const unsigned int hscif4_data_b_mux[] = {
2248 HRX4_B_MARK, HTX4_B_MARK,
2249 };
2250
2251 /* - I2C -------------------------------------------------------------------- */
2252 static const unsigned int i2c0_pins[] = {
2253 /* SCL, SDA */
2254 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2255 };
2256
2257 static const unsigned int i2c0_mux[] = {
2258 SCL0_MARK, SDA0_MARK,
2259 };
2260
2261 static const unsigned int i2c1_a_pins[] = {
2262 /* SDA, SCL */
2263 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2264 };
2265 static const unsigned int i2c1_a_mux[] = {
2266 SDA1_A_MARK, SCL1_A_MARK,
2267 };
2268 static const unsigned int i2c1_b_pins[] = {
2269 /* SDA, SCL */
2270 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2271 };
2272 static const unsigned int i2c1_b_mux[] = {
2273 SDA1_B_MARK, SCL1_B_MARK,
2274 };
2275 static const unsigned int i2c2_a_pins[] = {
2276 /* SDA, SCL */
2277 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2278 };
2279 static const unsigned int i2c2_a_mux[] = {
2280 SDA2_A_MARK, SCL2_A_MARK,
2281 };
2282 static const unsigned int i2c2_b_pins[] = {
2283 /* SDA, SCL */
2284 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2285 };
2286 static const unsigned int i2c2_b_mux[] = {
2287 SDA2_B_MARK, SCL2_B_MARK,
2288 };
2289
2290 static const unsigned int i2c3_pins[] = {
2291 /* SCL, SDA */
2292 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2293 };
2294
2295 static const unsigned int i2c3_mux[] = {
2296 SCL3_MARK, SDA3_MARK,
2297 };
2298
2299 static const unsigned int i2c5_pins[] = {
2300 /* SCL, SDA */
2301 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2302 };
2303
2304 static const unsigned int i2c5_mux[] = {
2305 SCL5_MARK, SDA5_MARK,
2306 };
2307
2308 static const unsigned int i2c6_a_pins[] = {
2309 /* SDA, SCL */
2310 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2311 };
2312 static const unsigned int i2c6_a_mux[] = {
2313 SDA6_A_MARK, SCL6_A_MARK,
2314 };
2315 static const unsigned int i2c6_b_pins[] = {
2316 /* SDA, SCL */
2317 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2318 };
2319 static const unsigned int i2c6_b_mux[] = {
2320 SDA6_B_MARK, SCL6_B_MARK,
2321 };
2322 static const unsigned int i2c6_c_pins[] = {
2323 /* SDA, SCL */
2324 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2325 };
2326 static const unsigned int i2c6_c_mux[] = {
2327 SDA6_C_MARK, SCL6_C_MARK,
2328 };
2329
2330 /* - INTC-EX ---------------------------------------------------------------- */
2331 static const unsigned int intc_ex_irq0_pins[] = {
2332 /* IRQ0 */
2333 RCAR_GP_PIN(2, 0),
2334 };
2335 static const unsigned int intc_ex_irq0_mux[] = {
2336 IRQ0_MARK,
2337 };
2338 static const unsigned int intc_ex_irq1_pins[] = {
2339 /* IRQ1 */
2340 RCAR_GP_PIN(2, 1),
2341 };
2342 static const unsigned int intc_ex_irq1_mux[] = {
2343 IRQ1_MARK,
2344 };
2345 static const unsigned int intc_ex_irq2_pins[] = {
2346 /* IRQ2 */
2347 RCAR_GP_PIN(2, 2),
2348 };
2349 static const unsigned int intc_ex_irq2_mux[] = {
2350 IRQ2_MARK,
2351 };
2352 static const unsigned int intc_ex_irq3_pins[] = {
2353 /* IRQ3 */
2354 RCAR_GP_PIN(2, 3),
2355 };
2356 static const unsigned int intc_ex_irq3_mux[] = {
2357 IRQ3_MARK,
2358 };
2359 static const unsigned int intc_ex_irq4_pins[] = {
2360 /* IRQ4 */
2361 RCAR_GP_PIN(2, 4),
2362 };
2363 static const unsigned int intc_ex_irq4_mux[] = {
2364 IRQ4_MARK,
2365 };
2366 static const unsigned int intc_ex_irq5_pins[] = {
2367 /* IRQ5 */
2368 RCAR_GP_PIN(2, 5),
2369 };
2370 static const unsigned int intc_ex_irq5_mux[] = {
2371 IRQ5_MARK,
2372 };
2373
2374 /* - MSIOF0 ----------------------------------------------------------------- */
2375 static const unsigned int msiof0_clk_pins[] = {
2376 /* SCK */
2377 RCAR_GP_PIN(5, 17),
2378 };
2379 static const unsigned int msiof0_clk_mux[] = {
2380 MSIOF0_SCK_MARK,
2381 };
2382 static const unsigned int msiof0_sync_pins[] = {
2383 /* SYNC */
2384 RCAR_GP_PIN(5, 18),
2385 };
2386 static const unsigned int msiof0_sync_mux[] = {
2387 MSIOF0_SYNC_MARK,
2388 };
2389 static const unsigned int msiof0_ss1_pins[] = {
2390 /* SS1 */
2391 RCAR_GP_PIN(5, 19),
2392 };
2393 static const unsigned int msiof0_ss1_mux[] = {
2394 MSIOF0_SS1_MARK,
2395 };
2396 static const unsigned int msiof0_ss2_pins[] = {
2397 /* SS2 */
2398 RCAR_GP_PIN(5, 21),
2399 };
2400 static const unsigned int msiof0_ss2_mux[] = {
2401 MSIOF0_SS2_MARK,
2402 };
2403 static const unsigned int msiof0_txd_pins[] = {
2404 /* TXD */
2405 RCAR_GP_PIN(5, 20),
2406 };
2407 static const unsigned int msiof0_txd_mux[] = {
2408 MSIOF0_TXD_MARK,
2409 };
2410 static const unsigned int msiof0_rxd_pins[] = {
2411 /* RXD */
2412 RCAR_GP_PIN(5, 22),
2413 };
2414 static const unsigned int msiof0_rxd_mux[] = {
2415 MSIOF0_RXD_MARK,
2416 };
2417 /* - MSIOF1 ----------------------------------------------------------------- */
2418 static const unsigned int msiof1_clk_a_pins[] = {
2419 /* SCK */
2420 RCAR_GP_PIN(6, 8),
2421 };
2422 static const unsigned int msiof1_clk_a_mux[] = {
2423 MSIOF1_SCK_A_MARK,
2424 };
2425 static const unsigned int msiof1_sync_a_pins[] = {
2426 /* SYNC */
2427 RCAR_GP_PIN(6, 9),
2428 };
2429 static const unsigned int msiof1_sync_a_mux[] = {
2430 MSIOF1_SYNC_A_MARK,
2431 };
2432 static const unsigned int msiof1_ss1_a_pins[] = {
2433 /* SS1 */
2434 RCAR_GP_PIN(6, 5),
2435 };
2436 static const unsigned int msiof1_ss1_a_mux[] = {
2437 MSIOF1_SS1_A_MARK,
2438 };
2439 static const unsigned int msiof1_ss2_a_pins[] = {
2440 /* SS2 */
2441 RCAR_GP_PIN(6, 6),
2442 };
2443 static const unsigned int msiof1_ss2_a_mux[] = {
2444 MSIOF1_SS2_A_MARK,
2445 };
2446 static const unsigned int msiof1_txd_a_pins[] = {
2447 /* TXD */
2448 RCAR_GP_PIN(6, 7),
2449 };
2450 static const unsigned int msiof1_txd_a_mux[] = {
2451 MSIOF1_TXD_A_MARK,
2452 };
2453 static const unsigned int msiof1_rxd_a_pins[] = {
2454 /* RXD */
2455 RCAR_GP_PIN(6, 10),
2456 };
2457 static const unsigned int msiof1_rxd_a_mux[] = {
2458 MSIOF1_RXD_A_MARK,
2459 };
2460 static const unsigned int msiof1_clk_b_pins[] = {
2461 /* SCK */
2462 RCAR_GP_PIN(5, 9),
2463 };
2464 static const unsigned int msiof1_clk_b_mux[] = {
2465 MSIOF1_SCK_B_MARK,
2466 };
2467 static const unsigned int msiof1_sync_b_pins[] = {
2468 /* SYNC */
2469 RCAR_GP_PIN(5, 3),
2470 };
2471 static const unsigned int msiof1_sync_b_mux[] = {
2472 MSIOF1_SYNC_B_MARK,
2473 };
2474 static const unsigned int msiof1_ss1_b_pins[] = {
2475 /* SS1 */
2476 RCAR_GP_PIN(5, 4),
2477 };
2478 static const unsigned int msiof1_ss1_b_mux[] = {
2479 MSIOF1_SS1_B_MARK,
2480 };
2481 static const unsigned int msiof1_ss2_b_pins[] = {
2482 /* SS2 */
2483 RCAR_GP_PIN(5, 0),
2484 };
2485 static const unsigned int msiof1_ss2_b_mux[] = {
2486 MSIOF1_SS2_B_MARK,
2487 };
2488 static const unsigned int msiof1_txd_b_pins[] = {
2489 /* TXD */
2490 RCAR_GP_PIN(5, 8),
2491 };
2492 static const unsigned int msiof1_txd_b_mux[] = {
2493 MSIOF1_TXD_B_MARK,
2494 };
2495 static const unsigned int msiof1_rxd_b_pins[] = {
2496 /* RXD */
2497 RCAR_GP_PIN(5, 7),
2498 };
2499 static const unsigned int msiof1_rxd_b_mux[] = {
2500 MSIOF1_RXD_B_MARK,
2501 };
2502 static const unsigned int msiof1_clk_c_pins[] = {
2503 /* SCK */
2504 RCAR_GP_PIN(6, 17),
2505 };
2506 static const unsigned int msiof1_clk_c_mux[] = {
2507 MSIOF1_SCK_C_MARK,
2508 };
2509 static const unsigned int msiof1_sync_c_pins[] = {
2510 /* SYNC */
2511 RCAR_GP_PIN(6, 18),
2512 };
2513 static const unsigned int msiof1_sync_c_mux[] = {
2514 MSIOF1_SYNC_C_MARK,
2515 };
2516 static const unsigned int msiof1_ss1_c_pins[] = {
2517 /* SS1 */
2518 RCAR_GP_PIN(6, 21),
2519 };
2520 static const unsigned int msiof1_ss1_c_mux[] = {
2521 MSIOF1_SS1_C_MARK,
2522 };
2523 static const unsigned int msiof1_ss2_c_pins[] = {
2524 /* SS2 */
2525 RCAR_GP_PIN(6, 27),
2526 };
2527 static const unsigned int msiof1_ss2_c_mux[] = {
2528 MSIOF1_SS2_C_MARK,
2529 };
2530 static const unsigned int msiof1_txd_c_pins[] = {
2531 /* TXD */
2532 RCAR_GP_PIN(6, 20),
2533 };
2534 static const unsigned int msiof1_txd_c_mux[] = {
2535 MSIOF1_TXD_C_MARK,
2536 };
2537 static const unsigned int msiof1_rxd_c_pins[] = {
2538 /* RXD */
2539 RCAR_GP_PIN(6, 19),
2540 };
2541 static const unsigned int msiof1_rxd_c_mux[] = {
2542 MSIOF1_RXD_C_MARK,
2543 };
2544 static const unsigned int msiof1_clk_d_pins[] = {
2545 /* SCK */
2546 RCAR_GP_PIN(5, 12),
2547 };
2548 static const unsigned int msiof1_clk_d_mux[] = {
2549 MSIOF1_SCK_D_MARK,
2550 };
2551 static const unsigned int msiof1_sync_d_pins[] = {
2552 /* SYNC */
2553 RCAR_GP_PIN(5, 15),
2554 };
2555 static const unsigned int msiof1_sync_d_mux[] = {
2556 MSIOF1_SYNC_D_MARK,
2557 };
2558 static const unsigned int msiof1_ss1_d_pins[] = {
2559 /* SS1 */
2560 RCAR_GP_PIN(5, 16),
2561 };
2562 static const unsigned int msiof1_ss1_d_mux[] = {
2563 MSIOF1_SS1_D_MARK,
2564 };
2565 static const unsigned int msiof1_ss2_d_pins[] = {
2566 /* SS2 */
2567 RCAR_GP_PIN(5, 21),
2568 };
2569 static const unsigned int msiof1_ss2_d_mux[] = {
2570 MSIOF1_SS2_D_MARK,
2571 };
2572 static const unsigned int msiof1_txd_d_pins[] = {
2573 /* TXD */
2574 RCAR_GP_PIN(5, 14),
2575 };
2576 static const unsigned int msiof1_txd_d_mux[] = {
2577 MSIOF1_TXD_D_MARK,
2578 };
2579 static const unsigned int msiof1_rxd_d_pins[] = {
2580 /* RXD */
2581 RCAR_GP_PIN(5, 13),
2582 };
2583 static const unsigned int msiof1_rxd_d_mux[] = {
2584 MSIOF1_RXD_D_MARK,
2585 };
2586 static const unsigned int msiof1_clk_e_pins[] = {
2587 /* SCK */
2588 RCAR_GP_PIN(3, 0),
2589 };
2590 static const unsigned int msiof1_clk_e_mux[] = {
2591 MSIOF1_SCK_E_MARK,
2592 };
2593 static const unsigned int msiof1_sync_e_pins[] = {
2594 /* SYNC */
2595 RCAR_GP_PIN(3, 1),
2596 };
2597 static const unsigned int msiof1_sync_e_mux[] = {
2598 MSIOF1_SYNC_E_MARK,
2599 };
2600 static const unsigned int msiof1_ss1_e_pins[] = {
2601 /* SS1 */
2602 RCAR_GP_PIN(3, 4),
2603 };
2604 static const unsigned int msiof1_ss1_e_mux[] = {
2605 MSIOF1_SS1_E_MARK,
2606 };
2607 static const unsigned int msiof1_ss2_e_pins[] = {
2608 /* SS2 */
2609 RCAR_GP_PIN(3, 5),
2610 };
2611 static const unsigned int msiof1_ss2_e_mux[] = {
2612 MSIOF1_SS2_E_MARK,
2613 };
2614 static const unsigned int msiof1_txd_e_pins[] = {
2615 /* TXD */
2616 RCAR_GP_PIN(3, 3),
2617 };
2618 static const unsigned int msiof1_txd_e_mux[] = {
2619 MSIOF1_TXD_E_MARK,
2620 };
2621 static const unsigned int msiof1_rxd_e_pins[] = {
2622 /* RXD */
2623 RCAR_GP_PIN(3, 2),
2624 };
2625 static const unsigned int msiof1_rxd_e_mux[] = {
2626 MSIOF1_RXD_E_MARK,
2627 };
2628 static const unsigned int msiof1_clk_f_pins[] = {
2629 /* SCK */
2630 RCAR_GP_PIN(5, 23),
2631 };
2632 static const unsigned int msiof1_clk_f_mux[] = {
2633 MSIOF1_SCK_F_MARK,
2634 };
2635 static const unsigned int msiof1_sync_f_pins[] = {
2636 /* SYNC */
2637 RCAR_GP_PIN(5, 24),
2638 };
2639 static const unsigned int msiof1_sync_f_mux[] = {
2640 MSIOF1_SYNC_F_MARK,
2641 };
2642 static const unsigned int msiof1_ss1_f_pins[] = {
2643 /* SS1 */
2644 RCAR_GP_PIN(6, 1),
2645 };
2646 static const unsigned int msiof1_ss1_f_mux[] = {
2647 MSIOF1_SS1_F_MARK,
2648 };
2649 static const unsigned int msiof1_ss2_f_pins[] = {
2650 /* SS2 */
2651 RCAR_GP_PIN(6, 2),
2652 };
2653 static const unsigned int msiof1_ss2_f_mux[] = {
2654 MSIOF1_SS2_F_MARK,
2655 };
2656 static const unsigned int msiof1_txd_f_pins[] = {
2657 /* TXD */
2658 RCAR_GP_PIN(6, 0),
2659 };
2660 static const unsigned int msiof1_txd_f_mux[] = {
2661 MSIOF1_TXD_F_MARK,
2662 };
2663 static const unsigned int msiof1_rxd_f_pins[] = {
2664 /* RXD */
2665 RCAR_GP_PIN(5, 25),
2666 };
2667 static const unsigned int msiof1_rxd_f_mux[] = {
2668 MSIOF1_RXD_F_MARK,
2669 };
2670 static const unsigned int msiof1_clk_g_pins[] = {
2671 /* SCK */
2672 RCAR_GP_PIN(3, 6),
2673 };
2674 static const unsigned int msiof1_clk_g_mux[] = {
2675 MSIOF1_SCK_G_MARK,
2676 };
2677 static const unsigned int msiof1_sync_g_pins[] = {
2678 /* SYNC */
2679 RCAR_GP_PIN(3, 7),
2680 };
2681 static const unsigned int msiof1_sync_g_mux[] = {
2682 MSIOF1_SYNC_G_MARK,
2683 };
2684 static const unsigned int msiof1_ss1_g_pins[] = {
2685 /* SS1 */
2686 RCAR_GP_PIN(3, 10),
2687 };
2688 static const unsigned int msiof1_ss1_g_mux[] = {
2689 MSIOF1_SS1_G_MARK,
2690 };
2691 static const unsigned int msiof1_ss2_g_pins[] = {
2692 /* SS2 */
2693 RCAR_GP_PIN(3, 11),
2694 };
2695 static const unsigned int msiof1_ss2_g_mux[] = {
2696 MSIOF1_SS2_G_MARK,
2697 };
2698 static const unsigned int msiof1_txd_g_pins[] = {
2699 /* TXD */
2700 RCAR_GP_PIN(3, 9),
2701 };
2702 static const unsigned int msiof1_txd_g_mux[] = {
2703 MSIOF1_TXD_G_MARK,
2704 };
2705 static const unsigned int msiof1_rxd_g_pins[] = {
2706 /* RXD */
2707 RCAR_GP_PIN(3, 8),
2708 };
2709 static const unsigned int msiof1_rxd_g_mux[] = {
2710 MSIOF1_RXD_G_MARK,
2711 };
2712 /* - MSIOF2 ----------------------------------------------------------------- */
2713 static const unsigned int msiof2_clk_a_pins[] = {
2714 /* SCK */
2715 RCAR_GP_PIN(1, 9),
2716 };
2717 static const unsigned int msiof2_clk_a_mux[] = {
2718 MSIOF2_SCK_A_MARK,
2719 };
2720 static const unsigned int msiof2_sync_a_pins[] = {
2721 /* SYNC */
2722 RCAR_GP_PIN(1, 8),
2723 };
2724 static const unsigned int msiof2_sync_a_mux[] = {
2725 MSIOF2_SYNC_A_MARK,
2726 };
2727 static const unsigned int msiof2_ss1_a_pins[] = {
2728 /* SS1 */
2729 RCAR_GP_PIN(1, 6),
2730 };
2731 static const unsigned int msiof2_ss1_a_mux[] = {
2732 MSIOF2_SS1_A_MARK,
2733 };
2734 static const unsigned int msiof2_ss2_a_pins[] = {
2735 /* SS2 */
2736 RCAR_GP_PIN(1, 7),
2737 };
2738 static const unsigned int msiof2_ss2_a_mux[] = {
2739 MSIOF2_SS2_A_MARK,
2740 };
2741 static const unsigned int msiof2_txd_a_pins[] = {
2742 /* TXD */
2743 RCAR_GP_PIN(1, 11),
2744 };
2745 static const unsigned int msiof2_txd_a_mux[] = {
2746 MSIOF2_TXD_A_MARK,
2747 };
2748 static const unsigned int msiof2_rxd_a_pins[] = {
2749 /* RXD */
2750 RCAR_GP_PIN(1, 10),
2751 };
2752 static const unsigned int msiof2_rxd_a_mux[] = {
2753 MSIOF2_RXD_A_MARK,
2754 };
2755 static const unsigned int msiof2_clk_b_pins[] = {
2756 /* SCK */
2757 RCAR_GP_PIN(0, 4),
2758 };
2759 static const unsigned int msiof2_clk_b_mux[] = {
2760 MSIOF2_SCK_B_MARK,
2761 };
2762 static const unsigned int msiof2_sync_b_pins[] = {
2763 /* SYNC */
2764 RCAR_GP_PIN(0, 5),
2765 };
2766 static const unsigned int msiof2_sync_b_mux[] = {
2767 MSIOF2_SYNC_B_MARK,
2768 };
2769 static const unsigned int msiof2_ss1_b_pins[] = {
2770 /* SS1 */
2771 RCAR_GP_PIN(0, 0),
2772 };
2773 static const unsigned int msiof2_ss1_b_mux[] = {
2774 MSIOF2_SS1_B_MARK,
2775 };
2776 static const unsigned int msiof2_ss2_b_pins[] = {
2777 /* SS2 */
2778 RCAR_GP_PIN(0, 1),
2779 };
2780 static const unsigned int msiof2_ss2_b_mux[] = {
2781 MSIOF2_SS2_B_MARK,
2782 };
2783 static const unsigned int msiof2_txd_b_pins[] = {
2784 /* TXD */
2785 RCAR_GP_PIN(0, 7),
2786 };
2787 static const unsigned int msiof2_txd_b_mux[] = {
2788 MSIOF2_TXD_B_MARK,
2789 };
2790 static const unsigned int msiof2_rxd_b_pins[] = {
2791 /* RXD */
2792 RCAR_GP_PIN(0, 6),
2793 };
2794 static const unsigned int msiof2_rxd_b_mux[] = {
2795 MSIOF2_RXD_B_MARK,
2796 };
2797 static const unsigned int msiof2_clk_c_pins[] = {
2798 /* SCK */
2799 RCAR_GP_PIN(2, 12),
2800 };
2801 static const unsigned int msiof2_clk_c_mux[] = {
2802 MSIOF2_SCK_C_MARK,
2803 };
2804 static const unsigned int msiof2_sync_c_pins[] = {
2805 /* SYNC */
2806 RCAR_GP_PIN(2, 11),
2807 };
2808 static const unsigned int msiof2_sync_c_mux[] = {
2809 MSIOF2_SYNC_C_MARK,
2810 };
2811 static const unsigned int msiof2_ss1_c_pins[] = {
2812 /* SS1 */
2813 RCAR_GP_PIN(2, 10),
2814 };
2815 static const unsigned int msiof2_ss1_c_mux[] = {
2816 MSIOF2_SS1_C_MARK,
2817 };
2818 static const unsigned int msiof2_ss2_c_pins[] = {
2819 /* SS2 */
2820 RCAR_GP_PIN(2, 9),
2821 };
2822 static const unsigned int msiof2_ss2_c_mux[] = {
2823 MSIOF2_SS2_C_MARK,
2824 };
2825 static const unsigned int msiof2_txd_c_pins[] = {
2826 /* TXD */
2827 RCAR_GP_PIN(2, 14),
2828 };
2829 static const unsigned int msiof2_txd_c_mux[] = {
2830 MSIOF2_TXD_C_MARK,
2831 };
2832 static const unsigned int msiof2_rxd_c_pins[] = {
2833 /* RXD */
2834 RCAR_GP_PIN(2, 13),
2835 };
2836 static const unsigned int msiof2_rxd_c_mux[] = {
2837 MSIOF2_RXD_C_MARK,
2838 };
2839 static const unsigned int msiof2_clk_d_pins[] = {
2840 /* SCK */
2841 RCAR_GP_PIN(0, 8),
2842 };
2843 static const unsigned int msiof2_clk_d_mux[] = {
2844 MSIOF2_SCK_D_MARK,
2845 };
2846 static const unsigned int msiof2_sync_d_pins[] = {
2847 /* SYNC */
2848 RCAR_GP_PIN(0, 9),
2849 };
2850 static const unsigned int msiof2_sync_d_mux[] = {
2851 MSIOF2_SYNC_D_MARK,
2852 };
2853 static const unsigned int msiof2_ss1_d_pins[] = {
2854 /* SS1 */
2855 RCAR_GP_PIN(0, 12),
2856 };
2857 static const unsigned int msiof2_ss1_d_mux[] = {
2858 MSIOF2_SS1_D_MARK,
2859 };
2860 static const unsigned int msiof2_ss2_d_pins[] = {
2861 /* SS2 */
2862 RCAR_GP_PIN(0, 13),
2863 };
2864 static const unsigned int msiof2_ss2_d_mux[] = {
2865 MSIOF2_SS2_D_MARK,
2866 };
2867 static const unsigned int msiof2_txd_d_pins[] = {
2868 /* TXD */
2869 RCAR_GP_PIN(0, 11),
2870 };
2871 static const unsigned int msiof2_txd_d_mux[] = {
2872 MSIOF2_TXD_D_MARK,
2873 };
2874 static const unsigned int msiof2_rxd_d_pins[] = {
2875 /* RXD */
2876 RCAR_GP_PIN(0, 10),
2877 };
2878 static const unsigned int msiof2_rxd_d_mux[] = {
2879 MSIOF2_RXD_D_MARK,
2880 };
2881 /* - MSIOF3 ----------------------------------------------------------------- */
2882 static const unsigned int msiof3_clk_a_pins[] = {
2883 /* SCK */
2884 RCAR_GP_PIN(0, 0),
2885 };
2886 static const unsigned int msiof3_clk_a_mux[] = {
2887 MSIOF3_SCK_A_MARK,
2888 };
2889 static const unsigned int msiof3_sync_a_pins[] = {
2890 /* SYNC */
2891 RCAR_GP_PIN(0, 1),
2892 };
2893 static const unsigned int msiof3_sync_a_mux[] = {
2894 MSIOF3_SYNC_A_MARK,
2895 };
2896 static const unsigned int msiof3_ss1_a_pins[] = {
2897 /* SS1 */
2898 RCAR_GP_PIN(0, 14),
2899 };
2900 static const unsigned int msiof3_ss1_a_mux[] = {
2901 MSIOF3_SS1_A_MARK,
2902 };
2903 static const unsigned int msiof3_ss2_a_pins[] = {
2904 /* SS2 */
2905 RCAR_GP_PIN(0, 15),
2906 };
2907 static const unsigned int msiof3_ss2_a_mux[] = {
2908 MSIOF3_SS2_A_MARK,
2909 };
2910 static const unsigned int msiof3_txd_a_pins[] = {
2911 /* TXD */
2912 RCAR_GP_PIN(0, 3),
2913 };
2914 static const unsigned int msiof3_txd_a_mux[] = {
2915 MSIOF3_TXD_A_MARK,
2916 };
2917 static const unsigned int msiof3_rxd_a_pins[] = {
2918 /* RXD */
2919 RCAR_GP_PIN(0, 2),
2920 };
2921 static const unsigned int msiof3_rxd_a_mux[] = {
2922 MSIOF3_RXD_A_MARK,
2923 };
2924 static const unsigned int msiof3_clk_b_pins[] = {
2925 /* SCK */
2926 RCAR_GP_PIN(1, 2),
2927 };
2928 static const unsigned int msiof3_clk_b_mux[] = {
2929 MSIOF3_SCK_B_MARK,
2930 };
2931 static const unsigned int msiof3_sync_b_pins[] = {
2932 /* SYNC */
2933 RCAR_GP_PIN(1, 0),
2934 };
2935 static const unsigned int msiof3_sync_b_mux[] = {
2936 MSIOF3_SYNC_B_MARK,
2937 };
2938 static const unsigned int msiof3_ss1_b_pins[] = {
2939 /* SS1 */
2940 RCAR_GP_PIN(1, 4),
2941 };
2942 static const unsigned int msiof3_ss1_b_mux[] = {
2943 MSIOF3_SS1_B_MARK,
2944 };
2945 static const unsigned int msiof3_ss2_b_pins[] = {
2946 /* SS2 */
2947 RCAR_GP_PIN(1, 5),
2948 };
2949 static const unsigned int msiof3_ss2_b_mux[] = {
2950 MSIOF3_SS2_B_MARK,
2951 };
2952 static const unsigned int msiof3_txd_b_pins[] = {
2953 /* TXD */
2954 RCAR_GP_PIN(1, 1),
2955 };
2956 static const unsigned int msiof3_txd_b_mux[] = {
2957 MSIOF3_TXD_B_MARK,
2958 };
2959 static const unsigned int msiof3_rxd_b_pins[] = {
2960 /* RXD */
2961 RCAR_GP_PIN(1, 3),
2962 };
2963 static const unsigned int msiof3_rxd_b_mux[] = {
2964 MSIOF3_RXD_B_MARK,
2965 };
2966 static const unsigned int msiof3_clk_c_pins[] = {
2967 /* SCK */
2968 RCAR_GP_PIN(1, 12),
2969 };
2970 static const unsigned int msiof3_clk_c_mux[] = {
2971 MSIOF3_SCK_C_MARK,
2972 };
2973 static const unsigned int msiof3_sync_c_pins[] = {
2974 /* SYNC */
2975 RCAR_GP_PIN(1, 13),
2976 };
2977 static const unsigned int msiof3_sync_c_mux[] = {
2978 MSIOF3_SYNC_C_MARK,
2979 };
2980 static const unsigned int msiof3_txd_c_pins[] = {
2981 /* TXD */
2982 RCAR_GP_PIN(1, 15),
2983 };
2984 static const unsigned int msiof3_txd_c_mux[] = {
2985 MSIOF3_TXD_C_MARK,
2986 };
2987 static const unsigned int msiof3_rxd_c_pins[] = {
2988 /* RXD */
2989 RCAR_GP_PIN(1, 14),
2990 };
2991 static const unsigned int msiof3_rxd_c_mux[] = {
2992 MSIOF3_RXD_C_MARK,
2993 };
2994 static const unsigned int msiof3_clk_d_pins[] = {
2995 /* SCK */
2996 RCAR_GP_PIN(1, 22),
2997 };
2998 static const unsigned int msiof3_clk_d_mux[] = {
2999 MSIOF3_SCK_D_MARK,
3000 };
3001 static const unsigned int msiof3_sync_d_pins[] = {
3002 /* SYNC */
3003 RCAR_GP_PIN(1, 23),
3004 };
3005 static const unsigned int msiof3_sync_d_mux[] = {
3006 MSIOF3_SYNC_D_MARK,
3007 };
3008 static const unsigned int msiof3_ss1_d_pins[] = {
3009 /* SS1 */
3010 RCAR_GP_PIN(1, 26),
3011 };
3012 static const unsigned int msiof3_ss1_d_mux[] = {
3013 MSIOF3_SS1_D_MARK,
3014 };
3015 static const unsigned int msiof3_txd_d_pins[] = {
3016 /* TXD */
3017 RCAR_GP_PIN(1, 25),
3018 };
3019 static const unsigned int msiof3_txd_d_mux[] = {
3020 MSIOF3_TXD_D_MARK,
3021 };
3022 static const unsigned int msiof3_rxd_d_pins[] = {
3023 /* RXD */
3024 RCAR_GP_PIN(1, 24),
3025 };
3026 static const unsigned int msiof3_rxd_d_mux[] = {
3027 MSIOF3_RXD_D_MARK,
3028 };
3029
3030 /* - PWM0 --------------------------------------------------------------------*/
3031 static const unsigned int pwm0_pins[] = {
3032 /* PWM */
3033 RCAR_GP_PIN(2, 6),
3034 };
3035 static const unsigned int pwm0_mux[] = {
3036 PWM0_MARK,
3037 };
3038 /* - PWM1 --------------------------------------------------------------------*/
3039 static const unsigned int pwm1_a_pins[] = {
3040 /* PWM */
3041 RCAR_GP_PIN(2, 7),
3042 };
3043 static const unsigned int pwm1_a_mux[] = {
3044 PWM1_A_MARK,
3045 };
3046 static const unsigned int pwm1_b_pins[] = {
3047 /* PWM */
3048 RCAR_GP_PIN(1, 8),
3049 };
3050 static const unsigned int pwm1_b_mux[] = {
3051 PWM1_B_MARK,
3052 };
3053 /* - PWM2 --------------------------------------------------------------------*/
3054 static const unsigned int pwm2_a_pins[] = {
3055 /* PWM */
3056 RCAR_GP_PIN(2, 8),
3057 };
3058 static const unsigned int pwm2_a_mux[] = {
3059 PWM2_A_MARK,
3060 };
3061 static const unsigned int pwm2_b_pins[] = {
3062 /* PWM */
3063 RCAR_GP_PIN(1, 11),
3064 };
3065 static const unsigned int pwm2_b_mux[] = {
3066 PWM2_B_MARK,
3067 };
3068 /* - PWM3 --------------------------------------------------------------------*/
3069 static const unsigned int pwm3_a_pins[] = {
3070 /* PWM */
3071 RCAR_GP_PIN(1, 0),
3072 };
3073 static const unsigned int pwm3_a_mux[] = {
3074 PWM3_A_MARK,
3075 };
3076 static const unsigned int pwm3_b_pins[] = {
3077 /* PWM */
3078 RCAR_GP_PIN(2, 2),
3079 };
3080 static const unsigned int pwm3_b_mux[] = {
3081 PWM3_B_MARK,
3082 };
3083 /* - PWM4 --------------------------------------------------------------------*/
3084 static const unsigned int pwm4_a_pins[] = {
3085 /* PWM */
3086 RCAR_GP_PIN(1, 1),
3087 };
3088 static const unsigned int pwm4_a_mux[] = {
3089 PWM4_A_MARK,
3090 };
3091 static const unsigned int pwm4_b_pins[] = {
3092 /* PWM */
3093 RCAR_GP_PIN(2, 3),
3094 };
3095 static const unsigned int pwm4_b_mux[] = {
3096 PWM4_B_MARK,
3097 };
3098 /* - PWM5 --------------------------------------------------------------------*/
3099 static const unsigned int pwm5_a_pins[] = {
3100 /* PWM */
3101 RCAR_GP_PIN(1, 2),
3102 };
3103 static const unsigned int pwm5_a_mux[] = {
3104 PWM5_A_MARK,
3105 };
3106 static const unsigned int pwm5_b_pins[] = {
3107 /* PWM */
3108 RCAR_GP_PIN(2, 4),
3109 };
3110 static const unsigned int pwm5_b_mux[] = {
3111 PWM5_B_MARK,
3112 };
3113 /* - PWM6 --------------------------------------------------------------------*/
3114 static const unsigned int pwm6_a_pins[] = {
3115 /* PWM */
3116 RCAR_GP_PIN(1, 3),
3117 };
3118 static const unsigned int pwm6_a_mux[] = {
3119 PWM6_A_MARK,
3120 };
3121 static const unsigned int pwm6_b_pins[] = {
3122 /* PWM */
3123 RCAR_GP_PIN(2, 5),
3124 };
3125 static const unsigned int pwm6_b_mux[] = {
3126 PWM6_B_MARK,
3127 };
3128
3129 /* - QSPI0 ------------------------------------------------------------------ */
3130 static const unsigned int qspi0_ctrl_pins[] = {
3131 /* QSPI0_SPCLK, QSPI0_SSL */
3132 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3133 };
3134 static const unsigned int qspi0_ctrl_mux[] = {
3135 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3136 };
3137 static const unsigned int qspi0_data2_pins[] = {
3138 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3139 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3140 };
3141 static const unsigned int qspi0_data2_mux[] = {
3142 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3143 };
3144 static const unsigned int qspi0_data4_pins[] = {
3145 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3146 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3147 };
3148 static const unsigned int qspi0_data4_mux[] = {
3149 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3150 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3151 };
3152 /* - QSPI1 ------------------------------------------------------------------ */
3153 static const unsigned int qspi1_ctrl_pins[] = {
3154 /* QSPI1_SPCLK, QSPI1_SSL */
3155 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3156 };
3157 static const unsigned int qspi1_ctrl_mux[] = {
3158 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3159 };
3160 static const unsigned int qspi1_data2_pins[] = {
3161 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3162 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3163 };
3164 static const unsigned int qspi1_data2_mux[] = {
3165 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3166 };
3167 static const unsigned int qspi1_data4_pins[] = {
3168 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3169 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3170 };
3171 static const unsigned int qspi1_data4_mux[] = {
3172 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3173 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3174 };
3175
3176 /* - SATA --------------------------------------------------------------------*/
3177 static const unsigned int sata0_devslp_a_pins[] = {
3178 /* DEVSLP */
3179 RCAR_GP_PIN(6, 16),
3180 };
3181 static const unsigned int sata0_devslp_a_mux[] = {
3182 SATA_DEVSLP_A_MARK,
3183 };
3184 static const unsigned int sata0_devslp_b_pins[] = {
3185 /* DEVSLP */
3186 RCAR_GP_PIN(4, 6),
3187 };
3188 static const unsigned int sata0_devslp_b_mux[] = {
3189 SATA_DEVSLP_B_MARK,
3190 };
3191
3192 /* - SCIF0 ------------------------------------------------------------------ */
3193 static const unsigned int scif0_data_pins[] = {
3194 /* RX, TX */
3195 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3196 };
3197 static const unsigned int scif0_data_mux[] = {
3198 RX0_MARK, TX0_MARK,
3199 };
3200 static const unsigned int scif0_clk_pins[] = {
3201 /* SCK */
3202 RCAR_GP_PIN(5, 0),
3203 };
3204 static const unsigned int scif0_clk_mux[] = {
3205 SCK0_MARK,
3206 };
3207 static const unsigned int scif0_ctrl_pins[] = {
3208 /* RTS, CTS */
3209 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3210 };
3211 static const unsigned int scif0_ctrl_mux[] = {
3212 RTS0_N_MARK, CTS0_N_MARK,
3213 };
3214 /* - SCIF1 ------------------------------------------------------------------ */
3215 static const unsigned int scif1_data_a_pins[] = {
3216 /* RX, TX */
3217 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3218 };
3219 static const unsigned int scif1_data_a_mux[] = {
3220 RX1_A_MARK, TX1_A_MARK,
3221 };
3222 static const unsigned int scif1_clk_pins[] = {
3223 /* SCK */
3224 RCAR_GP_PIN(6, 21),
3225 };
3226 static const unsigned int scif1_clk_mux[] = {
3227 SCK1_MARK,
3228 };
3229 static const unsigned int scif1_ctrl_pins[] = {
3230 /* RTS, CTS */
3231 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3232 };
3233 static const unsigned int scif1_ctrl_mux[] = {
3234 RTS1_N_MARK, CTS1_N_MARK,
3235 };
3236
3237 static const unsigned int scif1_data_b_pins[] = {
3238 /* RX, TX */
3239 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3240 };
3241 static const unsigned int scif1_data_b_mux[] = {
3242 RX1_B_MARK, TX1_B_MARK,
3243 };
3244 /* - SCIF2 ------------------------------------------------------------------ */
3245 static const unsigned int scif2_data_a_pins[] = {
3246 /* RX, TX */
3247 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3248 };
3249 static const unsigned int scif2_data_a_mux[] = {
3250 RX2_A_MARK, TX2_A_MARK,
3251 };
3252 static const unsigned int scif2_clk_pins[] = {
3253 /* SCK */
3254 RCAR_GP_PIN(5, 9),
3255 };
3256 static const unsigned int scif2_clk_mux[] = {
3257 SCK2_MARK,
3258 };
3259 static const unsigned int scif2_data_b_pins[] = {
3260 /* RX, TX */
3261 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3262 };
3263 static const unsigned int scif2_data_b_mux[] = {
3264 RX2_B_MARK, TX2_B_MARK,
3265 };
3266 /* - SCIF3 ------------------------------------------------------------------ */
3267 static const unsigned int scif3_data_a_pins[] = {
3268 /* RX, TX */
3269 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3270 };
3271 static const unsigned int scif3_data_a_mux[] = {
3272 RX3_A_MARK, TX3_A_MARK,
3273 };
3274 static const unsigned int scif3_clk_pins[] = {
3275 /* SCK */
3276 RCAR_GP_PIN(1, 22),
3277 };
3278 static const unsigned int scif3_clk_mux[] = {
3279 SCK3_MARK,
3280 };
3281 static const unsigned int scif3_ctrl_pins[] = {
3282 /* RTS, CTS */
3283 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3284 };
3285 static const unsigned int scif3_ctrl_mux[] = {
3286 RTS3_N_MARK, CTS3_N_MARK,
3287 };
3288 static const unsigned int scif3_data_b_pins[] = {
3289 /* RX, TX */
3290 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3291 };
3292 static const unsigned int scif3_data_b_mux[] = {
3293 RX3_B_MARK, TX3_B_MARK,
3294 };
3295 /* - SCIF4 ------------------------------------------------------------------ */
3296 static const unsigned int scif4_data_a_pins[] = {
3297 /* RX, TX */
3298 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3299 };
3300 static const unsigned int scif4_data_a_mux[] = {
3301 RX4_A_MARK, TX4_A_MARK,
3302 };
3303 static const unsigned int scif4_clk_a_pins[] = {
3304 /* SCK */
3305 RCAR_GP_PIN(2, 10),
3306 };
3307 static const unsigned int scif4_clk_a_mux[] = {
3308 SCK4_A_MARK,
3309 };
3310 static const unsigned int scif4_ctrl_a_pins[] = {
3311 /* RTS, CTS */
3312 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3313 };
3314 static const unsigned int scif4_ctrl_a_mux[] = {
3315 RTS4_N_A_MARK, CTS4_N_A_MARK,
3316 };
3317 static const unsigned int scif4_data_b_pins[] = {
3318 /* RX, TX */
3319 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3320 };
3321 static const unsigned int scif4_data_b_mux[] = {
3322 RX4_B_MARK, TX4_B_MARK,
3323 };
3324 static const unsigned int scif4_clk_b_pins[] = {
3325 /* SCK */
3326 RCAR_GP_PIN(1, 5),
3327 };
3328 static const unsigned int scif4_clk_b_mux[] = {
3329 SCK4_B_MARK,
3330 };
3331 static const unsigned int scif4_ctrl_b_pins[] = {
3332 /* RTS, CTS */
3333 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3334 };
3335 static const unsigned int scif4_ctrl_b_mux[] = {
3336 RTS4_N_B_MARK, CTS4_N_B_MARK,
3337 };
3338 static const unsigned int scif4_data_c_pins[] = {
3339 /* RX, TX */
3340 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3341 };
3342 static const unsigned int scif4_data_c_mux[] = {
3343 RX4_C_MARK, TX4_C_MARK,
3344 };
3345 static const unsigned int scif4_clk_c_pins[] = {
3346 /* SCK */
3347 RCAR_GP_PIN(0, 8),
3348 };
3349 static const unsigned int scif4_clk_c_mux[] = {
3350 SCK4_C_MARK,
3351 };
3352 static const unsigned int scif4_ctrl_c_pins[] = {
3353 /* RTS, CTS */
3354 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3355 };
3356 static const unsigned int scif4_ctrl_c_mux[] = {
3357 RTS4_N_C_MARK, CTS4_N_C_MARK,
3358 };
3359 /* - SCIF5 ------------------------------------------------------------------ */
3360 static const unsigned int scif5_data_pins[] = {
3361 /* RX, TX */
3362 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3363 };
3364 static const unsigned int scif5_data_mux[] = {
3365 RX5_MARK, TX5_MARK,
3366 };
3367 static const unsigned int scif5_clk_pins[] = {
3368 /* SCK */
3369 RCAR_GP_PIN(6, 21),
3370 };
3371 static const unsigned int scif5_clk_mux[] = {
3372 SCK5_MARK,
3373 };
3374
3375 /* - SCIF Clock ------------------------------------------------------------- */
3376 static const unsigned int scif_clk_a_pins[] = {
3377 /* SCIF_CLK */
3378 RCAR_GP_PIN(6, 23),
3379 };
3380 static const unsigned int scif_clk_a_mux[] = {
3381 SCIF_CLK_A_MARK,
3382 };
3383 static const unsigned int scif_clk_b_pins[] = {
3384 /* SCIF_CLK */
3385 RCAR_GP_PIN(5, 9),
3386 };
3387 static const unsigned int scif_clk_b_mux[] = {
3388 SCIF_CLK_B_MARK,
3389 };
3390
3391 /* - SDHI0 ------------------------------------------------------------------ */
3392 static const unsigned int sdhi0_data1_pins[] = {
3393 /* D0 */
3394 RCAR_GP_PIN(3, 2),
3395 };
3396 static const unsigned int sdhi0_data1_mux[] = {
3397 SD0_DAT0_MARK,
3398 };
3399 static const unsigned int sdhi0_data4_pins[] = {
3400 /* D[0:3] */
3401 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3402 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3403 };
3404 static const unsigned int sdhi0_data4_mux[] = {
3405 SD0_DAT0_MARK, SD0_DAT1_MARK,
3406 SD0_DAT2_MARK, SD0_DAT3_MARK,
3407 };
3408 static const unsigned int sdhi0_ctrl_pins[] = {
3409 /* CLK, CMD */
3410 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3411 };
3412 static const unsigned int sdhi0_ctrl_mux[] = {
3413 SD0_CLK_MARK, SD0_CMD_MARK,
3414 };
3415 static const unsigned int sdhi0_cd_pins[] = {
3416 /* CD */
3417 RCAR_GP_PIN(3, 12),
3418 };
3419 static const unsigned int sdhi0_cd_mux[] = {
3420 SD0_CD_MARK,
3421 };
3422 static const unsigned int sdhi0_wp_pins[] = {
3423 /* WP */
3424 RCAR_GP_PIN(3, 13),
3425 };
3426 static const unsigned int sdhi0_wp_mux[] = {
3427 SD0_WP_MARK,
3428 };
3429 /* - SDHI1 ------------------------------------------------------------------ */
3430 static const unsigned int sdhi1_data1_pins[] = {
3431 /* D0 */
3432 RCAR_GP_PIN(3, 8),
3433 };
3434 static const unsigned int sdhi1_data1_mux[] = {
3435 SD1_DAT0_MARK,
3436 };
3437 static const unsigned int sdhi1_data4_pins[] = {
3438 /* D[0:3] */
3439 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3440 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3441 };
3442 static const unsigned int sdhi1_data4_mux[] = {
3443 SD1_DAT0_MARK, SD1_DAT1_MARK,
3444 SD1_DAT2_MARK, SD1_DAT3_MARK,
3445 };
3446 static const unsigned int sdhi1_ctrl_pins[] = {
3447 /* CLK, CMD */
3448 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3449 };
3450 static const unsigned int sdhi1_ctrl_mux[] = {
3451 SD1_CLK_MARK, SD1_CMD_MARK,
3452 };
3453 static const unsigned int sdhi1_cd_pins[] = {
3454 /* CD */
3455 RCAR_GP_PIN(3, 14),
3456 };
3457 static const unsigned int sdhi1_cd_mux[] = {
3458 SD1_CD_MARK,
3459 };
3460 static const unsigned int sdhi1_wp_pins[] = {
3461 /* WP */
3462 RCAR_GP_PIN(3, 15),
3463 };
3464 static const unsigned int sdhi1_wp_mux[] = {
3465 SD1_WP_MARK,
3466 };
3467 /* - SDHI2 ------------------------------------------------------------------ */
3468 static const unsigned int sdhi2_data1_pins[] = {
3469 /* D0 */
3470 RCAR_GP_PIN(4, 2),
3471 };
3472 static const unsigned int sdhi2_data1_mux[] = {
3473 SD2_DAT0_MARK,
3474 };
3475 static const unsigned int sdhi2_data4_pins[] = {
3476 /* D[0:3] */
3477 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3478 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3479 };
3480 static const unsigned int sdhi2_data4_mux[] = {
3481 SD2_DAT0_MARK, SD2_DAT1_MARK,
3482 SD2_DAT2_MARK, SD2_DAT3_MARK,
3483 };
3484 static const unsigned int sdhi2_data8_pins[] = {
3485 /* D[0:7] */
3486 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3487 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3488 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3489 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3490 };
3491 static const unsigned int sdhi2_data8_mux[] = {
3492 SD2_DAT0_MARK, SD2_DAT1_MARK,
3493 SD2_DAT2_MARK, SD2_DAT3_MARK,
3494 SD2_DAT4_MARK, SD2_DAT5_MARK,
3495 SD2_DAT6_MARK, SD2_DAT7_MARK,
3496 };
3497 static const unsigned int sdhi2_ctrl_pins[] = {
3498 /* CLK, CMD */
3499 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3500 };
3501 static const unsigned int sdhi2_ctrl_mux[] = {
3502 SD2_CLK_MARK, SD2_CMD_MARK,
3503 };
3504 static const unsigned int sdhi2_cd_a_pins[] = {
3505 /* CD */
3506 RCAR_GP_PIN(4, 13),
3507 };
3508 static const unsigned int sdhi2_cd_a_mux[] = {
3509 SD2_CD_A_MARK,
3510 };
3511 static const unsigned int sdhi2_cd_b_pins[] = {
3512 /* CD */
3513 RCAR_GP_PIN(5, 10),
3514 };
3515 static const unsigned int sdhi2_cd_b_mux[] = {
3516 SD2_CD_B_MARK,
3517 };
3518 static const unsigned int sdhi2_wp_a_pins[] = {
3519 /* WP */
3520 RCAR_GP_PIN(4, 14),
3521 };
3522 static const unsigned int sdhi2_wp_a_mux[] = {
3523 SD2_WP_A_MARK,
3524 };
3525 static const unsigned int sdhi2_wp_b_pins[] = {
3526 /* WP */
3527 RCAR_GP_PIN(5, 11),
3528 };
3529 static const unsigned int sdhi2_wp_b_mux[] = {
3530 SD2_WP_B_MARK,
3531 };
3532 static const unsigned int sdhi2_ds_pins[] = {
3533 /* DS */
3534 RCAR_GP_PIN(4, 6),
3535 };
3536 static const unsigned int sdhi2_ds_mux[] = {
3537 SD2_DS_MARK,
3538 };
3539 /* - SDHI3 ------------------------------------------------------------------ */
3540 static const unsigned int sdhi3_data1_pins[] = {
3541 /* D0 */
3542 RCAR_GP_PIN(4, 9),
3543 };
3544 static const unsigned int sdhi3_data1_mux[] = {
3545 SD3_DAT0_MARK,
3546 };
3547 static const unsigned int sdhi3_data4_pins[] = {
3548 /* D[0:3] */
3549 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3550 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3551 };
3552 static const unsigned int sdhi3_data4_mux[] = {
3553 SD3_DAT0_MARK, SD3_DAT1_MARK,
3554 SD3_DAT2_MARK, SD3_DAT3_MARK,
3555 };
3556 static const unsigned int sdhi3_data8_pins[] = {
3557 /* D[0:7] */
3558 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3559 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3560 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3561 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3562 };
3563 static const unsigned int sdhi3_data8_mux[] = {
3564 SD3_DAT0_MARK, SD3_DAT1_MARK,
3565 SD3_DAT2_MARK, SD3_DAT3_MARK,
3566 SD3_DAT4_MARK, SD3_DAT5_MARK,
3567 SD3_DAT6_MARK, SD3_DAT7_MARK,
3568 };
3569 static const unsigned int sdhi3_ctrl_pins[] = {
3570 /* CLK, CMD */
3571 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3572 };
3573 static const unsigned int sdhi3_ctrl_mux[] = {
3574 SD3_CLK_MARK, SD3_CMD_MARK,
3575 };
3576 static const unsigned int sdhi3_cd_pins[] = {
3577 /* CD */
3578 RCAR_GP_PIN(4, 15),
3579 };
3580 static const unsigned int sdhi3_cd_mux[] = {
3581 SD3_CD_MARK,
3582 };
3583 static const unsigned int sdhi3_wp_pins[] = {
3584 /* WP */
3585 RCAR_GP_PIN(4, 16),
3586 };
3587 static const unsigned int sdhi3_wp_mux[] = {
3588 SD3_WP_MARK,
3589 };
3590 static const unsigned int sdhi3_ds_pins[] = {
3591 /* DS */
3592 RCAR_GP_PIN(4, 17),
3593 };
3594 static const unsigned int sdhi3_ds_mux[] = {
3595 SD3_DS_MARK,
3596 };
3597
3598 /* - SSI -------------------------------------------------------------------- */
3599 static const unsigned int ssi0_data_pins[] = {
3600 /* SDATA */
3601 RCAR_GP_PIN(6, 2),
3602 };
3603 static const unsigned int ssi0_data_mux[] = {
3604 SSI_SDATA0_MARK,
3605 };
3606 static const unsigned int ssi01239_ctrl_pins[] = {
3607 /* SCK, WS */
3608 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3609 };
3610 static const unsigned int ssi01239_ctrl_mux[] = {
3611 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3612 };
3613 static const unsigned int ssi1_data_a_pins[] = {
3614 /* SDATA */
3615 RCAR_GP_PIN(6, 3),
3616 };
3617 static const unsigned int ssi1_data_a_mux[] = {
3618 SSI_SDATA1_A_MARK,
3619 };
3620 static const unsigned int ssi1_data_b_pins[] = {
3621 /* SDATA */
3622 RCAR_GP_PIN(5, 12),
3623 };
3624 static const unsigned int ssi1_data_b_mux[] = {
3625 SSI_SDATA1_B_MARK,
3626 };
3627 static const unsigned int ssi1_ctrl_a_pins[] = {
3628 /* SCK, WS */
3629 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3630 };
3631 static const unsigned int ssi1_ctrl_a_mux[] = {
3632 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3633 };
3634 static const unsigned int ssi1_ctrl_b_pins[] = {
3635 /* SCK, WS */
3636 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3637 };
3638 static const unsigned int ssi1_ctrl_b_mux[] = {
3639 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3640 };
3641 static const unsigned int ssi2_data_a_pins[] = {
3642 /* SDATA */
3643 RCAR_GP_PIN(6, 4),
3644 };
3645 static const unsigned int ssi2_data_a_mux[] = {
3646 SSI_SDATA2_A_MARK,
3647 };
3648 static const unsigned int ssi2_data_b_pins[] = {
3649 /* SDATA */
3650 RCAR_GP_PIN(5, 13),
3651 };
3652 static const unsigned int ssi2_data_b_mux[] = {
3653 SSI_SDATA2_B_MARK,
3654 };
3655 static const unsigned int ssi2_ctrl_a_pins[] = {
3656 /* SCK, WS */
3657 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3658 };
3659 static const unsigned int ssi2_ctrl_a_mux[] = {
3660 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3661 };
3662 static const unsigned int ssi2_ctrl_b_pins[] = {
3663 /* SCK, WS */
3664 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3665 };
3666 static const unsigned int ssi2_ctrl_b_mux[] = {
3667 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3668 };
3669 static const unsigned int ssi3_data_pins[] = {
3670 /* SDATA */
3671 RCAR_GP_PIN(6, 7),
3672 };
3673 static const unsigned int ssi3_data_mux[] = {
3674 SSI_SDATA3_MARK,
3675 };
3676 static const unsigned int ssi349_ctrl_pins[] = {
3677 /* SCK, WS */
3678 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3679 };
3680 static const unsigned int ssi349_ctrl_mux[] = {
3681 SSI_SCK349_MARK, SSI_WS349_MARK,
3682 };
3683 static const unsigned int ssi4_data_pins[] = {
3684 /* SDATA */
3685 RCAR_GP_PIN(6, 10),
3686 };
3687 static const unsigned int ssi4_data_mux[] = {
3688 SSI_SDATA4_MARK,
3689 };
3690 static const unsigned int ssi4_ctrl_pins[] = {
3691 /* SCK, WS */
3692 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3693 };
3694 static const unsigned int ssi4_ctrl_mux[] = {
3695 SSI_SCK4_MARK, SSI_WS4_MARK,
3696 };
3697 static const unsigned int ssi5_data_pins[] = {
3698 /* SDATA */
3699 RCAR_GP_PIN(6, 13),
3700 };
3701 static const unsigned int ssi5_data_mux[] = {
3702 SSI_SDATA5_MARK,
3703 };
3704 static const unsigned int ssi5_ctrl_pins[] = {
3705 /* SCK, WS */
3706 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3707 };
3708 static const unsigned int ssi5_ctrl_mux[] = {
3709 SSI_SCK5_MARK, SSI_WS5_MARK,
3710 };
3711 static const unsigned int ssi6_data_pins[] = {
3712 /* SDATA */
3713 RCAR_GP_PIN(6, 16),
3714 };
3715 static const unsigned int ssi6_data_mux[] = {
3716 SSI_SDATA6_MARK,
3717 };
3718 static const unsigned int ssi6_ctrl_pins[] = {
3719 /* SCK, WS */
3720 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3721 };
3722 static const unsigned int ssi6_ctrl_mux[] = {
3723 SSI_SCK6_MARK, SSI_WS6_MARK,
3724 };
3725 static const unsigned int ssi7_data_pins[] = {
3726 /* SDATA */
3727 RCAR_GP_PIN(6, 19),
3728 };
3729 static const unsigned int ssi7_data_mux[] = {
3730 SSI_SDATA7_MARK,
3731 };
3732 static const unsigned int ssi78_ctrl_pins[] = {
3733 /* SCK, WS */
3734 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3735 };
3736 static const unsigned int ssi78_ctrl_mux[] = {
3737 SSI_SCK78_MARK, SSI_WS78_MARK,
3738 };
3739 static const unsigned int ssi8_data_pins[] = {
3740 /* SDATA */
3741 RCAR_GP_PIN(6, 20),
3742 };
3743 static const unsigned int ssi8_data_mux[] = {
3744 SSI_SDATA8_MARK,
3745 };
3746 static const unsigned int ssi9_data_a_pins[] = {
3747 /* SDATA */
3748 RCAR_GP_PIN(6, 21),
3749 };
3750 static const unsigned int ssi9_data_a_mux[] = {
3751 SSI_SDATA9_A_MARK,
3752 };
3753 static const unsigned int ssi9_data_b_pins[] = {
3754 /* SDATA */
3755 RCAR_GP_PIN(5, 14),
3756 };
3757 static const unsigned int ssi9_data_b_mux[] = {
3758 SSI_SDATA9_B_MARK,
3759 };
3760 static const unsigned int ssi9_ctrl_a_pins[] = {
3761 /* SCK, WS */
3762 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3763 };
3764 static const unsigned int ssi9_ctrl_a_mux[] = {
3765 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3766 };
3767 static const unsigned int ssi9_ctrl_b_pins[] = {
3768 /* SCK, WS */
3769 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3770 };
3771 static const unsigned int ssi9_ctrl_b_mux[] = {
3772 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3773 };
3774
3775 /* - TMU -------------------------------------------------------------------- */
3776 static const unsigned int tmu_tclk1_a_pins[] = {
3777 /* TCLK */
3778 RCAR_GP_PIN(6, 23),
3779 };
3780 static const unsigned int tmu_tclk1_a_mux[] = {
3781 TCLK1_A_MARK,
3782 };
3783 static const unsigned int tmu_tclk1_b_pins[] = {
3784 /* TCLK */
3785 RCAR_GP_PIN(5, 19),
3786 };
3787 static const unsigned int tmu_tclk1_b_mux[] = {
3788 TCLK1_B_MARK,
3789 };
3790 static const unsigned int tmu_tclk2_a_pins[] = {
3791 /* TCLK */
3792 RCAR_GP_PIN(6, 19),
3793 };
3794 static const unsigned int tmu_tclk2_a_mux[] = {
3795 TCLK2_A_MARK,
3796 };
3797 static const unsigned int tmu_tclk2_b_pins[] = {
3798 /* TCLK */
3799 RCAR_GP_PIN(6, 28),
3800 };
3801 static const unsigned int tmu_tclk2_b_mux[] = {
3802 TCLK2_B_MARK,
3803 };
3804
3805 /* - TPU ------------------------------------------------------------------- */
3806 static const unsigned int tpu_to0_pins[] = {
3807 /* TPU0TO0 */
3808 RCAR_GP_PIN(6, 28),
3809 };
3810 static const unsigned int tpu_to0_mux[] = {
3811 TPU0TO0_MARK,
3812 };
3813 static const unsigned int tpu_to1_pins[] = {
3814 /* TPU0TO1 */
3815 RCAR_GP_PIN(6, 29),
3816 };
3817 static const unsigned int tpu_to1_mux[] = {
3818 TPU0TO1_MARK,
3819 };
3820 static const unsigned int tpu_to2_pins[] = {
3821 /* TPU0TO2 */
3822 RCAR_GP_PIN(6, 30),
3823 };
3824 static const unsigned int tpu_to2_mux[] = {
3825 TPU0TO2_MARK,
3826 };
3827 static const unsigned int tpu_to3_pins[] = {
3828 /* TPU0TO3 */
3829 RCAR_GP_PIN(6, 31),
3830 };
3831 static const unsigned int tpu_to3_mux[] = {
3832 TPU0TO3_MARK,
3833 };
3834
3835 /* - USB0 ------------------------------------------------------------------- */
3836 static const unsigned int usb0_pins[] = {
3837 /* PWEN, OVC */
3838 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3839 };
3840 static const unsigned int usb0_mux[] = {
3841 USB0_PWEN_MARK, USB0_OVC_MARK,
3842 };
3843 /* - USB1 ------------------------------------------------------------------- */
3844 static const unsigned int usb1_pins[] = {
3845 /* PWEN, OVC */
3846 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3847 };
3848 static const unsigned int usb1_mux[] = {
3849 USB1_PWEN_MARK, USB1_OVC_MARK,
3850 };
3851 /* - USB2 ------------------------------------------------------------------- */
3852 static const unsigned int usb2_pins[] = {
3853 /* PWEN, OVC */
3854 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3855 };
3856 static const unsigned int usb2_mux[] = {
3857 USB2_PWEN_MARK, USB2_OVC_MARK,
3858 };
3859
3860 /* - USB30 ------------------------------------------------------------------ */
3861 static const unsigned int usb30_pins[] = {
3862 /* PWEN, OVC */
3863 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3864 };
3865 static const unsigned int usb30_mux[] = {
3866 USB30_PWEN_MARK, USB30_OVC_MARK,
3867 };
3868 /* - USB31 ------------------------------------------------------------------ */
3869 static const unsigned int usb31_pins[] = {
3870 /* PWEN, OVC */
3871 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3872 };
3873 static const unsigned int usb31_mux[] = {
3874 USB31_PWEN_MARK, USB31_OVC_MARK,
3875 };
3876
3877 static const struct sh_pfc_pin_group pinmux_groups[] = {
3878 SH_PFC_PIN_GROUP(audio_clk_a_a),
3879 SH_PFC_PIN_GROUP(audio_clk_a_b),
3880 SH_PFC_PIN_GROUP(audio_clk_a_c),
3881 SH_PFC_PIN_GROUP(audio_clk_b_a),
3882 SH_PFC_PIN_GROUP(audio_clk_b_b),
3883 SH_PFC_PIN_GROUP(audio_clk_c_a),
3884 SH_PFC_PIN_GROUP(audio_clk_c_b),
3885 SH_PFC_PIN_GROUP(audio_clkout_a),
3886 SH_PFC_PIN_GROUP(audio_clkout_b),
3887 SH_PFC_PIN_GROUP(audio_clkout_c),
3888 SH_PFC_PIN_GROUP(audio_clkout_d),
3889 SH_PFC_PIN_GROUP(audio_clkout1_a),
3890 SH_PFC_PIN_GROUP(audio_clkout1_b),
3891 SH_PFC_PIN_GROUP(audio_clkout2_a),
3892 SH_PFC_PIN_GROUP(audio_clkout2_b),
3893 SH_PFC_PIN_GROUP(audio_clkout3_a),
3894 SH_PFC_PIN_GROUP(audio_clkout3_b),
3895 SH_PFC_PIN_GROUP(avb_link),
3896 SH_PFC_PIN_GROUP(avb_magic),
3897 SH_PFC_PIN_GROUP(avb_phy_int),
3898 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
3899 SH_PFC_PIN_GROUP(avb_mdio),
3900 SH_PFC_PIN_GROUP(avb_mii),
3901 SH_PFC_PIN_GROUP(avb_avtp_pps),
3902 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3903 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3904 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3905 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3906 SH_PFC_PIN_GROUP(can0_data_a),
3907 SH_PFC_PIN_GROUP(can0_data_b),
3908 SH_PFC_PIN_GROUP(can1_data),
3909 SH_PFC_PIN_GROUP(can_clk),
3910 SH_PFC_PIN_GROUP(canfd0_data_a),
3911 SH_PFC_PIN_GROUP(canfd0_data_b),
3912 SH_PFC_PIN_GROUP(canfd1_data),
3913 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3914 SH_PFC_PIN_GROUP(drif0_data0_a),
3915 SH_PFC_PIN_GROUP(drif0_data1_a),
3916 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3917 SH_PFC_PIN_GROUP(drif0_data0_b),
3918 SH_PFC_PIN_GROUP(drif0_data1_b),
3919 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3920 SH_PFC_PIN_GROUP(drif0_data0_c),
3921 SH_PFC_PIN_GROUP(drif0_data1_c),
3922 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3923 SH_PFC_PIN_GROUP(drif1_data0_a),
3924 SH_PFC_PIN_GROUP(drif1_data1_a),
3925 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3926 SH_PFC_PIN_GROUP(drif1_data0_b),
3927 SH_PFC_PIN_GROUP(drif1_data1_b),
3928 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3929 SH_PFC_PIN_GROUP(drif1_data0_c),
3930 SH_PFC_PIN_GROUP(drif1_data1_c),
3931 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3932 SH_PFC_PIN_GROUP(drif2_data0_a),
3933 SH_PFC_PIN_GROUP(drif2_data1_a),
3934 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3935 SH_PFC_PIN_GROUP(drif2_data0_b),
3936 SH_PFC_PIN_GROUP(drif2_data1_b),
3937 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3938 SH_PFC_PIN_GROUP(drif3_data0_a),
3939 SH_PFC_PIN_GROUP(drif3_data1_a),
3940 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3941 SH_PFC_PIN_GROUP(drif3_data0_b),
3942 SH_PFC_PIN_GROUP(drif3_data1_b),
3943 SH_PFC_PIN_GROUP(du_rgb666),
3944 SH_PFC_PIN_GROUP(du_rgb888),
3945 SH_PFC_PIN_GROUP(du_clk_out_0),
3946 SH_PFC_PIN_GROUP(du_clk_out_1),
3947 SH_PFC_PIN_GROUP(du_sync),
3948 SH_PFC_PIN_GROUP(du_oddf),
3949 SH_PFC_PIN_GROUP(du_cde),
3950 SH_PFC_PIN_GROUP(du_disp),
3951 SH_PFC_PIN_GROUP(hscif0_data),
3952 SH_PFC_PIN_GROUP(hscif0_clk),
3953 SH_PFC_PIN_GROUP(hscif0_ctrl),
3954 SH_PFC_PIN_GROUP(hscif1_data_a),
3955 SH_PFC_PIN_GROUP(hscif1_clk_a),
3956 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3957 SH_PFC_PIN_GROUP(hscif1_data_b),
3958 SH_PFC_PIN_GROUP(hscif1_clk_b),
3959 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3960 SH_PFC_PIN_GROUP(hscif2_data_a),
3961 SH_PFC_PIN_GROUP(hscif2_clk_a),
3962 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3963 SH_PFC_PIN_GROUP(hscif2_data_b),
3964 SH_PFC_PIN_GROUP(hscif2_clk_b),
3965 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3966 SH_PFC_PIN_GROUP(hscif3_data_a),
3967 SH_PFC_PIN_GROUP(hscif3_clk),
3968 SH_PFC_PIN_GROUP(hscif3_ctrl),
3969 SH_PFC_PIN_GROUP(hscif3_data_b),
3970 SH_PFC_PIN_GROUP(hscif3_data_c),
3971 SH_PFC_PIN_GROUP(hscif3_data_d),
3972 SH_PFC_PIN_GROUP(hscif4_data_a),
3973 SH_PFC_PIN_GROUP(hscif4_clk),
3974 SH_PFC_PIN_GROUP(hscif4_ctrl),
3975 SH_PFC_PIN_GROUP(hscif4_data_b),
3976 SH_PFC_PIN_GROUP(i2c0),
3977 SH_PFC_PIN_GROUP(i2c1_a),
3978 SH_PFC_PIN_GROUP(i2c1_b),
3979 SH_PFC_PIN_GROUP(i2c2_a),
3980 SH_PFC_PIN_GROUP(i2c2_b),
3981 SH_PFC_PIN_GROUP(i2c3),
3982 SH_PFC_PIN_GROUP(i2c5),
3983 SH_PFC_PIN_GROUP(i2c6_a),
3984 SH_PFC_PIN_GROUP(i2c6_b),
3985 SH_PFC_PIN_GROUP(i2c6_c),
3986 SH_PFC_PIN_GROUP(intc_ex_irq0),
3987 SH_PFC_PIN_GROUP(intc_ex_irq1),
3988 SH_PFC_PIN_GROUP(intc_ex_irq2),
3989 SH_PFC_PIN_GROUP(intc_ex_irq3),
3990 SH_PFC_PIN_GROUP(intc_ex_irq4),
3991 SH_PFC_PIN_GROUP(intc_ex_irq5),
3992 SH_PFC_PIN_GROUP(msiof0_clk),
3993 SH_PFC_PIN_GROUP(msiof0_sync),
3994 SH_PFC_PIN_GROUP(msiof0_ss1),
3995 SH_PFC_PIN_GROUP(msiof0_ss2),
3996 SH_PFC_PIN_GROUP(msiof0_txd),
3997 SH_PFC_PIN_GROUP(msiof0_rxd),
3998 SH_PFC_PIN_GROUP(msiof1_clk_a),
3999 SH_PFC_PIN_GROUP(msiof1_sync_a),
4000 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4001 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4002 SH_PFC_PIN_GROUP(msiof1_txd_a),
4003 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4004 SH_PFC_PIN_GROUP(msiof1_clk_b),
4005 SH_PFC_PIN_GROUP(msiof1_sync_b),
4006 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4007 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4008 SH_PFC_PIN_GROUP(msiof1_txd_b),
4009 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4010 SH_PFC_PIN_GROUP(msiof1_clk_c),
4011 SH_PFC_PIN_GROUP(msiof1_sync_c),
4012 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4013 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4014 SH_PFC_PIN_GROUP(msiof1_txd_c),
4015 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4016 SH_PFC_PIN_GROUP(msiof1_clk_d),
4017 SH_PFC_PIN_GROUP(msiof1_sync_d),
4018 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4019 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4020 SH_PFC_PIN_GROUP(msiof1_txd_d),
4021 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4022 SH_PFC_PIN_GROUP(msiof1_clk_e),
4023 SH_PFC_PIN_GROUP(msiof1_sync_e),
4024 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4025 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4026 SH_PFC_PIN_GROUP(msiof1_txd_e),
4027 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4028 SH_PFC_PIN_GROUP(msiof1_clk_f),
4029 SH_PFC_PIN_GROUP(msiof1_sync_f),
4030 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4031 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4032 SH_PFC_PIN_GROUP(msiof1_txd_f),
4033 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4034 SH_PFC_PIN_GROUP(msiof1_clk_g),
4035 SH_PFC_PIN_GROUP(msiof1_sync_g),
4036 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4037 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4038 SH_PFC_PIN_GROUP(msiof1_txd_g),
4039 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4040 SH_PFC_PIN_GROUP(msiof2_clk_a),
4041 SH_PFC_PIN_GROUP(msiof2_sync_a),
4042 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4043 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4044 SH_PFC_PIN_GROUP(msiof2_txd_a),
4045 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4046 SH_PFC_PIN_GROUP(msiof2_clk_b),
4047 SH_PFC_PIN_GROUP(msiof2_sync_b),
4048 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4049 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4050 SH_PFC_PIN_GROUP(msiof2_txd_b),
4051 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4052 SH_PFC_PIN_GROUP(msiof2_clk_c),
4053 SH_PFC_PIN_GROUP(msiof2_sync_c),
4054 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4055 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4056 SH_PFC_PIN_GROUP(msiof2_txd_c),
4057 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4058 SH_PFC_PIN_GROUP(msiof2_clk_d),
4059 SH_PFC_PIN_GROUP(msiof2_sync_d),
4060 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4061 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4062 SH_PFC_PIN_GROUP(msiof2_txd_d),
4063 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4064 SH_PFC_PIN_GROUP(msiof3_clk_a),
4065 SH_PFC_PIN_GROUP(msiof3_sync_a),
4066 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4067 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4068 SH_PFC_PIN_GROUP(msiof3_txd_a),
4069 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4070 SH_PFC_PIN_GROUP(msiof3_clk_b),
4071 SH_PFC_PIN_GROUP(msiof3_sync_b),
4072 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4073 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4074 SH_PFC_PIN_GROUP(msiof3_txd_b),
4075 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4076 SH_PFC_PIN_GROUP(msiof3_clk_c),
4077 SH_PFC_PIN_GROUP(msiof3_sync_c),
4078 SH_PFC_PIN_GROUP(msiof3_txd_c),
4079 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4080 SH_PFC_PIN_GROUP(msiof3_clk_d),
4081 SH_PFC_PIN_GROUP(msiof3_sync_d),
4082 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4083 SH_PFC_PIN_GROUP(msiof3_txd_d),
4084 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4085 SH_PFC_PIN_GROUP(pwm0),
4086 SH_PFC_PIN_GROUP(pwm1_a),
4087 SH_PFC_PIN_GROUP(pwm1_b),
4088 SH_PFC_PIN_GROUP(pwm2_a),
4089 SH_PFC_PIN_GROUP(pwm2_b),
4090 SH_PFC_PIN_GROUP(pwm3_a),
4091 SH_PFC_PIN_GROUP(pwm3_b),
4092 SH_PFC_PIN_GROUP(pwm4_a),
4093 SH_PFC_PIN_GROUP(pwm4_b),
4094 SH_PFC_PIN_GROUP(pwm5_a),
4095 SH_PFC_PIN_GROUP(pwm5_b),
4096 SH_PFC_PIN_GROUP(pwm6_a),
4097 SH_PFC_PIN_GROUP(pwm6_b),
4098 SH_PFC_PIN_GROUP(qspi0_ctrl),
4099 SH_PFC_PIN_GROUP(qspi0_data2),
4100 SH_PFC_PIN_GROUP(qspi0_data4),
4101 SH_PFC_PIN_GROUP(qspi1_ctrl),
4102 SH_PFC_PIN_GROUP(qspi1_data2),
4103 SH_PFC_PIN_GROUP(qspi1_data4),
4104 SH_PFC_PIN_GROUP(sata0_devslp_a),
4105 SH_PFC_PIN_GROUP(sata0_devslp_b),
4106 SH_PFC_PIN_GROUP(scif0_data),
4107 SH_PFC_PIN_GROUP(scif0_clk),
4108 SH_PFC_PIN_GROUP(scif0_ctrl),
4109 SH_PFC_PIN_GROUP(scif1_data_a),
4110 SH_PFC_PIN_GROUP(scif1_clk),
4111 SH_PFC_PIN_GROUP(scif1_ctrl),
4112 SH_PFC_PIN_GROUP(scif1_data_b),
4113 SH_PFC_PIN_GROUP(scif2_data_a),
4114 SH_PFC_PIN_GROUP(scif2_clk),
4115 SH_PFC_PIN_GROUP(scif2_data_b),
4116 SH_PFC_PIN_GROUP(scif3_data_a),
4117 SH_PFC_PIN_GROUP(scif3_clk),
4118 SH_PFC_PIN_GROUP(scif3_ctrl),
4119 SH_PFC_PIN_GROUP(scif3_data_b),
4120 SH_PFC_PIN_GROUP(scif4_data_a),
4121 SH_PFC_PIN_GROUP(scif4_clk_a),
4122 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4123 SH_PFC_PIN_GROUP(scif4_data_b),
4124 SH_PFC_PIN_GROUP(scif4_clk_b),
4125 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4126 SH_PFC_PIN_GROUP(scif4_data_c),
4127 SH_PFC_PIN_GROUP(scif4_clk_c),
4128 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4129 SH_PFC_PIN_GROUP(scif5_data),
4130 SH_PFC_PIN_GROUP(scif5_clk),
4131 SH_PFC_PIN_GROUP(scif_clk_a),
4132 SH_PFC_PIN_GROUP(scif_clk_b),
4133 SH_PFC_PIN_GROUP(sdhi0_data1),
4134 SH_PFC_PIN_GROUP(sdhi0_data4),
4135 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4136 SH_PFC_PIN_GROUP(sdhi0_cd),
4137 SH_PFC_PIN_GROUP(sdhi0_wp),
4138 SH_PFC_PIN_GROUP(sdhi1_data1),
4139 SH_PFC_PIN_GROUP(sdhi1_data4),
4140 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4141 SH_PFC_PIN_GROUP(sdhi1_cd),
4142 SH_PFC_PIN_GROUP(sdhi1_wp),
4143 SH_PFC_PIN_GROUP(sdhi2_data1),
4144 SH_PFC_PIN_GROUP(sdhi2_data4),
4145 SH_PFC_PIN_GROUP(sdhi2_data8),
4146 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4147 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4148 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4149 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4150 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4151 SH_PFC_PIN_GROUP(sdhi2_ds),
4152 SH_PFC_PIN_GROUP(sdhi3_data1),
4153 SH_PFC_PIN_GROUP(sdhi3_data4),
4154 SH_PFC_PIN_GROUP(sdhi3_data8),
4155 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4156 SH_PFC_PIN_GROUP(sdhi3_cd),
4157 SH_PFC_PIN_GROUP(sdhi3_wp),
4158 SH_PFC_PIN_GROUP(sdhi3_ds),
4159 SH_PFC_PIN_GROUP(ssi0_data),
4160 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4161 SH_PFC_PIN_GROUP(ssi1_data_a),
4162 SH_PFC_PIN_GROUP(ssi1_data_b),
4163 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4164 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4165 SH_PFC_PIN_GROUP(ssi2_data_a),
4166 SH_PFC_PIN_GROUP(ssi2_data_b),
4167 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4168 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4169 SH_PFC_PIN_GROUP(ssi3_data),
4170 SH_PFC_PIN_GROUP(ssi349_ctrl),
4171 SH_PFC_PIN_GROUP(ssi4_data),
4172 SH_PFC_PIN_GROUP(ssi4_ctrl),
4173 SH_PFC_PIN_GROUP(ssi5_data),
4174 SH_PFC_PIN_GROUP(ssi5_ctrl),
4175 SH_PFC_PIN_GROUP(ssi6_data),
4176 SH_PFC_PIN_GROUP(ssi6_ctrl),
4177 SH_PFC_PIN_GROUP(ssi7_data),
4178 SH_PFC_PIN_GROUP(ssi78_ctrl),
4179 SH_PFC_PIN_GROUP(ssi8_data),
4180 SH_PFC_PIN_GROUP(ssi9_data_a),
4181 SH_PFC_PIN_GROUP(ssi9_data_b),
4182 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4183 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4184 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4185 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4186 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4187 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4188 SH_PFC_PIN_GROUP(tpu_to0),
4189 SH_PFC_PIN_GROUP(tpu_to1),
4190 SH_PFC_PIN_GROUP(tpu_to2),
4191 SH_PFC_PIN_GROUP(tpu_to3),
4192 SH_PFC_PIN_GROUP(usb0),
4193 SH_PFC_PIN_GROUP(usb1),
4194 SH_PFC_PIN_GROUP(usb2),
4195 SH_PFC_PIN_GROUP(usb30),
4196 SH_PFC_PIN_GROUP(usb31),
4197 };
4198
4199 static const char * const audio_clk_groups[] = {
4200 "audio_clk_a_a",
4201 "audio_clk_a_b",
4202 "audio_clk_a_c",
4203 "audio_clk_b_a",
4204 "audio_clk_b_b",
4205 "audio_clk_c_a",
4206 "audio_clk_c_b",
4207 "audio_clkout_a",
4208 "audio_clkout_b",
4209 "audio_clkout_c",
4210 "audio_clkout_d",
4211 "audio_clkout1_a",
4212 "audio_clkout1_b",
4213 "audio_clkout2_a",
4214 "audio_clkout2_b",
4215 "audio_clkout3_a",
4216 "audio_clkout3_b",
4217 };
4218
4219 static const char * const avb_groups[] = {
4220 "avb_link",
4221 "avb_magic",
4222 "avb_phy_int",
4223 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4224 "avb_mdio",
4225 "avb_mii",
4226 "avb_avtp_pps",
4227 "avb_avtp_match_a",
4228 "avb_avtp_capture_a",
4229 "avb_avtp_match_b",
4230 "avb_avtp_capture_b",
4231 };
4232
4233 static const char * const can0_groups[] = {
4234 "can0_data_a",
4235 "can0_data_b",
4236 };
4237
4238 static const char * const can1_groups[] = {
4239 "can1_data",
4240 };
4241
4242 static const char * const can_clk_groups[] = {
4243 "can_clk",
4244 };
4245
4246 static const char * const canfd0_groups[] = {
4247 "canfd0_data_a",
4248 "canfd0_data_b",
4249 };
4250
4251 static const char * const canfd1_groups[] = {
4252 "canfd1_data",
4253 };
4254
4255 static const char * const drif0_groups[] = {
4256 "drif0_ctrl_a",
4257 "drif0_data0_a",
4258 "drif0_data1_a",
4259 "drif0_ctrl_b",
4260 "drif0_data0_b",
4261 "drif0_data1_b",
4262 "drif0_ctrl_c",
4263 "drif0_data0_c",
4264 "drif0_data1_c",
4265 };
4266
4267 static const char * const drif1_groups[] = {
4268 "drif1_ctrl_a",
4269 "drif1_data0_a",
4270 "drif1_data1_a",
4271 "drif1_ctrl_b",
4272 "drif1_data0_b",
4273 "drif1_data1_b",
4274 "drif1_ctrl_c",
4275 "drif1_data0_c",
4276 "drif1_data1_c",
4277 };
4278
4279 static const char * const drif2_groups[] = {
4280 "drif2_ctrl_a",
4281 "drif2_data0_a",
4282 "drif2_data1_a",
4283 "drif2_ctrl_b",
4284 "drif2_data0_b",
4285 "drif2_data1_b",
4286 };
4287
4288 static const char * const drif3_groups[] = {
4289 "drif3_ctrl_a",
4290 "drif3_data0_a",
4291 "drif3_data1_a",
4292 "drif3_ctrl_b",
4293 "drif3_data0_b",
4294 "drif3_data1_b",
4295 };
4296
4297 static const char * const du_groups[] = {
4298 "du_rgb666",
4299 "du_rgb888",
4300 "du_clk_out_0",
4301 "du_clk_out_1",
4302 "du_sync",
4303 "du_oddf",
4304 "du_cde",
4305 "du_disp",
4306 };
4307
4308 static const char * const hscif0_groups[] = {
4309 "hscif0_data",
4310 "hscif0_clk",
4311 "hscif0_ctrl",
4312 };
4313
4314 static const char * const hscif1_groups[] = {
4315 "hscif1_data_a",
4316 "hscif1_clk_a",
4317 "hscif1_ctrl_a",
4318 "hscif1_data_b",
4319 "hscif1_clk_b",
4320 "hscif1_ctrl_b",
4321 };
4322
4323 static const char * const hscif2_groups[] = {
4324 "hscif2_data_a",
4325 "hscif2_clk_a",
4326 "hscif2_ctrl_a",
4327 "hscif2_data_b",
4328 "hscif2_clk_b",
4329 "hscif2_ctrl_b",
4330 };
4331
4332 static const char * const hscif3_groups[] = {
4333 "hscif3_data_a",
4334 "hscif3_clk",
4335 "hscif3_ctrl",
4336 "hscif3_data_b",
4337 "hscif3_data_c",
4338 "hscif3_data_d",
4339 };
4340
4341 static const char * const hscif4_groups[] = {
4342 "hscif4_data_a",
4343 "hscif4_clk",
4344 "hscif4_ctrl",
4345 "hscif4_data_b",
4346 };
4347
4348 static const char * const i2c0_groups[] = {
4349 "i2c0",
4350 };
4351
4352 static const char * const i2c1_groups[] = {
4353 "i2c1_a",
4354 "i2c1_b",
4355 };
4356
4357 static const char * const i2c2_groups[] = {
4358 "i2c2_a",
4359 "i2c2_b",
4360 };
4361
4362 static const char * const i2c3_groups[] = {
4363 "i2c3",
4364 };
4365
4366 static const char * const i2c5_groups[] = {
4367 "i2c5",
4368 };
4369
4370 static const char * const i2c6_groups[] = {
4371 "i2c6_a",
4372 "i2c6_b",
4373 "i2c6_c",
4374 };
4375
4376 static const char * const intc_ex_groups[] = {
4377 "intc_ex_irq0",
4378 "intc_ex_irq1",
4379 "intc_ex_irq2",
4380 "intc_ex_irq3",
4381 "intc_ex_irq4",
4382 "intc_ex_irq5",
4383 };
4384
4385 static const char * const msiof0_groups[] = {
4386 "msiof0_clk",
4387 "msiof0_sync",
4388 "msiof0_ss1",
4389 "msiof0_ss2",
4390 "msiof0_txd",
4391 "msiof0_rxd",
4392 };
4393
4394 static const char * const msiof1_groups[] = {
4395 "msiof1_clk_a",
4396 "msiof1_sync_a",
4397 "msiof1_ss1_a",
4398 "msiof1_ss2_a",
4399 "msiof1_txd_a",
4400 "msiof1_rxd_a",
4401 "msiof1_clk_b",
4402 "msiof1_sync_b",
4403 "msiof1_ss1_b",
4404 "msiof1_ss2_b",
4405 "msiof1_txd_b",
4406 "msiof1_rxd_b",
4407 "msiof1_clk_c",
4408 "msiof1_sync_c",
4409 "msiof1_ss1_c",
4410 "msiof1_ss2_c",
4411 "msiof1_txd_c",
4412 "msiof1_rxd_c",
4413 "msiof1_clk_d",
4414 "msiof1_sync_d",
4415 "msiof1_ss1_d",
4416 "msiof1_ss2_d",
4417 "msiof1_txd_d",
4418 "msiof1_rxd_d",
4419 "msiof1_clk_e",
4420 "msiof1_sync_e",
4421 "msiof1_ss1_e",
4422 "msiof1_ss2_e",
4423 "msiof1_txd_e",
4424 "msiof1_rxd_e",
4425 "msiof1_clk_f",
4426 "msiof1_sync_f",
4427 "msiof1_ss1_f",
4428 "msiof1_ss2_f",
4429 "msiof1_txd_f",
4430 "msiof1_rxd_f",
4431 "msiof1_clk_g",
4432 "msiof1_sync_g",
4433 "msiof1_ss1_g",
4434 "msiof1_ss2_g",
4435 "msiof1_txd_g",
4436 "msiof1_rxd_g",
4437 };
4438
4439 static const char * const msiof2_groups[] = {
4440 "msiof2_clk_a",
4441 "msiof2_sync_a",
4442 "msiof2_ss1_a",
4443 "msiof2_ss2_a",
4444 "msiof2_txd_a",
4445 "msiof2_rxd_a",
4446 "msiof2_clk_b",
4447 "msiof2_sync_b",
4448 "msiof2_ss1_b",
4449 "msiof2_ss2_b",
4450 "msiof2_txd_b",
4451 "msiof2_rxd_b",
4452 "msiof2_clk_c",
4453 "msiof2_sync_c",
4454 "msiof2_ss1_c",
4455 "msiof2_ss2_c",
4456 "msiof2_txd_c",
4457 "msiof2_rxd_c",
4458 "msiof2_clk_d",
4459 "msiof2_sync_d",
4460 "msiof2_ss1_d",
4461 "msiof2_ss2_d",
4462 "msiof2_txd_d",
4463 "msiof2_rxd_d",
4464 };
4465
4466 static const char * const msiof3_groups[] = {
4467 "msiof3_clk_a",
4468 "msiof3_sync_a",
4469 "msiof3_ss1_a",
4470 "msiof3_ss2_a",
4471 "msiof3_txd_a",
4472 "msiof3_rxd_a",
4473 "msiof3_clk_b",
4474 "msiof3_sync_b",
4475 "msiof3_ss1_b",
4476 "msiof3_ss2_b",
4477 "msiof3_txd_b",
4478 "msiof3_rxd_b",
4479 "msiof3_clk_c",
4480 "msiof3_sync_c",
4481 "msiof3_txd_c",
4482 "msiof3_rxd_c",
4483 "msiof3_clk_d",
4484 "msiof3_sync_d",
4485 "msiof3_ss1_d",
4486 "msiof3_txd_d",
4487 "msiof3_rxd_d",
4488 };
4489
4490 static const char * const pwm0_groups[] = {
4491 "pwm0",
4492 };
4493
4494 static const char * const pwm1_groups[] = {
4495 "pwm1_a",
4496 "pwm1_b",
4497 };
4498
4499 static const char * const pwm2_groups[] = {
4500 "pwm2_a",
4501 "pwm2_b",
4502 };
4503
4504 static const char * const pwm3_groups[] = {
4505 "pwm3_a",
4506 "pwm3_b",
4507 };
4508
4509 static const char * const pwm4_groups[] = {
4510 "pwm4_a",
4511 "pwm4_b",
4512 };
4513
4514 static const char * const pwm5_groups[] = {
4515 "pwm5_a",
4516 "pwm5_b",
4517 };
4518
4519 static const char * const pwm6_groups[] = {
4520 "pwm6_a",
4521 "pwm6_b",
4522 };
4523
4524 static const char * const qspi0_groups[] = {
4525 "qspi0_ctrl",
4526 "qspi0_data2",
4527 "qspi0_data4",
4528 };
4529
4530 static const char * const qspi1_groups[] = {
4531 "qspi1_ctrl",
4532 "qspi1_data2",
4533 "qspi1_data4",
4534 };
4535
4536 static const char * const sata0_groups[] = {
4537 "sata0_devslp_a",
4538 "sata0_devslp_b",
4539 };
4540
4541 static const char * const scif0_groups[] = {
4542 "scif0_data",
4543 "scif0_clk",
4544 "scif0_ctrl",
4545 };
4546
4547 static const char * const scif1_groups[] = {
4548 "scif1_data_a",
4549 "scif1_clk",
4550 "scif1_ctrl",
4551 "scif1_data_b",
4552 };
4553
4554 static const char * const scif2_groups[] = {
4555 "scif2_data_a",
4556 "scif2_clk",
4557 "scif2_data_b",
4558 };
4559
4560 static const char * const scif3_groups[] = {
4561 "scif3_data_a",
4562 "scif3_clk",
4563 "scif3_ctrl",
4564 "scif3_data_b",
4565 };
4566
4567 static const char * const scif4_groups[] = {
4568 "scif4_data_a",
4569 "scif4_clk_a",
4570 "scif4_ctrl_a",
4571 "scif4_data_b",
4572 "scif4_clk_b",
4573 "scif4_ctrl_b",
4574 "scif4_data_c",
4575 "scif4_clk_c",
4576 "scif4_ctrl_c",
4577 };
4578
4579 static const char * const scif5_groups[] = {
4580 "scif5_data",
4581 "scif5_clk",
4582 };
4583
4584 static const char * const scif_clk_groups[] = {
4585 "scif_clk_a",
4586 "scif_clk_b",
4587 };
4588
4589 static const char * const sdhi0_groups[] = {
4590 "sdhi0_data1",
4591 "sdhi0_data4",
4592 "sdhi0_ctrl",
4593 "sdhi0_cd",
4594 "sdhi0_wp",
4595 };
4596
4597 static const char * const sdhi1_groups[] = {
4598 "sdhi1_data1",
4599 "sdhi1_data4",
4600 "sdhi1_ctrl",
4601 "sdhi1_cd",
4602 "sdhi1_wp",
4603 };
4604
4605 static const char * const sdhi2_groups[] = {
4606 "sdhi2_data1",
4607 "sdhi2_data4",
4608 "sdhi2_data8",
4609 "sdhi2_ctrl",
4610 "sdhi2_cd_a",
4611 "sdhi2_wp_a",
4612 "sdhi2_cd_b",
4613 "sdhi2_wp_b",
4614 "sdhi2_ds",
4615 };
4616
4617 static const char * const sdhi3_groups[] = {
4618 "sdhi3_data1",
4619 "sdhi3_data4",
4620 "sdhi3_data8",
4621 "sdhi3_ctrl",
4622 "sdhi3_cd",
4623 "sdhi3_wp",
4624 "sdhi3_ds",
4625 };
4626
4627 static const char * const ssi_groups[] = {
4628 "ssi0_data",
4629 "ssi01239_ctrl",
4630 "ssi1_data_a",
4631 "ssi1_data_b",
4632 "ssi1_ctrl_a",
4633 "ssi1_ctrl_b",
4634 "ssi2_data_a",
4635 "ssi2_data_b",
4636 "ssi2_ctrl_a",
4637 "ssi2_ctrl_b",
4638 "ssi3_data",
4639 "ssi349_ctrl",
4640 "ssi4_data",
4641 "ssi4_ctrl",
4642 "ssi5_data",
4643 "ssi5_ctrl",
4644 "ssi6_data",
4645 "ssi6_ctrl",
4646 "ssi7_data",
4647 "ssi78_ctrl",
4648 "ssi8_data",
4649 "ssi9_data_a",
4650 "ssi9_data_b",
4651 "ssi9_ctrl_a",
4652 "ssi9_ctrl_b",
4653 };
4654
4655 static const char * const tmu_groups[] = {
4656 "tmu_tclk1_a",
4657 "tmu_tclk1_b",
4658 "tmu_tclk2_a",
4659 "tmu_tclk2_b",
4660 };
4661
4662 static const char * const tpu_groups[] = {
4663 "tpu_to0",
4664 "tpu_to1",
4665 "tpu_to2",
4666 "tpu_to3",
4667 };
4668
4669 static const char * const usb0_groups[] = {
4670 "usb0",
4671 };
4672
4673 static const char * const usb1_groups[] = {
4674 "usb1",
4675 };
4676
4677 static const char * const usb2_groups[] = {
4678 "usb2",
4679 };
4680
4681 static const char * const usb30_groups[] = {
4682 "usb30",
4683 };
4684
4685 static const char * const usb31_groups[] = {
4686 "usb31",
4687 };
4688
4689 static const struct sh_pfc_function pinmux_functions[] = {
4690 SH_PFC_FUNCTION(audio_clk),
4691 SH_PFC_FUNCTION(avb),
4692 SH_PFC_FUNCTION(can0),
4693 SH_PFC_FUNCTION(can1),
4694 SH_PFC_FUNCTION(can_clk),
4695 SH_PFC_FUNCTION(canfd0),
4696 SH_PFC_FUNCTION(canfd1),
4697 SH_PFC_FUNCTION(drif0),
4698 SH_PFC_FUNCTION(drif1),
4699 SH_PFC_FUNCTION(drif2),
4700 SH_PFC_FUNCTION(drif3),
4701 SH_PFC_FUNCTION(du),
4702 SH_PFC_FUNCTION(hscif0),
4703 SH_PFC_FUNCTION(hscif1),
4704 SH_PFC_FUNCTION(hscif2),
4705 SH_PFC_FUNCTION(hscif3),
4706 SH_PFC_FUNCTION(hscif4),
4707 SH_PFC_FUNCTION(i2c0),
4708 SH_PFC_FUNCTION(i2c1),
4709 SH_PFC_FUNCTION(i2c2),
4710 SH_PFC_FUNCTION(i2c3),
4711 SH_PFC_FUNCTION(i2c5),
4712 SH_PFC_FUNCTION(i2c6),
4713 SH_PFC_FUNCTION(intc_ex),
4714 SH_PFC_FUNCTION(msiof0),
4715 SH_PFC_FUNCTION(msiof1),
4716 SH_PFC_FUNCTION(msiof2),
4717 SH_PFC_FUNCTION(msiof3),
4718 SH_PFC_FUNCTION(pwm0),
4719 SH_PFC_FUNCTION(pwm1),
4720 SH_PFC_FUNCTION(pwm2),
4721 SH_PFC_FUNCTION(pwm3),
4722 SH_PFC_FUNCTION(pwm4),
4723 SH_PFC_FUNCTION(pwm5),
4724 SH_PFC_FUNCTION(pwm6),
4725 SH_PFC_FUNCTION(qspi0),
4726 SH_PFC_FUNCTION(qspi1),
4727 SH_PFC_FUNCTION(sata0),
4728 SH_PFC_FUNCTION(scif0),
4729 SH_PFC_FUNCTION(scif1),
4730 SH_PFC_FUNCTION(scif2),
4731 SH_PFC_FUNCTION(scif3),
4732 SH_PFC_FUNCTION(scif4),
4733 SH_PFC_FUNCTION(scif5),
4734 SH_PFC_FUNCTION(scif_clk),
4735 SH_PFC_FUNCTION(sdhi0),
4736 SH_PFC_FUNCTION(sdhi1),
4737 SH_PFC_FUNCTION(sdhi2),
4738 SH_PFC_FUNCTION(sdhi3),
4739 SH_PFC_FUNCTION(ssi),
4740 SH_PFC_FUNCTION(tmu),
4741 SH_PFC_FUNCTION(tpu),
4742 SH_PFC_FUNCTION(usb0),
4743 SH_PFC_FUNCTION(usb1),
4744 SH_PFC_FUNCTION(usb2),
4745 SH_PFC_FUNCTION(usb30),
4746 SH_PFC_FUNCTION(usb31),
4747 };
4748
4749 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4750 #define F_(x, y) FN_##y
4751 #define FM(x) FN_##x
4752 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4753 0, 0,
4754 0, 0,
4755 0, 0,
4756 0, 0,
4757 0, 0,
4758 0, 0,
4759 0, 0,
4760 0, 0,
4761 0, 0,
4762 0, 0,
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 0, 0,
4769 GP_0_15_FN, GPSR0_15,
4770 GP_0_14_FN, GPSR0_14,
4771 GP_0_13_FN, GPSR0_13,
4772 GP_0_12_FN, GPSR0_12,
4773 GP_0_11_FN, GPSR0_11,
4774 GP_0_10_FN, GPSR0_10,
4775 GP_0_9_FN, GPSR0_9,
4776 GP_0_8_FN, GPSR0_8,
4777 GP_0_7_FN, GPSR0_7,
4778 GP_0_6_FN, GPSR0_6,
4779 GP_0_5_FN, GPSR0_5,
4780 GP_0_4_FN, GPSR0_4,
4781 GP_0_3_FN, GPSR0_3,
4782 GP_0_2_FN, GPSR0_2,
4783 GP_0_1_FN, GPSR0_1,
4784 GP_0_0_FN, GPSR0_0, ))
4785 },
4786 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4787 0, 0,
4788 0, 0,
4789 0, 0,
4790 0, 0,
4791 GP_1_27_FN, GPSR1_27,
4792 GP_1_26_FN, GPSR1_26,
4793 GP_1_25_FN, GPSR1_25,
4794 GP_1_24_FN, GPSR1_24,
4795 GP_1_23_FN, GPSR1_23,
4796 GP_1_22_FN, GPSR1_22,
4797 GP_1_21_FN, GPSR1_21,
4798 GP_1_20_FN, GPSR1_20,
4799 GP_1_19_FN, GPSR1_19,
4800 GP_1_18_FN, GPSR1_18,
4801 GP_1_17_FN, GPSR1_17,
4802 GP_1_16_FN, GPSR1_16,
4803 GP_1_15_FN, GPSR1_15,
4804 GP_1_14_FN, GPSR1_14,
4805 GP_1_13_FN, GPSR1_13,
4806 GP_1_12_FN, GPSR1_12,
4807 GP_1_11_FN, GPSR1_11,
4808 GP_1_10_FN, GPSR1_10,
4809 GP_1_9_FN, GPSR1_9,
4810 GP_1_8_FN, GPSR1_8,
4811 GP_1_7_FN, GPSR1_7,
4812 GP_1_6_FN, GPSR1_6,
4813 GP_1_5_FN, GPSR1_5,
4814 GP_1_4_FN, GPSR1_4,
4815 GP_1_3_FN, GPSR1_3,
4816 GP_1_2_FN, GPSR1_2,
4817 GP_1_1_FN, GPSR1_1,
4818 GP_1_0_FN, GPSR1_0, ))
4819 },
4820 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4821 0, 0,
4822 0, 0,
4823 0, 0,
4824 0, 0,
4825 0, 0,
4826 0, 0,
4827 0, 0,
4828 0, 0,
4829 0, 0,
4830 0, 0,
4831 0, 0,
4832 0, 0,
4833 0, 0,
4834 0, 0,
4835 0, 0,
4836 0, 0,
4837 0, 0,
4838 GP_2_14_FN, GPSR2_14,
4839 GP_2_13_FN, GPSR2_13,
4840 GP_2_12_FN, GPSR2_12,
4841 GP_2_11_FN, GPSR2_11,
4842 GP_2_10_FN, GPSR2_10,
4843 GP_2_9_FN, GPSR2_9,
4844 GP_2_8_FN, GPSR2_8,
4845 GP_2_7_FN, GPSR2_7,
4846 GP_2_6_FN, GPSR2_6,
4847 GP_2_5_FN, GPSR2_5,
4848 GP_2_4_FN, GPSR2_4,
4849 GP_2_3_FN, GPSR2_3,
4850 GP_2_2_FN, GPSR2_2,
4851 GP_2_1_FN, GPSR2_1,
4852 GP_2_0_FN, GPSR2_0, ))
4853 },
4854 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4855 0, 0,
4856 0, 0,
4857 0, 0,
4858 0, 0,
4859 0, 0,
4860 0, 0,
4861 0, 0,
4862 0, 0,
4863 0, 0,
4864 0, 0,
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 GP_3_15_FN, GPSR3_15,
4872 GP_3_14_FN, GPSR3_14,
4873 GP_3_13_FN, GPSR3_13,
4874 GP_3_12_FN, GPSR3_12,
4875 GP_3_11_FN, GPSR3_11,
4876 GP_3_10_FN, GPSR3_10,
4877 GP_3_9_FN, GPSR3_9,
4878 GP_3_8_FN, GPSR3_8,
4879 GP_3_7_FN, GPSR3_7,
4880 GP_3_6_FN, GPSR3_6,
4881 GP_3_5_FN, GPSR3_5,
4882 GP_3_4_FN, GPSR3_4,
4883 GP_3_3_FN, GPSR3_3,
4884 GP_3_2_FN, GPSR3_2,
4885 GP_3_1_FN, GPSR3_1,
4886 GP_3_0_FN, GPSR3_0, ))
4887 },
4888 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4889 0, 0,
4890 0, 0,
4891 0, 0,
4892 0, 0,
4893 0, 0,
4894 0, 0,
4895 0, 0,
4896 0, 0,
4897 0, 0,
4898 0, 0,
4899 0, 0,
4900 0, 0,
4901 0, 0,
4902 0, 0,
4903 GP_4_17_FN, GPSR4_17,
4904 GP_4_16_FN, GPSR4_16,
4905 GP_4_15_FN, GPSR4_15,
4906 GP_4_14_FN, GPSR4_14,
4907 GP_4_13_FN, GPSR4_13,
4908 GP_4_12_FN, GPSR4_12,
4909 GP_4_11_FN, GPSR4_11,
4910 GP_4_10_FN, GPSR4_10,
4911 GP_4_9_FN, GPSR4_9,
4912 GP_4_8_FN, GPSR4_8,
4913 GP_4_7_FN, GPSR4_7,
4914 GP_4_6_FN, GPSR4_6,
4915 GP_4_5_FN, GPSR4_5,
4916 GP_4_4_FN, GPSR4_4,
4917 GP_4_3_FN, GPSR4_3,
4918 GP_4_2_FN, GPSR4_2,
4919 GP_4_1_FN, GPSR4_1,
4920 GP_4_0_FN, GPSR4_0, ))
4921 },
4922 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4923 0, 0,
4924 0, 0,
4925 0, 0,
4926 0, 0,
4927 0, 0,
4928 0, 0,
4929 GP_5_25_FN, GPSR5_25,
4930 GP_5_24_FN, GPSR5_24,
4931 GP_5_23_FN, GPSR5_23,
4932 GP_5_22_FN, GPSR5_22,
4933 GP_5_21_FN, GPSR5_21,
4934 GP_5_20_FN, GPSR5_20,
4935 GP_5_19_FN, GPSR5_19,
4936 GP_5_18_FN, GPSR5_18,
4937 GP_5_17_FN, GPSR5_17,
4938 GP_5_16_FN, GPSR5_16,
4939 GP_5_15_FN, GPSR5_15,
4940 GP_5_14_FN, GPSR5_14,
4941 GP_5_13_FN, GPSR5_13,
4942 GP_5_12_FN, GPSR5_12,
4943 GP_5_11_FN, GPSR5_11,
4944 GP_5_10_FN, GPSR5_10,
4945 GP_5_9_FN, GPSR5_9,
4946 GP_5_8_FN, GPSR5_8,
4947 GP_5_7_FN, GPSR5_7,
4948 GP_5_6_FN, GPSR5_6,
4949 GP_5_5_FN, GPSR5_5,
4950 GP_5_4_FN, GPSR5_4,
4951 GP_5_3_FN, GPSR5_3,
4952 GP_5_2_FN, GPSR5_2,
4953 GP_5_1_FN, GPSR5_1,
4954 GP_5_0_FN, GPSR5_0, ))
4955 },
4956 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4957 GP_6_31_FN, GPSR6_31,
4958 GP_6_30_FN, GPSR6_30,
4959 GP_6_29_FN, GPSR6_29,
4960 GP_6_28_FN, GPSR6_28,
4961 GP_6_27_FN, GPSR6_27,
4962 GP_6_26_FN, GPSR6_26,
4963 GP_6_25_FN, GPSR6_25,
4964 GP_6_24_FN, GPSR6_24,
4965 GP_6_23_FN, GPSR6_23,
4966 GP_6_22_FN, GPSR6_22,
4967 GP_6_21_FN, GPSR6_21,
4968 GP_6_20_FN, GPSR6_20,
4969 GP_6_19_FN, GPSR6_19,
4970 GP_6_18_FN, GPSR6_18,
4971 GP_6_17_FN, GPSR6_17,
4972 GP_6_16_FN, GPSR6_16,
4973 GP_6_15_FN, GPSR6_15,
4974 GP_6_14_FN, GPSR6_14,
4975 GP_6_13_FN, GPSR6_13,
4976 GP_6_12_FN, GPSR6_12,
4977 GP_6_11_FN, GPSR6_11,
4978 GP_6_10_FN, GPSR6_10,
4979 GP_6_9_FN, GPSR6_9,
4980 GP_6_8_FN, GPSR6_8,
4981 GP_6_7_FN, GPSR6_7,
4982 GP_6_6_FN, GPSR6_6,
4983 GP_6_5_FN, GPSR6_5,
4984 GP_6_4_FN, GPSR6_4,
4985 GP_6_3_FN, GPSR6_3,
4986 GP_6_2_FN, GPSR6_2,
4987 GP_6_1_FN, GPSR6_1,
4988 GP_6_0_FN, GPSR6_0, ))
4989 },
4990 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
4991 0, 0,
4992 0, 0,
4993 0, 0,
4994 0, 0,
4995 0, 0,
4996 0, 0,
4997 0, 0,
4998 0, 0,
4999 0, 0,
5000 0, 0,
5001 0, 0,
5002 0, 0,
5003 0, 0,
5004 0, 0,
5005 0, 0,
5006 0, 0,
5007 0, 0,
5008 0, 0,
5009 0, 0,
5010 0, 0,
5011 0, 0,
5012 0, 0,
5013 0, 0,
5014 0, 0,
5015 0, 0,
5016 0, 0,
5017 0, 0,
5018 0, 0,
5019 GP_7_3_FN, GPSR7_3,
5020 GP_7_2_FN, GPSR7_2,
5021 GP_7_1_FN, GPSR7_1,
5022 GP_7_0_FN, GPSR7_0, ))
5023 },
5024 #undef F_
5025 #undef FM
5026
5027 #define F_(x, y) x,
5028 #define FM(x) FN_##x,
5029 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5030 IP0_31_28
5031 IP0_27_24
5032 IP0_23_20
5033 IP0_19_16
5034 IP0_15_12
5035 IP0_11_8
5036 IP0_7_4
5037 IP0_3_0 ))
5038 },
5039 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5040 IP1_31_28
5041 IP1_27_24
5042 IP1_23_20
5043 IP1_19_16
5044 IP1_15_12
5045 IP1_11_8
5046 IP1_7_4
5047 IP1_3_0 ))
5048 },
5049 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5050 IP2_31_28
5051 IP2_27_24
5052 IP2_23_20
5053 IP2_19_16
5054 IP2_15_12
5055 IP2_11_8
5056 IP2_7_4
5057 IP2_3_0 ))
5058 },
5059 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5060 IP3_31_28
5061 IP3_27_24
5062 IP3_23_20
5063 IP3_19_16
5064 IP3_15_12
5065 IP3_11_8
5066 IP3_7_4
5067 IP3_3_0 ))
5068 },
5069 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5070 IP4_31_28
5071 IP4_27_24
5072 IP4_23_20
5073 IP4_19_16
5074 IP4_15_12
5075 IP4_11_8
5076 IP4_7_4
5077 IP4_3_0 ))
5078 },
5079 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5080 IP5_31_28
5081 IP5_27_24
5082 IP5_23_20
5083 IP5_19_16
5084 IP5_15_12
5085 IP5_11_8
5086 IP5_7_4
5087 IP5_3_0 ))
5088 },
5089 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5090 IP6_31_28
5091 IP6_27_24
5092 IP6_23_20
5093 IP6_19_16
5094 IP6_15_12
5095 IP6_11_8
5096 IP6_7_4
5097 IP6_3_0 ))
5098 },
5099 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5100 IP7_31_28
5101 IP7_27_24
5102 IP7_23_20
5103 IP7_19_16
5104 IP7_15_12
5105 IP7_11_8
5106 IP7_7_4
5107 IP7_3_0 ))
5108 },
5109 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5110 IP8_31_28
5111 IP8_27_24
5112 IP8_23_20
5113 IP8_19_16
5114 IP8_15_12
5115 IP8_11_8
5116 IP8_7_4
5117 IP8_3_0 ))
5118 },
5119 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5120 IP9_31_28
5121 IP9_27_24
5122 IP9_23_20
5123 IP9_19_16
5124 IP9_15_12
5125 IP9_11_8
5126 IP9_7_4
5127 IP9_3_0 ))
5128 },
5129 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5130 IP10_31_28
5131 IP10_27_24
5132 IP10_23_20
5133 IP10_19_16
5134 IP10_15_12
5135 IP10_11_8
5136 IP10_7_4
5137 IP10_3_0 ))
5138 },
5139 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5140 IP11_31_28
5141 IP11_27_24
5142 IP11_23_20
5143 IP11_19_16
5144 IP11_15_12
5145 IP11_11_8
5146 IP11_7_4
5147 IP11_3_0 ))
5148 },
5149 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5150 IP12_31_28
5151 IP12_27_24
5152 IP12_23_20
5153 IP12_19_16
5154 IP12_15_12
5155 IP12_11_8
5156 IP12_7_4
5157 IP12_3_0 ))
5158 },
5159 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5160 IP13_31_28
5161 IP13_27_24
5162 IP13_23_20
5163 IP13_19_16
5164 IP13_15_12
5165 IP13_11_8
5166 IP13_7_4
5167 IP13_3_0 ))
5168 },
5169 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5170 IP14_31_28
5171 IP14_27_24
5172 IP14_23_20
5173 IP14_19_16
5174 IP14_15_12
5175 IP14_11_8
5176 IP14_7_4
5177 IP14_3_0 ))
5178 },
5179 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5180 IP15_31_28
5181 IP15_27_24
5182 IP15_23_20
5183 IP15_19_16
5184 IP15_15_12
5185 IP15_11_8
5186 IP15_7_4
5187 IP15_3_0 ))
5188 },
5189 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5190 IP16_31_28
5191 IP16_27_24
5192 IP16_23_20
5193 IP16_19_16
5194 IP16_15_12
5195 IP16_11_8
5196 IP16_7_4
5197 IP16_3_0 ))
5198 },
5199 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5200 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5201 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5202 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5203 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5204 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5205 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5206 IP17_7_4
5207 IP17_3_0 ))
5208 },
5209 #undef F_
5210 #undef FM
5211
5212 #define F_(x, y) x,
5213 #define FM(x) FN_##x,
5214 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5215 GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
5216 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
5217 GROUP(
5218 0, 0, /* RESERVED 31 */
5219 MOD_SEL0_30_29
5220 MOD_SEL0_28_27
5221 MOD_SEL0_26_25_24
5222 MOD_SEL0_23
5223 MOD_SEL0_22
5224 MOD_SEL0_21_20
5225 MOD_SEL0_19
5226 MOD_SEL0_18
5227 MOD_SEL0_17
5228 MOD_SEL0_16_15
5229 MOD_SEL0_14
5230 MOD_SEL0_13
5231 MOD_SEL0_12
5232 MOD_SEL0_11
5233 MOD_SEL0_10
5234 MOD_SEL0_9
5235 MOD_SEL0_8
5236 MOD_SEL0_7_6
5237 MOD_SEL0_5_4
5238 MOD_SEL0_3
5239 MOD_SEL0_2_1
5240 0, 0, /* RESERVED 0 */ ))
5241 },
5242 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5243 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5244 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5245 GROUP(
5246 MOD_SEL1_31_30
5247 MOD_SEL1_29_28_27
5248 MOD_SEL1_26
5249 MOD_SEL1_25_24
5250 MOD_SEL1_23_22_21
5251 MOD_SEL1_20
5252 MOD_SEL1_19
5253 MOD_SEL1_18_17
5254 MOD_SEL1_16
5255 MOD_SEL1_15_14
5256 MOD_SEL1_13
5257 MOD_SEL1_12
5258 MOD_SEL1_11
5259 MOD_SEL1_10
5260 MOD_SEL1_9
5261 0, 0, 0, 0, /* RESERVED 8, 7 */
5262 MOD_SEL1_6
5263 MOD_SEL1_5
5264 MOD_SEL1_4
5265 MOD_SEL1_3
5266 MOD_SEL1_2
5267 MOD_SEL1_1
5268 MOD_SEL1_0 ))
5269 },
5270 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5271 GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
5272 GROUP(
5273 MOD_SEL2_31
5274 MOD_SEL2_30
5275 MOD_SEL2_29
5276 /* RESERVED 28 */
5277 0, 0,
5278 /* RESERVED 27, 26, 25, 24 */
5279 0, 0, 0, 0, 0, 0, 0, 0,
5280 0, 0, 0, 0, 0, 0, 0, 0,
5281 /* RESERVED 23, 22, 21, 20 */
5282 0, 0, 0, 0, 0, 0, 0, 0,
5283 0, 0, 0, 0, 0, 0, 0, 0,
5284 /* RESERVED 19, 18, 17, 16 */
5285 0, 0, 0, 0, 0, 0, 0, 0,
5286 0, 0, 0, 0, 0, 0, 0, 0,
5287 /* RESERVED 15, 14, 13, 12 */
5288 0, 0, 0, 0, 0, 0, 0, 0,
5289 0, 0, 0, 0, 0, 0, 0, 0,
5290 /* RESERVED 11, 10, 9, 8 */
5291 0, 0, 0, 0, 0, 0, 0, 0,
5292 0, 0, 0, 0, 0, 0, 0, 0,
5293 /* RESERVED 7, 6, 5, 4 */
5294 0, 0, 0, 0, 0, 0, 0, 0,
5295 0, 0, 0, 0, 0, 0, 0, 0,
5296 /* RESERVED 3 */
5297 0, 0,
5298 /* RESERVED 2, 1 */
5299 0, 0, 0, 0,
5300 MOD_SEL2_0 ))
5301 },
5302 { },
5303 };
5304
5305 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5306 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5307 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5308 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5309 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5310 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5311 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5312 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5313 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5314 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5315 } },
5316 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5317 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5318 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5319 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5320 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5321 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5322 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5323 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5324 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5325 } },
5326 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5327 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5328 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5329 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5330 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5331 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5332 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5333 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5334 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5335 } },
5336 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5337 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5338 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5339 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5340 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5341 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5342 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5343 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5344 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5345 } },
5346 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5347 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5348 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5349 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5350 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5351 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5352 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5353 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5354 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5355 } },
5356 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5357 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5358 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5359 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5360 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5361 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5362 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5363 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5364 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5365 } },
5366 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5367 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5368 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5369 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5370 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5371 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5372 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5373 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5374 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5375 } },
5376 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5377 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5378 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5379 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5380 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5381 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5382 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5383 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5384 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5385 } },
5386 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5387 { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
5388 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5389 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5390 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5391 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5392 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5393 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5394 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5395 } },
5396 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5397 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5398 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5399 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5400 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5401 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5402 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5403 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5404 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5405 } },
5406 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5407 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5408 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5409 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5410 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5411 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5412 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5413 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5414 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5415 } },
5416 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5417 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5418 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5419 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5420 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5421 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5422 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5423 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5424 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5425 } },
5426 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5427 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5428 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5429 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5430 { PIN_TMS, 4, 2 }, /* TMS */
5431 } },
5432 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5433 { PIN_TDO, 28, 2 }, /* TDO */
5434 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5435 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5436 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5437 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5438 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5439 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5440 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5441 } },
5442 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5443 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5444 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5445 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5446 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5447 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5448 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5449 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5450 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5451 } },
5452 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5453 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5454 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5455 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5456 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5457 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5458 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5459 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5460 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5461 } },
5462 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5463 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5464 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5465 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5466 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5467 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5468 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5469 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5470 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5471 } },
5472 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5473 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5474 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5475 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5476 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5477 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5478 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5479 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5480 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5481 } },
5482 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5483 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5484 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5485 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5486 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5487 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5488 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5489 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5490 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5491 } },
5492 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5493 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5494 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5495 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5496 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5497 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5498 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5499 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5500 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5501 } },
5502 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5503 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5504 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5505 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5506 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5507 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5508 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5509 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5510 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5511 } },
5512 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5513 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5514 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5515 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5516 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5517 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5518 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5519 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5520 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5521 } },
5522 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5523 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5524 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5525 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5526 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5527 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5528 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5529 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5530 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5531 } },
5532 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5533 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5534 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5535 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5536 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5537 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5538 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5539 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5540 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5541 } },
5542 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5543 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5544 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5545 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5546 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5547 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5548 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5549 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5550 } },
5551 { },
5552 };
5553
5554 enum ioctrl_regs {
5555 POCCTRL,
5556 TDSELCTRL,
5557 };
5558
5559 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5560 [POCCTRL] = { 0xe6060380, },
5561 [TDSELCTRL] = { 0xe60603c0, },
5562 { /* sentinel */ },
5563 };
5564
r8a77950_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)5565 static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5566 u32 *pocctrl)
5567 {
5568 int bit = -EINVAL;
5569
5570 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5571
5572 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5573 bit = pin & 0x1f;
5574
5575 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5576 bit = (pin & 0x1f) + 12;
5577
5578 return bit;
5579 }
5580
5581 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5582 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5583 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5584 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5585 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5586 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5587 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5588 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5589 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5590 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5591 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5592 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5593 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5594 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5595 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5596 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5597 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5598 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5599 [16] = PIN_AVB_RXC, /* AVB_RXC */
5600 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5601 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5602 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5603 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5604 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5605 [22] = PIN_AVB_TXC, /* AVB_TXC */
5606 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5607 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5608 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5609 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5610 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5611 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
5612 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5613 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5614 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5615 } },
5616 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5617 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5618 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5619 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5620 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5621 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5622 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5623 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5624 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5625 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5626 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5627 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5628 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5629 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5630 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5631 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5632 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5633 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5634 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5635 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5636 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5637 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5638 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5639 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5640 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5641 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5642 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5643 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5644 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5645 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5646 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5647 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5648 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5649 } },
5650 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5651 [ 0] = PIN_CLKOUT, /* CLKOUT */
5652 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5653 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
5654 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5655 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5656 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5657 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5658 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5659 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5660 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
5661 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5662 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5663 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5664 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5665 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5666 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5667 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5668 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5669 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5670 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5671 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5672 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5673 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5674 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5675 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5676 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5677 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5678 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5679 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5680 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5681 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5682 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
5683 } },
5684 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5685 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5686 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
5687 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
5688 [ 3] = PIN_EXTALR, /* EXTALR*/
5689 [ 4] = PIN_TRST_N, /* TRST# */
5690 [ 5] = PIN_TCK, /* TCK */
5691 [ 6] = PIN_TMS, /* TMS */
5692 [ 7] = PIN_TDI, /* TDI */
5693 [ 8] = SH_PFC_PIN_NONE,
5694 [ 9] = PIN_ASEBRK, /* ASEBRK */
5695 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5696 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5697 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5698 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5699 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5700 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5701 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5702 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5703 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5704 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5705 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5706 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5707 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5708 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5709 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5710 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5711 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5712 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5713 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5714 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5715 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5716 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5717 } },
5718 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5719 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5720 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5721 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5722 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5723 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5724 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5725 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5726 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5727 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5728 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5729 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5730 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5731 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5732 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5733 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5734 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5735 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5736 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5737 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5738 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5739 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5740 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5741 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5742 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5743 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5744 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5745 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5746 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5747 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5748 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5749 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5750 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5751 } },
5752 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5753 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5754 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5755 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5756 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5757 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5758 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5759 [ 6] = PIN_MLB_REF, /* MLB_REF */
5760 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5761 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5762 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5763 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5764 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5765 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5766 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5767 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5768 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5769 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5770 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5771 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5772 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5773 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5774 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5775 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5776 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5777 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5778 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5779 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5780 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5781 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5782 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5783 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5784 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5785 } },
5786 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5787 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5788 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5789 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5790 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5791 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5792 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
5793 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5794 [ 7] = SH_PFC_PIN_NONE,
5795 [ 8] = SH_PFC_PIN_NONE,
5796 [ 9] = SH_PFC_PIN_NONE,
5797 [10] = SH_PFC_PIN_NONE,
5798 [11] = SH_PFC_PIN_NONE,
5799 [12] = SH_PFC_PIN_NONE,
5800 [13] = SH_PFC_PIN_NONE,
5801 [14] = SH_PFC_PIN_NONE,
5802 [15] = SH_PFC_PIN_NONE,
5803 [16] = SH_PFC_PIN_NONE,
5804 [17] = SH_PFC_PIN_NONE,
5805 [18] = SH_PFC_PIN_NONE,
5806 [19] = SH_PFC_PIN_NONE,
5807 [20] = SH_PFC_PIN_NONE,
5808 [21] = SH_PFC_PIN_NONE,
5809 [22] = SH_PFC_PIN_NONE,
5810 [23] = SH_PFC_PIN_NONE,
5811 [24] = SH_PFC_PIN_NONE,
5812 [25] = SH_PFC_PIN_NONE,
5813 [26] = SH_PFC_PIN_NONE,
5814 [27] = SH_PFC_PIN_NONE,
5815 [28] = SH_PFC_PIN_NONE,
5816 [29] = SH_PFC_PIN_NONE,
5817 [30] = SH_PFC_PIN_NONE,
5818 [31] = SH_PFC_PIN_NONE,
5819 } },
5820 { /* sentinel */ },
5821 };
5822
r8a77950_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)5823 static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
5824 unsigned int pin)
5825 {
5826 const struct pinmux_bias_reg *reg;
5827 unsigned int bit;
5828
5829 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5830 if (!reg)
5831 return PIN_CONFIG_BIAS_DISABLE;
5832
5833 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5834 return PIN_CONFIG_BIAS_DISABLE;
5835 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5836 return PIN_CONFIG_BIAS_PULL_UP;
5837 else
5838 return PIN_CONFIG_BIAS_PULL_DOWN;
5839 }
5840
r8a77950_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)5841 static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5842 unsigned int bias)
5843 {
5844 const struct pinmux_bias_reg *reg;
5845 u32 enable, updown;
5846 unsigned int bit;
5847
5848 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5849 if (!reg)
5850 return;
5851
5852 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5853 if (bias != PIN_CONFIG_BIAS_DISABLE)
5854 enable |= BIT(bit);
5855
5856 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5857 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5858 updown |= BIT(bit);
5859
5860 sh_pfc_write(pfc, reg->pud, updown);
5861 sh_pfc_write(pfc, reg->puen, enable);
5862 }
5863
5864 static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
5865 .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
5866 .get_bias = r8a77950_pinmux_get_bias,
5867 .set_bias = r8a77950_pinmux_set_bias,
5868 };
5869
5870 const struct sh_pfc_soc_info r8a77950_pinmux_info = {
5871 .name = "r8a77950_pfc",
5872 .ops = &r8a77950_pinmux_ops,
5873 .unlock_reg = 0xe6060000, /* PMMR */
5874
5875 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5876
5877 .pins = pinmux_pins,
5878 .nr_pins = ARRAY_SIZE(pinmux_pins),
5879 .groups = pinmux_groups,
5880 .nr_groups = ARRAY_SIZE(pinmux_groups),
5881 .functions = pinmux_functions,
5882 .nr_functions = ARRAY_SIZE(pinmux_functions),
5883
5884 .cfg_regs = pinmux_config_regs,
5885 .drive_regs = pinmux_drive_regs,
5886 .bias_regs = pinmux_bias_regs,
5887 .ioctrl_regs = pinmux_ioctrl_regs,
5888
5889 .pinmux_data = pinmux_data,
5890 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5891 };
5892