1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <linux/bitfield.h>
13 #include <linux/can.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/error.h>
16 #include <linux/can/led.h>
17 #include <linux/can/rx-offload.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32
33 #define DRV_NAME "flexcan"
34
35 /* 8 for RX fifo and 2 error handling */
36 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
37
38 /* FLEXCAN module configuration register (CANMCR) bits */
39 #define FLEXCAN_MCR_MDIS BIT(31)
40 #define FLEXCAN_MCR_FRZ BIT(30)
41 #define FLEXCAN_MCR_FEN BIT(29)
42 #define FLEXCAN_MCR_HALT BIT(28)
43 #define FLEXCAN_MCR_NOT_RDY BIT(27)
44 #define FLEXCAN_MCR_WAK_MSK BIT(26)
45 #define FLEXCAN_MCR_SOFTRST BIT(25)
46 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
47 #define FLEXCAN_MCR_SUPV BIT(23)
48 #define FLEXCAN_MCR_SLF_WAK BIT(22)
49 #define FLEXCAN_MCR_WRN_EN BIT(21)
50 #define FLEXCAN_MCR_LPM_ACK BIT(20)
51 #define FLEXCAN_MCR_WAK_SRC BIT(19)
52 #define FLEXCAN_MCR_DOZE BIT(18)
53 #define FLEXCAN_MCR_SRX_DIS BIT(17)
54 #define FLEXCAN_MCR_IRMQ BIT(16)
55 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
56 #define FLEXCAN_MCR_AEN BIT(12)
57 #define FLEXCAN_MCR_FDEN BIT(11)
58 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
59 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
60 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
61 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
62 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
63 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
64
65 /* FLEXCAN control register (CANCTRL) bits */
66 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
67 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
68 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
69 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
70 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
71 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
72 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
73 #define FLEXCAN_CTRL_LPB BIT(12)
74 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
75 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
76 #define FLEXCAN_CTRL_SMP BIT(7)
77 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
78 #define FLEXCAN_CTRL_TSYN BIT(5)
79 #define FLEXCAN_CTRL_LBUF BIT(4)
80 #define FLEXCAN_CTRL_LOM BIT(3)
81 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
82 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
83 #define FLEXCAN_CTRL_ERR_STATE \
84 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
85 FLEXCAN_CTRL_BOFF_MSK)
86 #define FLEXCAN_CTRL_ERR_ALL \
87 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
88
89 /* FLEXCAN control register 2 (CTRL2) bits */
90 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
91 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
92 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
93 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
94 #define FLEXCAN_CTRL2_MRP BIT(18)
95 #define FLEXCAN_CTRL2_RRS BIT(17)
96 #define FLEXCAN_CTRL2_EACEN BIT(16)
97 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
98
99 /* FLEXCAN memory error control register (MECR) bits */
100 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
101 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
102 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
103 #define FLEXCAN_MECR_CEI_MSK BIT(16)
104 #define FLEXCAN_MECR_HAERRIE BIT(15)
105 #define FLEXCAN_MECR_FAERRIE BIT(14)
106 #define FLEXCAN_MECR_EXTERRIE BIT(13)
107 #define FLEXCAN_MECR_RERRDIS BIT(9)
108 #define FLEXCAN_MECR_ECCDIS BIT(8)
109 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
110
111 /* FLEXCAN error and status register (ESR) bits */
112 #define FLEXCAN_ESR_TWRN_INT BIT(17)
113 #define FLEXCAN_ESR_RWRN_INT BIT(16)
114 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
115 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
116 #define FLEXCAN_ESR_ACK_ERR BIT(13)
117 #define FLEXCAN_ESR_CRC_ERR BIT(12)
118 #define FLEXCAN_ESR_FRM_ERR BIT(11)
119 #define FLEXCAN_ESR_STF_ERR BIT(10)
120 #define FLEXCAN_ESR_TX_WRN BIT(9)
121 #define FLEXCAN_ESR_RX_WRN BIT(8)
122 #define FLEXCAN_ESR_IDLE BIT(7)
123 #define FLEXCAN_ESR_TXRX BIT(6)
124 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
125 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
126 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
127 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
128 #define FLEXCAN_ESR_BOFF_INT BIT(2)
129 #define FLEXCAN_ESR_ERR_INT BIT(1)
130 #define FLEXCAN_ESR_WAK_INT BIT(0)
131 #define FLEXCAN_ESR_ERR_BUS \
132 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
133 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
134 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
135 #define FLEXCAN_ESR_ERR_STATE \
136 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
137 #define FLEXCAN_ESR_ERR_ALL \
138 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
139 #define FLEXCAN_ESR_ALL_INT \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
141 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
142
143 /* FLEXCAN Bit Timing register (CBT) bits */
144 #define FLEXCAN_CBT_BTF BIT(31)
145 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
146 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
147 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
148 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
149 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
150
151 /* FLEXCAN FD control register (FDCTRL) bits */
152 #define FLEXCAN_FDCTRL_FDRATE BIT(31)
153 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
154 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
155 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
156 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
157 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
158 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
159 #define FLEXCAN_FDCTRL_TDCEN BIT(15)
160 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
161 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
162 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
163
164 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
165 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
166 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
167 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
168 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
169 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
170
171 /* FLEXCAN interrupt flag register (IFLAG) bits */
172 /* Errata ERR005829 step7: Reserve first valid MB */
173 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
174 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
175 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
176 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
177 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
178 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
179 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
180
181 /* FLEXCAN message buffers */
182 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
183 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
184 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
185 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
186 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
187 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
188 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
189
190 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
191 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
192 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
193 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
194
195 #define FLEXCAN_MB_CNT_EDL BIT(31)
196 #define FLEXCAN_MB_CNT_BRS BIT(30)
197 #define FLEXCAN_MB_CNT_ESI BIT(29)
198 #define FLEXCAN_MB_CNT_SRR BIT(22)
199 #define FLEXCAN_MB_CNT_IDE BIT(21)
200 #define FLEXCAN_MB_CNT_RTR BIT(20)
201 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
202 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
203
204 #define FLEXCAN_TIMEOUT_US (250)
205
206 /* FLEXCAN hardware feature flags
207 *
208 * Below is some version info we got:
209 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
210 * Filter? connected? Passive detection ption in MB Supported?
211 * MX25 FlexCAN2 03.00.00.00 no no no no no no
212 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no
213 * MX35 FlexCAN2 03.00.00.00 no no no no no no
214 * MX53 FlexCAN2 03.00.00.00 yes no no no no no
215 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
216 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
217 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
218 * VF610 FlexCAN3 ? no yes no yes yes? no
219 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
220 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
221 *
222 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
223 */
224
225 /* [TR]WRN_INT not connected */
226 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
227 /* Disable RX FIFO Global mask */
228 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
229 /* Enable EACEN and RRS bit in ctrl2 */
230 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
231 /* Disable non-correctable errors interrupt and freeze mode */
232 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
233 /* Use timestamp based offloading */
234 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
235 /* No interrupt for error passive */
236 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
237 /* default to BE register access */
238 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
239 /* Setup stop mode to support wakeup */
240 #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
241 /* Support CAN-FD mode */
242 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
243 /* support memory detection and correction */
244 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
245
246 /* Structure of the message buffer */
247 struct flexcan_mb {
248 u32 can_ctrl;
249 u32 can_id;
250 u32 data[];
251 };
252
253 /* Structure of the hardware registers */
254 struct flexcan_regs {
255 u32 mcr; /* 0x00 */
256 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
257 u32 timer; /* 0x08 */
258 u32 tcr; /* 0x0c */
259 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
260 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
261 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
262 u32 ecr; /* 0x1c */
263 u32 esr; /* 0x20 */
264 u32 imask2; /* 0x24 */
265 u32 imask1; /* 0x28 */
266 u32 iflag2; /* 0x2c */
267 u32 iflag1; /* 0x30 */
268 union { /* 0x34 */
269 u32 gfwr_mx28; /* MX28, MX53 */
270 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
271 };
272 u32 esr2; /* 0x38 */
273 u32 imeur; /* 0x3c */
274 u32 lrfr; /* 0x40 */
275 u32 crcr; /* 0x44 */
276 u32 rxfgmask; /* 0x48 */
277 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
278 u32 cbt; /* 0x50 - Not affected by Soft Reset */
279 u32 _reserved2; /* 0x54 */
280 u32 dbg1; /* 0x58 */
281 u32 dbg2; /* 0x5c */
282 u32 _reserved3[8]; /* 0x60 */
283 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
284 /* FIFO-mode:
285 * MB
286 * 0x080...0x08f 0 RX message buffer
287 * 0x090...0x0df 1-5 reserved
288 * 0x0e0...0x0ff 6-7 8 entry ID table
289 * (mx25, mx28, mx35, mx53)
290 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
291 * size conf'ed via ctrl2::RFFN
292 * (mx6, vf610)
293 */
294 u32 _reserved4[256]; /* 0x480 */
295 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
296 u32 _reserved5[24]; /* 0x980 */
297 u32 gfwr_mx6; /* 0x9e0 - MX6 */
298 u32 _reserved6[39]; /* 0x9e4 */
299 u32 _rxfir[6]; /* 0xa80 */
300 u32 _reserved8[2]; /* 0xa98 */
301 u32 _rxmgmask; /* 0xaa0 */
302 u32 _rxfgmask; /* 0xaa4 */
303 u32 _rx14mask; /* 0xaa8 */
304 u32 _rx15mask; /* 0xaac */
305 u32 tx_smb[4]; /* 0xab0 */
306 u32 rx_smb0[4]; /* 0xac0 */
307 u32 rx_smb1[4]; /* 0xad0 */
308 u32 mecr; /* 0xae0 */
309 u32 erriar; /* 0xae4 */
310 u32 erridpr; /* 0xae8 */
311 u32 errippr; /* 0xaec */
312 u32 rerrar; /* 0xaf0 */
313 u32 rerrdr; /* 0xaf4 */
314 u32 rerrsynr; /* 0xaf8 */
315 u32 errsr; /* 0xafc */
316 u32 _reserved7[64]; /* 0xb00 */
317 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
318 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
319 u32 fdcrc; /* 0xc08 */
320 u32 _reserved9[199]; /* 0xc0c */
321 u32 tx_smb_fd[18]; /* 0xf28 */
322 u32 rx_smb0_fd[18]; /* 0xf70 */
323 u32 rx_smb1_fd[18]; /* 0xfb8 */
324 };
325
326 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
327
328 struct flexcan_devtype_data {
329 u32 quirks; /* quirks needed for different IP cores */
330 };
331
332 struct flexcan_stop_mode {
333 struct regmap *gpr;
334 u8 req_gpr;
335 u8 req_bit;
336 };
337
338 struct flexcan_priv {
339 struct can_priv can;
340 struct can_rx_offload offload;
341 struct device *dev;
342
343 struct flexcan_regs __iomem *regs;
344 struct flexcan_mb __iomem *tx_mb;
345 struct flexcan_mb __iomem *tx_mb_reserved;
346 u8 tx_mb_idx;
347 u8 mb_count;
348 u8 mb_size;
349 u8 clk_src; /* clock source of CAN Protocol Engine */
350
351 u64 rx_mask;
352 u64 tx_mask;
353 u32 reg_ctrl_default;
354
355 struct clk *clk_ipg;
356 struct clk *clk_per;
357 const struct flexcan_devtype_data *devtype_data;
358 struct regulator *reg_xceiver;
359 struct flexcan_stop_mode stm;
360
361 /* Read and Write APIs */
362 u32 (*read)(void __iomem *addr);
363 void (*write)(u32 val, void __iomem *addr);
364 };
365
366 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
367 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
368 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
369 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
370 };
371
372 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
373 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
374 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
375 };
376
377 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
378 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
379 };
380
381 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
382 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
383 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
384 FLEXCAN_QUIRK_SETUP_STOP_MODE,
385 };
386
387 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
388 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
389 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
390 FLEXCAN_QUIRK_SUPPORT_FD,
391 };
392
393 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
394 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
395 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
396 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE |
397 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
398 };
399
400 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
401 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
402 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
403 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
404 };
405
406 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
407 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
408 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
409 };
410
411 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
412 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
413 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
414 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
415 FLEXCAN_QUIRK_SUPPORT_ECC,
416 };
417
418 static const struct can_bittiming_const flexcan_bittiming_const = {
419 .name = DRV_NAME,
420 .tseg1_min = 4,
421 .tseg1_max = 16,
422 .tseg2_min = 2,
423 .tseg2_max = 8,
424 .sjw_max = 4,
425 .brp_min = 1,
426 .brp_max = 256,
427 .brp_inc = 1,
428 };
429
430 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
431 .name = DRV_NAME,
432 .tseg1_min = 2,
433 .tseg1_max = 96,
434 .tseg2_min = 2,
435 .tseg2_max = 32,
436 .sjw_max = 16,
437 .brp_min = 1,
438 .brp_max = 1024,
439 .brp_inc = 1,
440 };
441
442 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
443 .name = DRV_NAME,
444 .tseg1_min = 2,
445 .tseg1_max = 39,
446 .tseg2_min = 2,
447 .tseg2_max = 8,
448 .sjw_max = 4,
449 .brp_min = 1,
450 .brp_max = 1024,
451 .brp_inc = 1,
452 };
453
454 /* FlexCAN module is essentially modelled as a little-endian IP in most
455 * SoCs, i.e the registers as well as the message buffer areas are
456 * implemented in a little-endian fashion.
457 *
458 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
459 * module in a big-endian fashion (i.e the registers as well as the
460 * message buffer areas are implemented in a big-endian way).
461 *
462 * In addition, the FlexCAN module can be found on SoCs having ARM or
463 * PPC cores. So, we need to abstract off the register read/write
464 * functions, ensuring that these cater to all the combinations of module
465 * endianness and underlying CPU endianness.
466 */
flexcan_read_be(void __iomem * addr)467 static inline u32 flexcan_read_be(void __iomem *addr)
468 {
469 return ioread32be(addr);
470 }
471
flexcan_write_be(u32 val,void __iomem * addr)472 static inline void flexcan_write_be(u32 val, void __iomem *addr)
473 {
474 iowrite32be(val, addr);
475 }
476
flexcan_read_le(void __iomem * addr)477 static inline u32 flexcan_read_le(void __iomem *addr)
478 {
479 return ioread32(addr);
480 }
481
flexcan_write_le(u32 val,void __iomem * addr)482 static inline void flexcan_write_le(u32 val, void __iomem *addr)
483 {
484 iowrite32(val, addr);
485 }
486
flexcan_get_mb(const struct flexcan_priv * priv,u8 mb_index)487 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
488 u8 mb_index)
489 {
490 u8 bank_size;
491 bool bank;
492
493 if (WARN_ON(mb_index >= priv->mb_count))
494 return NULL;
495
496 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
497
498 bank = mb_index >= bank_size;
499 if (bank)
500 mb_index -= bank_size;
501
502 return (struct flexcan_mb __iomem *)
503 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
504 }
505
flexcan_low_power_enter_ack(struct flexcan_priv * priv)506 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
507 {
508 struct flexcan_regs __iomem *regs = priv->regs;
509 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
510
511 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
512 udelay(10);
513
514 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
515 return -ETIMEDOUT;
516
517 return 0;
518 }
519
flexcan_low_power_exit_ack(struct flexcan_priv * priv)520 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
521 {
522 struct flexcan_regs __iomem *regs = priv->regs;
523 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
524
525 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
526 udelay(10);
527
528 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
529 return -ETIMEDOUT;
530
531 return 0;
532 }
533
flexcan_enable_wakeup_irq(struct flexcan_priv * priv,bool enable)534 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
535 {
536 struct flexcan_regs __iomem *regs = priv->regs;
537 u32 reg_mcr;
538
539 reg_mcr = priv->read(®s->mcr);
540
541 if (enable)
542 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
543 else
544 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
545
546 priv->write(reg_mcr, ®s->mcr);
547 }
548
flexcan_enter_stop_mode(struct flexcan_priv * priv)549 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
550 {
551 struct flexcan_regs __iomem *regs = priv->regs;
552 u32 reg_mcr;
553
554 reg_mcr = priv->read(®s->mcr);
555 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
556 priv->write(reg_mcr, ®s->mcr);
557
558 /* enable stop request */
559 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
560 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
561
562 return flexcan_low_power_enter_ack(priv);
563 }
564
flexcan_exit_stop_mode(struct flexcan_priv * priv)565 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
566 {
567 struct flexcan_regs __iomem *regs = priv->regs;
568 u32 reg_mcr;
569
570 /* remove stop request */
571 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
572 1 << priv->stm.req_bit, 0);
573
574 reg_mcr = priv->read(®s->mcr);
575 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
576 priv->write(reg_mcr, ®s->mcr);
577
578 return flexcan_low_power_exit_ack(priv);
579 }
580
flexcan_error_irq_enable(const struct flexcan_priv * priv)581 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
582 {
583 struct flexcan_regs __iomem *regs = priv->regs;
584 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
585
586 priv->write(reg_ctrl, ®s->ctrl);
587 }
588
flexcan_error_irq_disable(const struct flexcan_priv * priv)589 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
590 {
591 struct flexcan_regs __iomem *regs = priv->regs;
592 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
593
594 priv->write(reg_ctrl, ®s->ctrl);
595 }
596
flexcan_clks_enable(const struct flexcan_priv * priv)597 static int flexcan_clks_enable(const struct flexcan_priv *priv)
598 {
599 int err;
600
601 err = clk_prepare_enable(priv->clk_ipg);
602 if (err)
603 return err;
604
605 err = clk_prepare_enable(priv->clk_per);
606 if (err)
607 clk_disable_unprepare(priv->clk_ipg);
608
609 return err;
610 }
611
flexcan_clks_disable(const struct flexcan_priv * priv)612 static void flexcan_clks_disable(const struct flexcan_priv *priv)
613 {
614 clk_disable_unprepare(priv->clk_per);
615 clk_disable_unprepare(priv->clk_ipg);
616 }
617
flexcan_transceiver_enable(const struct flexcan_priv * priv)618 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
619 {
620 if (!priv->reg_xceiver)
621 return 0;
622
623 return regulator_enable(priv->reg_xceiver);
624 }
625
flexcan_transceiver_disable(const struct flexcan_priv * priv)626 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
627 {
628 if (!priv->reg_xceiver)
629 return 0;
630
631 return regulator_disable(priv->reg_xceiver);
632 }
633
flexcan_chip_enable(struct flexcan_priv * priv)634 static int flexcan_chip_enable(struct flexcan_priv *priv)
635 {
636 struct flexcan_regs __iomem *regs = priv->regs;
637 u32 reg;
638
639 reg = priv->read(®s->mcr);
640 reg &= ~FLEXCAN_MCR_MDIS;
641 priv->write(reg, ®s->mcr);
642
643 return flexcan_low_power_exit_ack(priv);
644 }
645
flexcan_chip_disable(struct flexcan_priv * priv)646 static int flexcan_chip_disable(struct flexcan_priv *priv)
647 {
648 struct flexcan_regs __iomem *regs = priv->regs;
649 u32 reg;
650
651 reg = priv->read(®s->mcr);
652 reg |= FLEXCAN_MCR_MDIS;
653 priv->write(reg, ®s->mcr);
654
655 return flexcan_low_power_enter_ack(priv);
656 }
657
flexcan_chip_freeze(struct flexcan_priv * priv)658 static int flexcan_chip_freeze(struct flexcan_priv *priv)
659 {
660 struct flexcan_regs __iomem *regs = priv->regs;
661 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
662 u32 reg;
663
664 reg = priv->read(®s->mcr);
665 reg |= FLEXCAN_MCR_HALT;
666 priv->write(reg, ®s->mcr);
667
668 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
669 udelay(100);
670
671 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
672 return -ETIMEDOUT;
673
674 return 0;
675 }
676
flexcan_chip_unfreeze(struct flexcan_priv * priv)677 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
678 {
679 struct flexcan_regs __iomem *regs = priv->regs;
680 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
681 u32 reg;
682
683 reg = priv->read(®s->mcr);
684 reg &= ~FLEXCAN_MCR_HALT;
685 priv->write(reg, ®s->mcr);
686
687 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
688 udelay(10);
689
690 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
691 return -ETIMEDOUT;
692
693 return 0;
694 }
695
flexcan_chip_softreset(struct flexcan_priv * priv)696 static int flexcan_chip_softreset(struct flexcan_priv *priv)
697 {
698 struct flexcan_regs __iomem *regs = priv->regs;
699 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
700
701 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
702 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
703 udelay(10);
704
705 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
706 return -ETIMEDOUT;
707
708 return 0;
709 }
710
__flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)711 static int __flexcan_get_berr_counter(const struct net_device *dev,
712 struct can_berr_counter *bec)
713 {
714 const struct flexcan_priv *priv = netdev_priv(dev);
715 struct flexcan_regs __iomem *regs = priv->regs;
716 u32 reg = priv->read(®s->ecr);
717
718 bec->txerr = (reg >> 0) & 0xff;
719 bec->rxerr = (reg >> 8) & 0xff;
720
721 return 0;
722 }
723
flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)724 static int flexcan_get_berr_counter(const struct net_device *dev,
725 struct can_berr_counter *bec)
726 {
727 const struct flexcan_priv *priv = netdev_priv(dev);
728 int err;
729
730 err = pm_runtime_get_sync(priv->dev);
731 if (err < 0) {
732 pm_runtime_put_noidle(priv->dev);
733 return err;
734 }
735
736 err = __flexcan_get_berr_counter(dev, bec);
737
738 pm_runtime_put(priv->dev);
739
740 return err;
741 }
742
flexcan_start_xmit(struct sk_buff * skb,struct net_device * dev)743 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
744 {
745 const struct flexcan_priv *priv = netdev_priv(dev);
746 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
747 u32 can_id;
748 u32 data;
749 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
750 int i;
751
752 if (can_dropped_invalid_skb(dev, skb))
753 return NETDEV_TX_OK;
754
755 netif_stop_queue(dev);
756
757 if (cfd->can_id & CAN_EFF_FLAG) {
758 can_id = cfd->can_id & CAN_EFF_MASK;
759 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
760 } else {
761 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
762 }
763
764 if (cfd->can_id & CAN_RTR_FLAG)
765 ctrl |= FLEXCAN_MB_CNT_RTR;
766
767 if (can_is_canfd_skb(skb)) {
768 ctrl |= FLEXCAN_MB_CNT_EDL;
769
770 if (cfd->flags & CANFD_BRS)
771 ctrl |= FLEXCAN_MB_CNT_BRS;
772 }
773
774 for (i = 0; i < cfd->len; i += sizeof(u32)) {
775 data = be32_to_cpup((__be32 *)&cfd->data[i]);
776 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
777 }
778
779 can_put_echo_skb(skb, dev, 0);
780
781 priv->write(can_id, &priv->tx_mb->can_id);
782 priv->write(ctrl, &priv->tx_mb->can_ctrl);
783
784 /* Errata ERR005829 step8:
785 * Write twice INACTIVE(0x8) code to first MB.
786 */
787 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
788 &priv->tx_mb_reserved->can_ctrl);
789 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
790 &priv->tx_mb_reserved->can_ctrl);
791
792 return NETDEV_TX_OK;
793 }
794
flexcan_irq_bus_err(struct net_device * dev,u32 reg_esr)795 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
796 {
797 struct flexcan_priv *priv = netdev_priv(dev);
798 struct flexcan_regs __iomem *regs = priv->regs;
799 struct sk_buff *skb;
800 struct can_frame *cf;
801 bool rx_errors = false, tx_errors = false;
802 u32 timestamp;
803 int err;
804
805 timestamp = priv->read(®s->timer) << 16;
806
807 skb = alloc_can_err_skb(dev, &cf);
808 if (unlikely(!skb))
809 return;
810
811 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
812
813 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
814 netdev_dbg(dev, "BIT1_ERR irq\n");
815 cf->data[2] |= CAN_ERR_PROT_BIT1;
816 tx_errors = true;
817 }
818 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
819 netdev_dbg(dev, "BIT0_ERR irq\n");
820 cf->data[2] |= CAN_ERR_PROT_BIT0;
821 tx_errors = true;
822 }
823 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
824 netdev_dbg(dev, "ACK_ERR irq\n");
825 cf->can_id |= CAN_ERR_ACK;
826 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
827 tx_errors = true;
828 }
829 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
830 netdev_dbg(dev, "CRC_ERR irq\n");
831 cf->data[2] |= CAN_ERR_PROT_BIT;
832 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
833 rx_errors = true;
834 }
835 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
836 netdev_dbg(dev, "FRM_ERR irq\n");
837 cf->data[2] |= CAN_ERR_PROT_FORM;
838 rx_errors = true;
839 }
840 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
841 netdev_dbg(dev, "STF_ERR irq\n");
842 cf->data[2] |= CAN_ERR_PROT_STUFF;
843 rx_errors = true;
844 }
845
846 priv->can.can_stats.bus_error++;
847 if (rx_errors)
848 dev->stats.rx_errors++;
849 if (tx_errors)
850 dev->stats.tx_errors++;
851
852 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
853 if (err)
854 dev->stats.rx_fifo_errors++;
855 }
856
flexcan_irq_state(struct net_device * dev,u32 reg_esr)857 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
858 {
859 struct flexcan_priv *priv = netdev_priv(dev);
860 struct flexcan_regs __iomem *regs = priv->regs;
861 struct sk_buff *skb;
862 struct can_frame *cf;
863 enum can_state new_state, rx_state, tx_state;
864 int flt;
865 struct can_berr_counter bec;
866 u32 timestamp;
867 int err;
868
869 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
870 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
871 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
872 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
873 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
874 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
875 new_state = max(tx_state, rx_state);
876 } else {
877 __flexcan_get_berr_counter(dev, &bec);
878 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
879 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
880 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
881 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
882 }
883
884 /* state hasn't changed */
885 if (likely(new_state == priv->can.state))
886 return;
887
888 timestamp = priv->read(®s->timer) << 16;
889
890 skb = alloc_can_err_skb(dev, &cf);
891 if (unlikely(!skb))
892 return;
893
894 can_change_state(dev, cf, tx_state, rx_state);
895
896 if (unlikely(new_state == CAN_STATE_BUS_OFF))
897 can_bus_off(dev);
898
899 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
900 if (err)
901 dev->stats.rx_fifo_errors++;
902 }
903
flexcan_read64_mask(struct flexcan_priv * priv,void __iomem * addr,u64 mask)904 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
905 {
906 u64 reg = 0;
907
908 if (upper_32_bits(mask))
909 reg = (u64)priv->read(addr - 4) << 32;
910 if (lower_32_bits(mask))
911 reg |= priv->read(addr);
912
913 return reg & mask;
914 }
915
flexcan_write64(struct flexcan_priv * priv,u64 val,void __iomem * addr)916 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
917 {
918 if (upper_32_bits(val))
919 priv->write(upper_32_bits(val), addr - 4);
920 if (lower_32_bits(val))
921 priv->write(lower_32_bits(val), addr);
922 }
923
flexcan_read_reg_iflag_rx(struct flexcan_priv * priv)924 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
925 {
926 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
927 }
928
flexcan_read_reg_iflag_tx(struct flexcan_priv * priv)929 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
930 {
931 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
932 }
933
rx_offload_to_priv(struct can_rx_offload * offload)934 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
935 {
936 return container_of(offload, struct flexcan_priv, offload);
937 }
938
flexcan_mailbox_read(struct can_rx_offload * offload,unsigned int n,u32 * timestamp,bool drop)939 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
940 unsigned int n, u32 *timestamp,
941 bool drop)
942 {
943 struct flexcan_priv *priv = rx_offload_to_priv(offload);
944 struct flexcan_regs __iomem *regs = priv->regs;
945 struct flexcan_mb __iomem *mb;
946 struct sk_buff *skb;
947 struct canfd_frame *cfd;
948 u32 reg_ctrl, reg_id, reg_iflag1;
949 int i;
950
951 if (unlikely(drop)) {
952 skb = ERR_PTR(-ENOBUFS);
953 goto mark_as_read;
954 }
955
956 mb = flexcan_get_mb(priv, n);
957
958 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
959 u32 code;
960
961 do {
962 reg_ctrl = priv->read(&mb->can_ctrl);
963 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
964
965 /* is this MB empty? */
966 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
967 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
968 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
969 return NULL;
970
971 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
972 /* This MB was overrun, we lost data */
973 offload->dev->stats.rx_over_errors++;
974 offload->dev->stats.rx_errors++;
975 }
976 } else {
977 reg_iflag1 = priv->read(®s->iflag1);
978 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
979 return NULL;
980
981 reg_ctrl = priv->read(&mb->can_ctrl);
982 }
983
984 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
985 skb = alloc_canfd_skb(offload->dev, &cfd);
986 else
987 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
988 if (unlikely(!skb)) {
989 skb = ERR_PTR(-ENOMEM);
990 goto mark_as_read;
991 }
992
993 /* increase timstamp to full 32 bit */
994 *timestamp = reg_ctrl << 16;
995
996 reg_id = priv->read(&mb->can_id);
997 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
998 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
999 else
1000 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1001
1002 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1003 cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
1004
1005 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1006 cfd->flags |= CANFD_BRS;
1007 } else {
1008 cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);
1009
1010 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1011 cfd->can_id |= CAN_RTR_FLAG;
1012 }
1013
1014 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1015 cfd->flags |= CANFD_ESI;
1016
1017 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1018 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1019 *(__be32 *)(cfd->data + i) = data;
1020 }
1021
1022 mark_as_read:
1023 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1024 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1025 else
1026 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1027
1028 /* Read the Free Running Timer. It is optional but recommended
1029 * to unlock Mailbox as soon as possible and make it available
1030 * for reception.
1031 */
1032 priv->read(®s->timer);
1033
1034 return skb;
1035 }
1036
flexcan_irq(int irq,void * dev_id)1037 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1038 {
1039 struct net_device *dev = dev_id;
1040 struct net_device_stats *stats = &dev->stats;
1041 struct flexcan_priv *priv = netdev_priv(dev);
1042 struct flexcan_regs __iomem *regs = priv->regs;
1043 irqreturn_t handled = IRQ_NONE;
1044 u64 reg_iflag_tx;
1045 u32 reg_esr;
1046 enum can_state last_state = priv->can.state;
1047
1048 /* reception interrupt */
1049 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1050 u64 reg_iflag_rx;
1051 int ret;
1052
1053 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1054 handled = IRQ_HANDLED;
1055 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1056 reg_iflag_rx);
1057 if (!ret)
1058 break;
1059 }
1060 } else {
1061 u32 reg_iflag1;
1062
1063 reg_iflag1 = priv->read(®s->iflag1);
1064 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1065 handled = IRQ_HANDLED;
1066 can_rx_offload_irq_offload_fifo(&priv->offload);
1067 }
1068
1069 /* FIFO overflow interrupt */
1070 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1071 handled = IRQ_HANDLED;
1072 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1073 ®s->iflag1);
1074 dev->stats.rx_over_errors++;
1075 dev->stats.rx_errors++;
1076 }
1077 }
1078
1079 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1080
1081 /* transmission complete interrupt */
1082 if (reg_iflag_tx & priv->tx_mask) {
1083 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1084
1085 handled = IRQ_HANDLED;
1086 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
1087 0, reg_ctrl << 16);
1088 stats->tx_packets++;
1089 can_led_event(dev, CAN_LED_EVENT_TX);
1090
1091 /* after sending a RTR frame MB is in RX mode */
1092 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1093 &priv->tx_mb->can_ctrl);
1094 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1095 netif_wake_queue(dev);
1096 }
1097
1098 reg_esr = priv->read(®s->esr);
1099
1100 /* ACK all bus error, state change and wake IRQ sources */
1101 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1102 handled = IRQ_HANDLED;
1103 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1104 }
1105
1106 /* state change interrupt or broken error state quirk fix is enabled */
1107 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1108 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1109 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1110 flexcan_irq_state(dev, reg_esr);
1111
1112 /* bus error IRQ - handle if bus error reporting is activated */
1113 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1114 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1115 flexcan_irq_bus_err(dev, reg_esr);
1116
1117 /* availability of error interrupt among state transitions in case
1118 * bus error reporting is de-activated and
1119 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1120 * +--------------------------------------------------------------+
1121 * | +----------------------------------------------+ [stopped / |
1122 * | | | sleeping] -+
1123 * +-+-> active <-> warning <-> passive -> bus off -+
1124 * ___________^^^^^^^^^^^^_______________________________
1125 * disabled(1) enabled disabled
1126 *
1127 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1128 */
1129 if ((last_state != priv->can.state) &&
1130 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1131 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1132 switch (priv->can.state) {
1133 case CAN_STATE_ERROR_ACTIVE:
1134 if (priv->devtype_data->quirks &
1135 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1136 flexcan_error_irq_enable(priv);
1137 else
1138 flexcan_error_irq_disable(priv);
1139 break;
1140
1141 case CAN_STATE_ERROR_WARNING:
1142 flexcan_error_irq_enable(priv);
1143 break;
1144
1145 case CAN_STATE_ERROR_PASSIVE:
1146 case CAN_STATE_BUS_OFF:
1147 flexcan_error_irq_disable(priv);
1148 break;
1149
1150 default:
1151 break;
1152 }
1153 }
1154
1155 return handled;
1156 }
1157
flexcan_set_bittiming_ctrl(const struct net_device * dev)1158 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1159 {
1160 const struct flexcan_priv *priv = netdev_priv(dev);
1161 const struct can_bittiming *bt = &priv->can.bittiming;
1162 struct flexcan_regs __iomem *regs = priv->regs;
1163 u32 reg;
1164
1165 reg = priv->read(®s->ctrl);
1166 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1167 FLEXCAN_CTRL_RJW(0x3) |
1168 FLEXCAN_CTRL_PSEG1(0x7) |
1169 FLEXCAN_CTRL_PSEG2(0x7) |
1170 FLEXCAN_CTRL_PROPSEG(0x7));
1171
1172 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1173 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1174 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1175 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1176 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1177
1178 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1179 priv->write(reg, ®s->ctrl);
1180
1181 /* print chip status */
1182 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1183 priv->read(®s->mcr), priv->read(®s->ctrl));
1184 }
1185
flexcan_set_bittiming_cbt(const struct net_device * dev)1186 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1187 {
1188 struct flexcan_priv *priv = netdev_priv(dev);
1189 struct can_bittiming *bt = &priv->can.bittiming;
1190 struct can_bittiming *dbt = &priv->can.data_bittiming;
1191 struct flexcan_regs __iomem *regs = priv->regs;
1192 u32 reg_cbt, reg_fdctrl;
1193
1194 /* CBT */
1195 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1196 * long. The can_calc_bittiming() tries to divide the tseg1
1197 * equally between phase_seg1 and prop_seg, which may not fit
1198 * in CBT register. Therefore, if phase_seg1 is more than
1199 * possible value, increase prop_seg and decrease phase_seg1.
1200 */
1201 if (bt->phase_seg1 > 0x20) {
1202 bt->prop_seg += (bt->phase_seg1 - 0x20);
1203 bt->phase_seg1 = 0x20;
1204 }
1205
1206 reg_cbt = FLEXCAN_CBT_BTF |
1207 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1208 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1209 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1210 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1211 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1212
1213 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1214 priv->write(reg_cbt, ®s->cbt);
1215
1216 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1217 u32 reg_fdcbt, reg_ctrl2;
1218
1219 if (bt->brp != dbt->brp)
1220 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1221 dbt->brp, bt->brp);
1222
1223 /* FDCBT */
1224 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1225 * 5 bit long. The can_calc_bittiming tries to divide
1226 * the tseg1 equally between phase_seg1 and prop_seg,
1227 * which may not fit in FDCBT register. Therefore, if
1228 * phase_seg1 is more than possible value, increase
1229 * prop_seg and decrease phase_seg1
1230 */
1231 if (dbt->phase_seg1 > 0x8) {
1232 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1233 dbt->phase_seg1 = 0x8;
1234 }
1235
1236 reg_fdcbt = priv->read(®s->fdcbt);
1237 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1238 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1239 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1240 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1241 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1242
1243 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1244 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1245 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1246 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1247 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1248
1249 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1250 priv->write(reg_fdcbt, ®s->fdcbt);
1251
1252 /* CTRL2 */
1253 reg_ctrl2 = priv->read(®s->ctrl2);
1254 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1255 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1256 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1257
1258 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1259 priv->write(reg_ctrl2, ®s->ctrl2);
1260 }
1261
1262 /* FDCTRL */
1263 reg_fdctrl = priv->read(®s->fdctrl);
1264 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1265 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1266
1267 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1268 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1269
1270 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1271 /* TDC must be disabled for Loop Back mode */
1272 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1273 } else {
1274 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1275 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1276 ((dbt->phase_seg1 - 1) +
1277 dbt->prop_seg + 2) *
1278 ((dbt->brp - 1 ) + 1));
1279 }
1280 }
1281
1282 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1283 priv->write(reg_fdctrl, ®s->fdctrl);
1284
1285 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1286 __func__,
1287 priv->read(®s->mcr), priv->read(®s->ctrl),
1288 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1289 priv->read(®s->cbt), priv->read(®s->fdcbt));
1290 }
1291
flexcan_set_bittiming(struct net_device * dev)1292 static void flexcan_set_bittiming(struct net_device *dev)
1293 {
1294 const struct flexcan_priv *priv = netdev_priv(dev);
1295 struct flexcan_regs __iomem *regs = priv->regs;
1296 u32 reg;
1297
1298 reg = priv->read(®s->ctrl);
1299 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1300 FLEXCAN_CTRL_LOM);
1301
1302 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1303 reg |= FLEXCAN_CTRL_LPB;
1304 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1305 reg |= FLEXCAN_CTRL_LOM;
1306 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1307 reg |= FLEXCAN_CTRL_SMP;
1308
1309 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1310 priv->write(reg, ®s->ctrl);
1311
1312 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1313 return flexcan_set_bittiming_cbt(dev);
1314 else
1315 return flexcan_set_bittiming_ctrl(dev);
1316 }
1317
flexcan_ram_init(struct net_device * dev)1318 static void flexcan_ram_init(struct net_device *dev)
1319 {
1320 struct flexcan_priv *priv = netdev_priv(dev);
1321 struct flexcan_regs __iomem *regs = priv->regs;
1322 u32 reg_ctrl2;
1323
1324 /* 11.8.3.13 Detection and correction of memory errors:
1325 * CTRL2[WRMFRZ] grants write access to all memory positions
1326 * that require initialization, ranging from 0x080 to 0xADF
1327 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1328 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1329 * need to be initialized as well. MCR[RFEN] must not be set
1330 * during memory initialization.
1331 */
1332 reg_ctrl2 = priv->read(®s->ctrl2);
1333 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1334 priv->write(reg_ctrl2, ®s->ctrl2);
1335
1336 memset_io(®s->mb[0][0], 0,
1337 offsetof(struct flexcan_regs, rx_smb1[3]) -
1338 offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1339
1340 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1341 memset_io(®s->tx_smb_fd[0], 0,
1342 offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1343 offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1344
1345 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1346 priv->write(reg_ctrl2, ®s->ctrl2);
1347 }
1348
1349 /* flexcan_chip_start
1350 *
1351 * this functions is entered with clocks enabled
1352 *
1353 */
flexcan_chip_start(struct net_device * dev)1354 static int flexcan_chip_start(struct net_device *dev)
1355 {
1356 struct flexcan_priv *priv = netdev_priv(dev);
1357 struct flexcan_regs __iomem *regs = priv->regs;
1358 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1359 u64 reg_imask;
1360 int err, i;
1361 struct flexcan_mb __iomem *mb;
1362
1363 /* enable module */
1364 err = flexcan_chip_enable(priv);
1365 if (err)
1366 return err;
1367
1368 /* soft reset */
1369 err = flexcan_chip_softreset(priv);
1370 if (err)
1371 goto out_chip_disable;
1372
1373 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1374 flexcan_ram_init(dev);
1375
1376 flexcan_set_bittiming(dev);
1377
1378 /* MCR
1379 *
1380 * enable freeze
1381 * halt now
1382 * only supervisor access
1383 * enable warning int
1384 * enable individual RX masking
1385 * choose format C
1386 * set max mailbox number
1387 */
1388 reg_mcr = priv->read(®s->mcr);
1389 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1390 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1391 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1392 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1393
1394 /* MCR
1395 *
1396 * FIFO:
1397 * - disable for timestamp mode
1398 * - enable for FIFO mode
1399 */
1400 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1401 reg_mcr &= ~FLEXCAN_MCR_FEN;
1402 else
1403 reg_mcr |= FLEXCAN_MCR_FEN;
1404
1405 /* MCR
1406 *
1407 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1408 * asserted because this will impede the self reception
1409 * of a transmitted message. This is not documented in
1410 * earlier versions of flexcan block guide.
1411 *
1412 * Self Reception:
1413 * - enable Self Reception for loopback mode
1414 * (by clearing "Self Reception Disable" bit)
1415 * - disable for normal operation
1416 */
1417 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1418 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1419 else
1420 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1421
1422 /* MCR - CAN-FD */
1423 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1424 reg_mcr |= FLEXCAN_MCR_FDEN;
1425 else
1426 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1427
1428 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1429 priv->write(reg_mcr, ®s->mcr);
1430
1431 /* CTRL
1432 *
1433 * disable timer sync feature
1434 *
1435 * disable auto busoff recovery
1436 * transmit lowest buffer first
1437 *
1438 * enable tx and rx warning interrupt
1439 * enable bus off interrupt
1440 * (== FLEXCAN_CTRL_ERR_STATE)
1441 */
1442 reg_ctrl = priv->read(®s->ctrl);
1443 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1444 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1445 FLEXCAN_CTRL_ERR_STATE;
1446
1447 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1448 * on most Flexcan cores, too. Otherwise we don't get
1449 * any error warning or passive interrupts.
1450 */
1451 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1452 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1453 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1454 else
1455 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1456
1457 /* save for later use */
1458 priv->reg_ctrl_default = reg_ctrl;
1459 /* leave interrupts disabled for now */
1460 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1461 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1462 priv->write(reg_ctrl, ®s->ctrl);
1463
1464 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1465 reg_ctrl2 = priv->read(®s->ctrl2);
1466 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1467 priv->write(reg_ctrl2, ®s->ctrl2);
1468 }
1469
1470 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1471 u32 reg_fdctrl;
1472
1473 reg_fdctrl = priv->read(®s->fdctrl);
1474 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1475 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1476
1477 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1478 reg_fdctrl |=
1479 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1480 FLEXCAN_FDCTRL_MBDSR_64) |
1481 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1482 FLEXCAN_FDCTRL_MBDSR_64);
1483 } else {
1484 reg_fdctrl |=
1485 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1486 FLEXCAN_FDCTRL_MBDSR_8) |
1487 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1488 FLEXCAN_FDCTRL_MBDSR_8);
1489 }
1490
1491 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1492 __func__, reg_fdctrl);
1493 priv->write(reg_fdctrl, ®s->fdctrl);
1494 }
1495
1496 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1497 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1498 mb = flexcan_get_mb(priv, i);
1499 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1500 &mb->can_ctrl);
1501 }
1502 } else {
1503 /* clear and invalidate unused mailboxes first */
1504 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1505 mb = flexcan_get_mb(priv, i);
1506 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1507 &mb->can_ctrl);
1508 }
1509 }
1510
1511 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1512 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1513 &priv->tx_mb_reserved->can_ctrl);
1514
1515 /* mark TX mailbox as INACTIVE */
1516 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1517 &priv->tx_mb->can_ctrl);
1518
1519 /* acceptance mask/acceptance code (accept everything) */
1520 priv->write(0x0, ®s->rxgmask);
1521 priv->write(0x0, ®s->rx14mask);
1522 priv->write(0x0, ®s->rx15mask);
1523
1524 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1525 priv->write(0x0, ®s->rxfgmask);
1526
1527 /* clear acceptance filters */
1528 for (i = 0; i < priv->mb_count; i++)
1529 priv->write(0, ®s->rximr[i]);
1530
1531 /* On Vybrid, disable non-correctable errors interrupt and
1532 * freeze mode. It still can correct the correctable errors
1533 * when HW supports ECC.
1534 *
1535 * This also works around errata e5295 which generates false
1536 * positive memory errors and put the device in freeze mode.
1537 */
1538 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1539 /* Follow the protocol as described in "Detection
1540 * and Correction of Memory Errors" to write to
1541 * MECR register (step 1 - 5)
1542 *
1543 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1544 * 2. set CTRL2[ECRWRE]
1545 */
1546 reg_ctrl2 = priv->read(®s->ctrl2);
1547 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1548 priv->write(reg_ctrl2, ®s->ctrl2);
1549
1550 /* 3. clear MECR[ECRWRDIS] */
1551 reg_mecr = priv->read(®s->mecr);
1552 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1553 priv->write(reg_mecr, ®s->mecr);
1554
1555 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1556 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1557 FLEXCAN_MECR_FANCEI_MSK);
1558 priv->write(reg_mecr, ®s->mecr);
1559
1560 /* 5. after configuration done, lock MECR by either
1561 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1562 */
1563 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1564 priv->write(reg_mecr, ®s->mecr);
1565
1566 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1567 priv->write(reg_ctrl2, ®s->ctrl2);
1568 }
1569
1570 /* synchronize with the can bus */
1571 err = flexcan_chip_unfreeze(priv);
1572 if (err)
1573 goto out_chip_disable;
1574
1575 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1576
1577 /* enable interrupts atomically */
1578 disable_irq(dev->irq);
1579 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1580 reg_imask = priv->rx_mask | priv->tx_mask;
1581 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1582 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1583 enable_irq(dev->irq);
1584
1585 /* print chip status */
1586 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1587 priv->read(®s->mcr), priv->read(®s->ctrl));
1588
1589 return 0;
1590
1591 out_chip_disable:
1592 flexcan_chip_disable(priv);
1593 return err;
1594 }
1595
1596 /* __flexcan_chip_stop
1597 *
1598 * this function is entered with clocks enabled
1599 */
__flexcan_chip_stop(struct net_device * dev,bool disable_on_error)1600 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1601 {
1602 struct flexcan_priv *priv = netdev_priv(dev);
1603 struct flexcan_regs __iomem *regs = priv->regs;
1604 int err;
1605
1606 /* freeze + disable module */
1607 err = flexcan_chip_freeze(priv);
1608 if (err && !disable_on_error)
1609 return err;
1610 err = flexcan_chip_disable(priv);
1611 if (err && !disable_on_error)
1612 goto out_chip_unfreeze;
1613
1614 /* Disable all interrupts */
1615 priv->write(0, ®s->imask2);
1616 priv->write(0, ®s->imask1);
1617 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1618 ®s->ctrl);
1619
1620 priv->can.state = CAN_STATE_STOPPED;
1621
1622 return 0;
1623
1624 out_chip_unfreeze:
1625 flexcan_chip_unfreeze(priv);
1626
1627 return err;
1628 }
1629
flexcan_chip_stop_disable_on_error(struct net_device * dev)1630 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1631 {
1632 return __flexcan_chip_stop(dev, true);
1633 }
1634
flexcan_chip_stop(struct net_device * dev)1635 static inline int flexcan_chip_stop(struct net_device *dev)
1636 {
1637 return __flexcan_chip_stop(dev, false);
1638 }
1639
flexcan_open(struct net_device * dev)1640 static int flexcan_open(struct net_device *dev)
1641 {
1642 struct flexcan_priv *priv = netdev_priv(dev);
1643 int err;
1644
1645 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1646 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1647 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1648 return -EINVAL;
1649 }
1650
1651 err = pm_runtime_get_sync(priv->dev);
1652 if (err < 0) {
1653 pm_runtime_put_noidle(priv->dev);
1654 return err;
1655 }
1656
1657 err = open_candev(dev);
1658 if (err)
1659 goto out_runtime_put;
1660
1661 err = flexcan_transceiver_enable(priv);
1662 if (err)
1663 goto out_close;
1664
1665 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1666 if (err)
1667 goto out_transceiver_disable;
1668
1669 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1670 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1671 else
1672 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1673 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1674 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1675
1676 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1677 priv->tx_mb_reserved =
1678 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1679 else
1680 priv->tx_mb_reserved =
1681 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1682 priv->tx_mb_idx = priv->mb_count - 1;
1683 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1684 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1685
1686 priv->offload.mailbox_read = flexcan_mailbox_read;
1687
1688 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1689 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1690 priv->offload.mb_last = priv->mb_count - 2;
1691
1692 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1693 priv->offload.mb_first);
1694 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1695 } else {
1696 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1697 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1698 err = can_rx_offload_add_fifo(dev, &priv->offload,
1699 FLEXCAN_NAPI_WEIGHT);
1700 }
1701 if (err)
1702 goto out_free_irq;
1703
1704 /* start chip and queuing */
1705 err = flexcan_chip_start(dev);
1706 if (err)
1707 goto out_offload_del;
1708
1709 can_led_event(dev, CAN_LED_EVENT_OPEN);
1710
1711 can_rx_offload_enable(&priv->offload);
1712 netif_start_queue(dev);
1713
1714 return 0;
1715
1716 out_offload_del:
1717 can_rx_offload_del(&priv->offload);
1718 out_free_irq:
1719 free_irq(dev->irq, dev);
1720 out_transceiver_disable:
1721 flexcan_transceiver_disable(priv);
1722 out_close:
1723 close_candev(dev);
1724 out_runtime_put:
1725 pm_runtime_put(priv->dev);
1726
1727 return err;
1728 }
1729
flexcan_close(struct net_device * dev)1730 static int flexcan_close(struct net_device *dev)
1731 {
1732 struct flexcan_priv *priv = netdev_priv(dev);
1733
1734 netif_stop_queue(dev);
1735 can_rx_offload_disable(&priv->offload);
1736 flexcan_chip_stop_disable_on_error(dev);
1737
1738 can_rx_offload_del(&priv->offload);
1739 free_irq(dev->irq, dev);
1740 flexcan_transceiver_disable(priv);
1741
1742 close_candev(dev);
1743 pm_runtime_put(priv->dev);
1744
1745 can_led_event(dev, CAN_LED_EVENT_STOP);
1746
1747 return 0;
1748 }
1749
flexcan_set_mode(struct net_device * dev,enum can_mode mode)1750 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1751 {
1752 int err;
1753
1754 switch (mode) {
1755 case CAN_MODE_START:
1756 err = flexcan_chip_start(dev);
1757 if (err)
1758 return err;
1759
1760 netif_wake_queue(dev);
1761 break;
1762
1763 default:
1764 return -EOPNOTSUPP;
1765 }
1766
1767 return 0;
1768 }
1769
1770 static const struct net_device_ops flexcan_netdev_ops = {
1771 .ndo_open = flexcan_open,
1772 .ndo_stop = flexcan_close,
1773 .ndo_start_xmit = flexcan_start_xmit,
1774 .ndo_change_mtu = can_change_mtu,
1775 };
1776
register_flexcandev(struct net_device * dev)1777 static int register_flexcandev(struct net_device *dev)
1778 {
1779 struct flexcan_priv *priv = netdev_priv(dev);
1780 struct flexcan_regs __iomem *regs = priv->regs;
1781 u32 reg, err;
1782
1783 err = flexcan_clks_enable(priv);
1784 if (err)
1785 return err;
1786
1787 /* select "bus clock", chip must be disabled */
1788 err = flexcan_chip_disable(priv);
1789 if (err)
1790 goto out_clks_disable;
1791
1792 reg = priv->read(®s->ctrl);
1793 if (priv->clk_src)
1794 reg |= FLEXCAN_CTRL_CLK_SRC;
1795 else
1796 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1797 priv->write(reg, ®s->ctrl);
1798
1799 err = flexcan_chip_enable(priv);
1800 if (err)
1801 goto out_chip_disable;
1802
1803 /* set freeze, halt and activate FIFO, restrict register access */
1804 reg = priv->read(®s->mcr);
1805 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1806 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1807 priv->write(reg, ®s->mcr);
1808
1809 /* Currently we only support newer versions of this core
1810 * featuring a RX hardware FIFO (although this driver doesn't
1811 * make use of it on some cores). Older cores, found on some
1812 * Coldfire derivates are not tested.
1813 */
1814 reg = priv->read(®s->mcr);
1815 if (!(reg & FLEXCAN_MCR_FEN)) {
1816 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1817 err = -ENODEV;
1818 goto out_chip_disable;
1819 }
1820
1821 err = register_candev(dev);
1822 if (err)
1823 goto out_chip_disable;
1824
1825 /* Disable core and let pm_runtime_put() disable the clocks.
1826 * If CONFIG_PM is not enabled, the clocks will stay powered.
1827 */
1828 flexcan_chip_disable(priv);
1829 pm_runtime_put(priv->dev);
1830
1831 return 0;
1832
1833 out_chip_disable:
1834 flexcan_chip_disable(priv);
1835 out_clks_disable:
1836 flexcan_clks_disable(priv);
1837 return err;
1838 }
1839
unregister_flexcandev(struct net_device * dev)1840 static void unregister_flexcandev(struct net_device *dev)
1841 {
1842 unregister_candev(dev);
1843 }
1844
flexcan_setup_stop_mode(struct platform_device * pdev)1845 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1846 {
1847 struct net_device *dev = platform_get_drvdata(pdev);
1848 struct device_node *np = pdev->dev.of_node;
1849 struct device_node *gpr_np;
1850 struct flexcan_priv *priv;
1851 phandle phandle;
1852 u32 out_val[3];
1853 int ret;
1854
1855 if (!np)
1856 return -EINVAL;
1857
1858 /* stop mode property format is:
1859 * <&gpr req_gpr req_bit>.
1860 */
1861 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1862 ARRAY_SIZE(out_val));
1863 if (ret) {
1864 dev_dbg(&pdev->dev, "no stop-mode property\n");
1865 return ret;
1866 }
1867 phandle = *out_val;
1868
1869 gpr_np = of_find_node_by_phandle(phandle);
1870 if (!gpr_np) {
1871 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1872 return -ENODEV;
1873 }
1874
1875 priv = netdev_priv(dev);
1876 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1877 if (IS_ERR(priv->stm.gpr)) {
1878 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1879 ret = PTR_ERR(priv->stm.gpr);
1880 goto out_put_node;
1881 }
1882
1883 priv->stm.req_gpr = out_val[1];
1884 priv->stm.req_bit = out_val[2];
1885
1886 dev_dbg(&pdev->dev,
1887 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1888 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1889
1890 device_set_wakeup_capable(&pdev->dev, true);
1891
1892 if (of_property_read_bool(np, "wakeup-source"))
1893 device_set_wakeup_enable(&pdev->dev, true);
1894
1895 return 0;
1896
1897 out_put_node:
1898 of_node_put(gpr_np);
1899 return ret;
1900 }
1901
1902 static const struct of_device_id flexcan_of_match[] = {
1903 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
1904 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
1905 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1906 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1907 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1908 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1909 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1910 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1911 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1912 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1913 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
1914 { /* sentinel */ },
1915 };
1916 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1917
1918 static const struct platform_device_id flexcan_id_table[] = {
1919 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1920 { /* sentinel */ },
1921 };
1922 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1923
flexcan_probe(struct platform_device * pdev)1924 static int flexcan_probe(struct platform_device *pdev)
1925 {
1926 const struct of_device_id *of_id;
1927 const struct flexcan_devtype_data *devtype_data;
1928 struct net_device *dev;
1929 struct flexcan_priv *priv;
1930 struct regulator *reg_xceiver;
1931 struct clk *clk_ipg = NULL, *clk_per = NULL;
1932 struct flexcan_regs __iomem *regs;
1933 int err, irq;
1934 u8 clk_src = 1;
1935 u32 clock_freq = 0;
1936
1937 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
1938 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1939 return -EPROBE_DEFER;
1940 else if (PTR_ERR(reg_xceiver) == -ENODEV)
1941 reg_xceiver = NULL;
1942 else if (IS_ERR(reg_xceiver))
1943 return PTR_ERR(reg_xceiver);
1944
1945 if (pdev->dev.of_node) {
1946 of_property_read_u32(pdev->dev.of_node,
1947 "clock-frequency", &clock_freq);
1948 of_property_read_u8(pdev->dev.of_node,
1949 "fsl,clk-source", &clk_src);
1950 }
1951
1952 if (!clock_freq) {
1953 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1954 if (IS_ERR(clk_ipg)) {
1955 dev_err(&pdev->dev, "no ipg clock defined\n");
1956 return PTR_ERR(clk_ipg);
1957 }
1958
1959 clk_per = devm_clk_get(&pdev->dev, "per");
1960 if (IS_ERR(clk_per)) {
1961 dev_err(&pdev->dev, "no per clock defined\n");
1962 return PTR_ERR(clk_per);
1963 }
1964 clock_freq = clk_get_rate(clk_per);
1965 }
1966
1967 irq = platform_get_irq(pdev, 0);
1968 if (irq <= 0)
1969 return -ENODEV;
1970
1971 regs = devm_platform_ioremap_resource(pdev, 0);
1972 if (IS_ERR(regs))
1973 return PTR_ERR(regs);
1974
1975 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1976 if (of_id) {
1977 devtype_data = of_id->data;
1978 } else if (platform_get_device_id(pdev)->driver_data) {
1979 devtype_data = (struct flexcan_devtype_data *)
1980 platform_get_device_id(pdev)->driver_data;
1981 } else {
1982 return -ENODEV;
1983 }
1984
1985 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
1986 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
1987 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
1988 return -EINVAL;
1989 }
1990
1991 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1992 if (!dev)
1993 return -ENOMEM;
1994
1995 platform_set_drvdata(pdev, dev);
1996 SET_NETDEV_DEV(dev, &pdev->dev);
1997
1998 dev->netdev_ops = &flexcan_netdev_ops;
1999 dev->irq = irq;
2000 dev->flags |= IFF_ECHO;
2001
2002 priv = netdev_priv(dev);
2003
2004 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2005 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2006 priv->read = flexcan_read_be;
2007 priv->write = flexcan_write_be;
2008 } else {
2009 priv->read = flexcan_read_le;
2010 priv->write = flexcan_write_le;
2011 }
2012
2013 priv->dev = &pdev->dev;
2014 priv->can.clock.freq = clock_freq;
2015 priv->can.do_set_mode = flexcan_set_mode;
2016 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2017 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2018 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2019 CAN_CTRLMODE_BERR_REPORTING;
2020 priv->regs = regs;
2021 priv->clk_ipg = clk_ipg;
2022 priv->clk_per = clk_per;
2023 priv->clk_src = clk_src;
2024 priv->devtype_data = devtype_data;
2025 priv->reg_xceiver = reg_xceiver;
2026
2027 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2028 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2029 CAN_CTRLMODE_FD_NON_ISO;
2030 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2031 priv->can.data_bittiming_const =
2032 &flexcan_fd_data_bittiming_const;
2033 } else {
2034 priv->can.bittiming_const = &flexcan_bittiming_const;
2035 }
2036
2037 pm_runtime_get_noresume(&pdev->dev);
2038 pm_runtime_set_active(&pdev->dev);
2039 pm_runtime_enable(&pdev->dev);
2040
2041 err = register_flexcandev(dev);
2042 if (err) {
2043 dev_err(&pdev->dev, "registering netdev failed\n");
2044 goto failed_register;
2045 }
2046
2047 of_can_transceiver(dev);
2048 devm_can_led_init(dev);
2049
2050 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
2051 err = flexcan_setup_stop_mode(pdev);
2052 if (err)
2053 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
2054 }
2055
2056 return 0;
2057
2058 failed_register:
2059 pm_runtime_put_noidle(&pdev->dev);
2060 pm_runtime_disable(&pdev->dev);
2061 free_candev(dev);
2062 return err;
2063 }
2064
flexcan_remove(struct platform_device * pdev)2065 static int flexcan_remove(struct platform_device *pdev)
2066 {
2067 struct net_device *dev = platform_get_drvdata(pdev);
2068
2069 device_set_wakeup_enable(&pdev->dev, false);
2070 device_set_wakeup_capable(&pdev->dev, false);
2071 unregister_flexcandev(dev);
2072 pm_runtime_disable(&pdev->dev);
2073 free_candev(dev);
2074
2075 return 0;
2076 }
2077
flexcan_suspend(struct device * device)2078 static int __maybe_unused flexcan_suspend(struct device *device)
2079 {
2080 struct net_device *dev = dev_get_drvdata(device);
2081 struct flexcan_priv *priv = netdev_priv(dev);
2082 int err;
2083
2084 if (netif_running(dev)) {
2085 /* if wakeup is enabled, enter stop mode
2086 * else enter disabled mode.
2087 */
2088 if (device_may_wakeup(device)) {
2089 enable_irq_wake(dev->irq);
2090 err = flexcan_enter_stop_mode(priv);
2091 if (err)
2092 return err;
2093 } else {
2094 err = flexcan_chip_stop(dev);
2095 if (err)
2096 return err;
2097
2098 err = pinctrl_pm_select_sleep_state(device);
2099 if (err)
2100 return err;
2101 }
2102 netif_stop_queue(dev);
2103 netif_device_detach(dev);
2104 }
2105 priv->can.state = CAN_STATE_SLEEPING;
2106
2107 return 0;
2108 }
2109
flexcan_resume(struct device * device)2110 static int __maybe_unused flexcan_resume(struct device *device)
2111 {
2112 struct net_device *dev = dev_get_drvdata(device);
2113 struct flexcan_priv *priv = netdev_priv(dev);
2114 int err;
2115
2116 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2117 if (netif_running(dev)) {
2118 netif_device_attach(dev);
2119 netif_start_queue(dev);
2120 if (device_may_wakeup(device)) {
2121 disable_irq_wake(dev->irq);
2122 err = flexcan_exit_stop_mode(priv);
2123 if (err)
2124 return err;
2125 } else {
2126 err = pinctrl_pm_select_default_state(device);
2127 if (err)
2128 return err;
2129
2130 err = flexcan_chip_start(dev);
2131 if (err)
2132 return err;
2133 }
2134 }
2135
2136 return 0;
2137 }
2138
flexcan_runtime_suspend(struct device * device)2139 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2140 {
2141 struct net_device *dev = dev_get_drvdata(device);
2142 struct flexcan_priv *priv = netdev_priv(dev);
2143
2144 flexcan_clks_disable(priv);
2145
2146 return 0;
2147 }
2148
flexcan_runtime_resume(struct device * device)2149 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2150 {
2151 struct net_device *dev = dev_get_drvdata(device);
2152 struct flexcan_priv *priv = netdev_priv(dev);
2153
2154 return flexcan_clks_enable(priv);
2155 }
2156
flexcan_noirq_suspend(struct device * device)2157 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2158 {
2159 struct net_device *dev = dev_get_drvdata(device);
2160 struct flexcan_priv *priv = netdev_priv(dev);
2161
2162 if (netif_running(dev)) {
2163 int err;
2164
2165 if (device_may_wakeup(device))
2166 flexcan_enable_wakeup_irq(priv, true);
2167
2168 err = pm_runtime_force_suspend(device);
2169 if (err)
2170 return err;
2171 }
2172
2173 return 0;
2174 }
2175
flexcan_noirq_resume(struct device * device)2176 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2177 {
2178 struct net_device *dev = dev_get_drvdata(device);
2179 struct flexcan_priv *priv = netdev_priv(dev);
2180
2181 if (netif_running(dev)) {
2182 int err;
2183
2184 err = pm_runtime_force_resume(device);
2185 if (err)
2186 return err;
2187
2188 if (device_may_wakeup(device))
2189 flexcan_enable_wakeup_irq(priv, false);
2190 }
2191
2192 return 0;
2193 }
2194
2195 static const struct dev_pm_ops flexcan_pm_ops = {
2196 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2197 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2198 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2199 };
2200
2201 static struct platform_driver flexcan_driver = {
2202 .driver = {
2203 .name = DRV_NAME,
2204 .pm = &flexcan_pm_ops,
2205 .of_match_table = flexcan_of_match,
2206 },
2207 .probe = flexcan_probe,
2208 .remove = flexcan_remove,
2209 .id_table = flexcan_id_table,
2210 };
2211
2212 module_platform_driver(flexcan_driver);
2213
2214 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2215 "Marc Kleine-Budde <kernel@pengutronix.de>");
2216 MODULE_LICENSE("GPL v2");
2217 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2218