1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 * Copyright 2009 Semihalf.
5 *
6 * Approved as OSADL project by a majority of OSADL members and funded
7 * by OSADL membership fees in 2009; for details see www.osadl.org.
8 *
9 * Based on original driver from Freescale Semiconductor
10 * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c.
11 * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>.
12 */
13
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/gfp.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/rawnand.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28
29 #include <asm/mpc5121.h>
30
31 /* Addresses for NFC MAIN RAM BUFFER areas */
32 #define NFC_MAIN_AREA(n) ((n) * 0x200)
33
34 /* Addresses for NFC SPARE BUFFER areas */
35 #define NFC_SPARE_BUFFERS 8
36 #define NFC_SPARE_LEN 0x40
37 #define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
38
39 /* MPC5121 NFC registers */
40 #define NFC_BUF_ADDR 0x1E04
41 #define NFC_FLASH_ADDR 0x1E06
42 #define NFC_FLASH_CMD 0x1E08
43 #define NFC_CONFIG 0x1E0A
44 #define NFC_ECC_STATUS1 0x1E0C
45 #define NFC_ECC_STATUS2 0x1E0E
46 #define NFC_SPAS 0x1E10
47 #define NFC_WRPROT 0x1E12
48 #define NFC_NF_WRPRST 0x1E18
49 #define NFC_CONFIG1 0x1E1A
50 #define NFC_CONFIG2 0x1E1C
51 #define NFC_UNLOCKSTART_BLK0 0x1E20
52 #define NFC_UNLOCKEND_BLK0 0x1E22
53 #define NFC_UNLOCKSTART_BLK1 0x1E24
54 #define NFC_UNLOCKEND_BLK1 0x1E26
55 #define NFC_UNLOCKSTART_BLK2 0x1E28
56 #define NFC_UNLOCKEND_BLK2 0x1E2A
57 #define NFC_UNLOCKSTART_BLK3 0x1E2C
58 #define NFC_UNLOCKEND_BLK3 0x1E2E
59
60 /* Bit Definitions: NFC_BUF_ADDR */
61 #define NFC_RBA_MASK (7 << 0)
62 #define NFC_ACTIVE_CS_SHIFT 5
63 #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
64
65 /* Bit Definitions: NFC_CONFIG */
66 #define NFC_BLS_UNLOCKED (1 << 1)
67
68 /* Bit Definitions: NFC_CONFIG1 */
69 #define NFC_ECC_4BIT (1 << 0)
70 #define NFC_FULL_PAGE_DMA (1 << 1)
71 #define NFC_SPARE_ONLY (1 << 2)
72 #define NFC_ECC_ENABLE (1 << 3)
73 #define NFC_INT_MASK (1 << 4)
74 #define NFC_BIG_ENDIAN (1 << 5)
75 #define NFC_RESET (1 << 6)
76 #define NFC_CE (1 << 7)
77 #define NFC_ONE_CYCLE (1 << 8)
78 #define NFC_PPB_32 (0 << 9)
79 #define NFC_PPB_64 (1 << 9)
80 #define NFC_PPB_128 (2 << 9)
81 #define NFC_PPB_256 (3 << 9)
82 #define NFC_PPB_MASK (3 << 9)
83 #define NFC_FULL_PAGE_INT (1 << 11)
84
85 /* Bit Definitions: NFC_CONFIG2 */
86 #define NFC_COMMAND (1 << 0)
87 #define NFC_ADDRESS (1 << 1)
88 #define NFC_INPUT (1 << 2)
89 #define NFC_OUTPUT (1 << 3)
90 #define NFC_ID (1 << 4)
91 #define NFC_STATUS (1 << 5)
92 #define NFC_CMD_FAIL (1 << 15)
93 #define NFC_INT (1 << 15)
94
95 /* Bit Definitions: NFC_WRPROT */
96 #define NFC_WPC_LOCK_TIGHT (1 << 0)
97 #define NFC_WPC_LOCK (1 << 1)
98 #define NFC_WPC_UNLOCK (1 << 2)
99
100 #define DRV_NAME "mpc5121_nfc"
101
102 /* Timeouts */
103 #define NFC_RESET_TIMEOUT 1000 /* 1 ms */
104 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
105
106 struct mpc5121_nfc_prv {
107 struct nand_controller controller;
108 struct nand_chip chip;
109 int irq;
110 void __iomem *regs;
111 struct clk *clk;
112 wait_queue_head_t irq_waitq;
113 uint column;
114 int spareonly;
115 void __iomem *csreg;
116 struct device *dev;
117 };
118
119 static void mpc5121_nfc_done(struct mtd_info *mtd);
120
121 /* Read NFC register */
nfc_read(struct mtd_info * mtd,uint reg)122 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
123 {
124 struct nand_chip *chip = mtd_to_nand(mtd);
125 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
126
127 return in_be16(prv->regs + reg);
128 }
129
130 /* Write NFC register */
nfc_write(struct mtd_info * mtd,uint reg,u16 val)131 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
132 {
133 struct nand_chip *chip = mtd_to_nand(mtd);
134 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
135
136 out_be16(prv->regs + reg, val);
137 }
138
139 /* Set bits in NFC register */
nfc_set(struct mtd_info * mtd,uint reg,u16 bits)140 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
141 {
142 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
143 }
144
145 /* Clear bits in NFC register */
nfc_clear(struct mtd_info * mtd,uint reg,u16 bits)146 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
147 {
148 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
149 }
150
151 /* Invoke address cycle */
mpc5121_nfc_send_addr(struct mtd_info * mtd,u16 addr)152 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
153 {
154 nfc_write(mtd, NFC_FLASH_ADDR, addr);
155 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
156 mpc5121_nfc_done(mtd);
157 }
158
159 /* Invoke command cycle */
mpc5121_nfc_send_cmd(struct mtd_info * mtd,u16 cmd)160 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
161 {
162 nfc_write(mtd, NFC_FLASH_CMD, cmd);
163 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
164 mpc5121_nfc_done(mtd);
165 }
166
167 /* Send data from NFC buffers to NAND flash */
mpc5121_nfc_send_prog_page(struct mtd_info * mtd)168 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
169 {
170 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
171 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
172 mpc5121_nfc_done(mtd);
173 }
174
175 /* Receive data from NAND flash */
mpc5121_nfc_send_read_page(struct mtd_info * mtd)176 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
177 {
178 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
179 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
180 mpc5121_nfc_done(mtd);
181 }
182
183 /* Receive ID from NAND flash */
mpc5121_nfc_send_read_id(struct mtd_info * mtd)184 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
185 {
186 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
187 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
188 mpc5121_nfc_done(mtd);
189 }
190
191 /* Receive status from NAND flash */
mpc5121_nfc_send_read_status(struct mtd_info * mtd)192 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
193 {
194 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
195 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
196 mpc5121_nfc_done(mtd);
197 }
198
199 /* NFC interrupt handler */
mpc5121_nfc_irq(int irq,void * data)200 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
201 {
202 struct mtd_info *mtd = data;
203 struct nand_chip *chip = mtd_to_nand(mtd);
204 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
205
206 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
207 wake_up(&prv->irq_waitq);
208
209 return IRQ_HANDLED;
210 }
211
212 /* Wait for operation complete */
mpc5121_nfc_done(struct mtd_info * mtd)213 static void mpc5121_nfc_done(struct mtd_info *mtd)
214 {
215 struct nand_chip *chip = mtd_to_nand(mtd);
216 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
217 int rv;
218
219 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
220 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
221 rv = wait_event_timeout(prv->irq_waitq,
222 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
223
224 if (!rv)
225 dev_warn(prv->dev,
226 "Timeout while waiting for interrupt.\n");
227 }
228
229 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
230 }
231
232 /* Do address cycle(s) */
mpc5121_nfc_addr_cycle(struct mtd_info * mtd,int column,int page)233 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
234 {
235 struct nand_chip *chip = mtd_to_nand(mtd);
236 u32 pagemask = chip->pagemask;
237
238 if (column != -1) {
239 mpc5121_nfc_send_addr(mtd, column);
240 if (mtd->writesize > 512)
241 mpc5121_nfc_send_addr(mtd, column >> 8);
242 }
243
244 if (page != -1) {
245 do {
246 mpc5121_nfc_send_addr(mtd, page & 0xFF);
247 page >>= 8;
248 pagemask >>= 8;
249 } while (pagemask);
250 }
251 }
252
253 /* Control chip select signals */
mpc5121_nfc_select_chip(struct nand_chip * nand,int chip)254 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip)
255 {
256 struct mtd_info *mtd = nand_to_mtd(nand);
257
258 if (chip < 0) {
259 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
260 return;
261 }
262
263 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
264 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
265 NFC_ACTIVE_CS_MASK);
266 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
267 }
268
269 /* Init external chip select logic on ADS5121 board */
ads5121_chipselect_init(struct mtd_info * mtd)270 static int ads5121_chipselect_init(struct mtd_info *mtd)
271 {
272 struct nand_chip *chip = mtd_to_nand(mtd);
273 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
274 struct device_node *dn;
275
276 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
277 if (dn) {
278 prv->csreg = of_iomap(dn, 0);
279 of_node_put(dn);
280 if (!prv->csreg)
281 return -ENOMEM;
282
283 /* CPLD Register 9 controls NAND /CE Lines */
284 prv->csreg += 9;
285 return 0;
286 }
287
288 return -EINVAL;
289 }
290
291 /* Control chips select signal on ADS5121 board */
ads5121_select_chip(struct nand_chip * nand,int chip)292 static void ads5121_select_chip(struct nand_chip *nand, int chip)
293 {
294 struct mtd_info *mtd = nand_to_mtd(nand);
295 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
296 u8 v;
297
298 v = in_8(prv->csreg);
299 v |= 0x0F;
300
301 if (chip >= 0) {
302 mpc5121_nfc_select_chip(nand, 0);
303 v &= ~(1 << chip);
304 } else
305 mpc5121_nfc_select_chip(nand, -1);
306
307 out_8(prv->csreg, v);
308 }
309
310 /* Read NAND Ready/Busy signal */
mpc5121_nfc_dev_ready(struct nand_chip * nand)311 static int mpc5121_nfc_dev_ready(struct nand_chip *nand)
312 {
313 /*
314 * NFC handles ready/busy signal internally. Therefore, this function
315 * always returns status as ready.
316 */
317 return 1;
318 }
319
320 /* Write command to NAND flash */
mpc5121_nfc_command(struct nand_chip * chip,unsigned command,int column,int page)321 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command,
322 int column, int page)
323 {
324 struct mtd_info *mtd = nand_to_mtd(chip);
325 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
326
327 prv->column = (column >= 0) ? column : 0;
328 prv->spareonly = 0;
329
330 switch (command) {
331 case NAND_CMD_PAGEPROG:
332 mpc5121_nfc_send_prog_page(mtd);
333 break;
334 /*
335 * NFC does not support sub-page reads and writes,
336 * so emulate them using full page transfers.
337 */
338 case NAND_CMD_READ0:
339 column = 0;
340 break;
341
342 case NAND_CMD_READ1:
343 prv->column += 256;
344 command = NAND_CMD_READ0;
345 column = 0;
346 break;
347
348 case NAND_CMD_READOOB:
349 prv->spareonly = 1;
350 command = NAND_CMD_READ0;
351 column = 0;
352 break;
353
354 case NAND_CMD_SEQIN:
355 mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
356 column = 0;
357 break;
358
359 case NAND_CMD_ERASE1:
360 case NAND_CMD_ERASE2:
361 case NAND_CMD_READID:
362 case NAND_CMD_STATUS:
363 break;
364
365 default:
366 return;
367 }
368
369 mpc5121_nfc_send_cmd(mtd, command);
370 mpc5121_nfc_addr_cycle(mtd, column, page);
371
372 switch (command) {
373 case NAND_CMD_READ0:
374 if (mtd->writesize > 512)
375 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
376 mpc5121_nfc_send_read_page(mtd);
377 break;
378
379 case NAND_CMD_READID:
380 mpc5121_nfc_send_read_id(mtd);
381 break;
382
383 case NAND_CMD_STATUS:
384 mpc5121_nfc_send_read_status(mtd);
385 if (chip->options & NAND_BUSWIDTH_16)
386 prv->column = 1;
387 else
388 prv->column = 0;
389 break;
390 }
391 }
392
393 /* Copy data from/to NFC spare buffers. */
mpc5121_nfc_copy_spare(struct mtd_info * mtd,uint offset,u8 * buffer,uint size,int wr)394 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
395 u8 *buffer, uint size, int wr)
396 {
397 struct nand_chip *nand = mtd_to_nand(mtd);
398 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
399 uint o, s, sbsize, blksize;
400
401 /*
402 * NAND spare area is available through NFC spare buffers.
403 * The NFC divides spare area into (page_size / 512) chunks.
404 * Each chunk is placed into separate spare memory area, using
405 * first (spare_size / num_of_chunks) bytes of the buffer.
406 *
407 * For NAND device in which the spare area is not divided fully
408 * by the number of chunks, number of used bytes in each spare
409 * buffer is rounded down to the nearest even number of bytes,
410 * and all remaining bytes are added to the last used spare area.
411 *
412 * For more information read section 26.6.10 of MPC5121e
413 * Microcontroller Reference Manual, Rev. 3.
414 */
415
416 /* Calculate number of valid bytes in each spare buffer */
417 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
418
419 while (size) {
420 /* Calculate spare buffer number */
421 s = offset / sbsize;
422 if (s > NFC_SPARE_BUFFERS - 1)
423 s = NFC_SPARE_BUFFERS - 1;
424
425 /*
426 * Calculate offset to requested data block in selected spare
427 * buffer and its size.
428 */
429 o = offset - (s * sbsize);
430 blksize = min(sbsize - o, size);
431
432 if (wr)
433 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
434 buffer, blksize);
435 else
436 memcpy_fromio(buffer,
437 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
438
439 buffer += blksize;
440 offset += blksize;
441 size -= blksize;
442 }
443 }
444
445 /* Copy data from/to NFC main and spare buffers */
mpc5121_nfc_buf_copy(struct mtd_info * mtd,u_char * buf,int len,int wr)446 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
447 int wr)
448 {
449 struct nand_chip *chip = mtd_to_nand(mtd);
450 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
451 uint c = prv->column;
452 uint l;
453
454 /* Handle spare area access */
455 if (prv->spareonly || c >= mtd->writesize) {
456 /* Calculate offset from beginning of spare area */
457 if (c >= mtd->writesize)
458 c -= mtd->writesize;
459
460 prv->column += len;
461 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
462 return;
463 }
464
465 /*
466 * Handle main area access - limit copy length to prevent
467 * crossing main/spare boundary.
468 */
469 l = min((uint)len, mtd->writesize - c);
470 prv->column += l;
471
472 if (wr)
473 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
474 else
475 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
476
477 /* Handle crossing main/spare boundary */
478 if (l != len) {
479 buf += l;
480 len -= l;
481 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
482 }
483 }
484
485 /* Read data from NFC buffers */
mpc5121_nfc_read_buf(struct nand_chip * chip,u_char * buf,int len)486 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len)
487 {
488 mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0);
489 }
490
491 /* Write data to NFC buffers */
mpc5121_nfc_write_buf(struct nand_chip * chip,const u_char * buf,int len)492 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf,
493 int len)
494 {
495 mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1);
496 }
497
498 /* Read byte from NFC buffers */
mpc5121_nfc_read_byte(struct nand_chip * chip)499 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip)
500 {
501 u8 tmp;
502
503 mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp));
504
505 return tmp;
506 }
507
508 /*
509 * Read NFC configuration from Reset Config Word
510 *
511 * NFC is configured during reset in basis of information stored
512 * in Reset Config Word. There is no other way to set NAND block
513 * size, spare size and bus width.
514 */
mpc5121_nfc_read_hw_config(struct mtd_info * mtd)515 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
516 {
517 struct nand_chip *chip = mtd_to_nand(mtd);
518 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
519 struct mpc512x_reset_module *rm;
520 struct device_node *rmnode;
521 uint rcw_pagesize = 0;
522 uint rcw_sparesize = 0;
523 uint rcw_width;
524 uint rcwh;
525 uint romloc, ps;
526 int ret = 0;
527
528 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
529 if (!rmnode) {
530 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
531 "node in device tree!\n");
532 return -ENODEV;
533 }
534
535 rm = of_iomap(rmnode, 0);
536 if (!rm) {
537 dev_err(prv->dev, "Error mapping reset module node!\n");
538 ret = -EBUSY;
539 goto out;
540 }
541
542 rcwh = in_be32(&rm->rcwhr);
543
544 /* Bit 6: NFC bus width */
545 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
546
547 /* Bit 7: NFC Page/Spare size */
548 ps = (rcwh >> 7) & 0x1;
549
550 /* Bits [22:21]: ROM Location */
551 romloc = (rcwh >> 21) & 0x3;
552
553 /* Decode RCW bits */
554 switch ((ps << 2) | romloc) {
555 case 0x00:
556 case 0x01:
557 rcw_pagesize = 512;
558 rcw_sparesize = 16;
559 break;
560 case 0x02:
561 case 0x03:
562 rcw_pagesize = 4096;
563 rcw_sparesize = 128;
564 break;
565 case 0x04:
566 case 0x05:
567 rcw_pagesize = 2048;
568 rcw_sparesize = 64;
569 break;
570 case 0x06:
571 case 0x07:
572 rcw_pagesize = 4096;
573 rcw_sparesize = 218;
574 break;
575 }
576
577 mtd->writesize = rcw_pagesize;
578 mtd->oobsize = rcw_sparesize;
579 if (rcw_width == 2)
580 chip->options |= NAND_BUSWIDTH_16;
581
582 dev_notice(prv->dev, "Configured for "
583 "%u-bit NAND, page size %u "
584 "with %u spare.\n",
585 rcw_width * 8, rcw_pagesize,
586 rcw_sparesize);
587 iounmap(rm);
588 out:
589 of_node_put(rmnode);
590 return ret;
591 }
592
593 /* Free driver resources */
mpc5121_nfc_free(struct device * dev,struct mtd_info * mtd)594 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
595 {
596 struct nand_chip *chip = mtd_to_nand(mtd);
597 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
598
599 if (prv->clk)
600 clk_disable_unprepare(prv->clk);
601
602 if (prv->csreg)
603 iounmap(prv->csreg);
604 }
605
mpc5121_nfc_attach_chip(struct nand_chip * chip)606 static int mpc5121_nfc_attach_chip(struct nand_chip *chip)
607 {
608 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
609
610 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
611 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
612
613 return 0;
614 }
615
616 static const struct nand_controller_ops mpc5121_nfc_ops = {
617 .attach_chip = mpc5121_nfc_attach_chip,
618 };
619
mpc5121_nfc_probe(struct platform_device * op)620 static int mpc5121_nfc_probe(struct platform_device *op)
621 {
622 struct device_node *dn = op->dev.of_node;
623 struct clk *clk;
624 struct device *dev = &op->dev;
625 struct mpc5121_nfc_prv *prv;
626 struct resource res;
627 struct mtd_info *mtd;
628 struct nand_chip *chip;
629 unsigned long regs_paddr, regs_size;
630 const __be32 *chips_no;
631 int resettime = 0;
632 int retval = 0;
633 int rev, len;
634
635 /*
636 * Check SoC revision. This driver supports only NFC
637 * in MPC5121 revision 2 and MPC5123 revision 3.
638 */
639 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
640 if ((rev != 2) && (rev != 3)) {
641 dev_err(dev, "SoC revision %u is not supported!\n", rev);
642 return -ENXIO;
643 }
644
645 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
646 if (!prv)
647 return -ENOMEM;
648
649 chip = &prv->chip;
650 mtd = nand_to_mtd(chip);
651
652 nand_controller_init(&prv->controller);
653 prv->controller.ops = &mpc5121_nfc_ops;
654 chip->controller = &prv->controller;
655
656 mtd->dev.parent = dev;
657 nand_set_controller_data(chip, prv);
658 nand_set_flash_node(chip, dn);
659 prv->dev = dev;
660
661 /* Read NFC configuration from Reset Config Word */
662 retval = mpc5121_nfc_read_hw_config(mtd);
663 if (retval) {
664 dev_err(dev, "Unable to read NFC config!\n");
665 return retval;
666 }
667
668 prv->irq = irq_of_parse_and_map(dn, 0);
669 if (prv->irq == NO_IRQ) {
670 dev_err(dev, "Error mapping IRQ!\n");
671 return -EINVAL;
672 }
673
674 retval = of_address_to_resource(dn, 0, &res);
675 if (retval) {
676 dev_err(dev, "Error parsing memory region!\n");
677 return retval;
678 }
679
680 chips_no = of_get_property(dn, "chips", &len);
681 if (!chips_no || len != sizeof(*chips_no)) {
682 dev_err(dev, "Invalid/missing 'chips' property!\n");
683 return -EINVAL;
684 }
685
686 regs_paddr = res.start;
687 regs_size = resource_size(&res);
688
689 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
690 dev_err(dev, "Error requesting memory region!\n");
691 return -EBUSY;
692 }
693
694 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
695 if (!prv->regs) {
696 dev_err(dev, "Error mapping memory region!\n");
697 return -ENOMEM;
698 }
699
700 mtd->name = "MPC5121 NAND";
701 chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
702 chip->legacy.cmdfunc = mpc5121_nfc_command;
703 chip->legacy.read_byte = mpc5121_nfc_read_byte;
704 chip->legacy.read_buf = mpc5121_nfc_read_buf;
705 chip->legacy.write_buf = mpc5121_nfc_write_buf;
706 chip->legacy.select_chip = mpc5121_nfc_select_chip;
707 chip->legacy.set_features = nand_get_set_features_notsupp;
708 chip->legacy.get_features = nand_get_set_features_notsupp;
709 chip->bbt_options = NAND_BBT_USE_FLASH;
710
711 /* Support external chip-select logic on ADS5121 board */
712 if (of_machine_is_compatible("fsl,mpc5121ads")) {
713 retval = ads5121_chipselect_init(mtd);
714 if (retval) {
715 dev_err(dev, "Chipselect init error!\n");
716 return retval;
717 }
718
719 chip->legacy.select_chip = ads5121_select_chip;
720 }
721
722 /* Enable NFC clock */
723 clk = devm_clk_get(dev, "ipg");
724 if (IS_ERR(clk)) {
725 dev_err(dev, "Unable to acquire NFC clock!\n");
726 retval = PTR_ERR(clk);
727 goto error;
728 }
729 retval = clk_prepare_enable(clk);
730 if (retval) {
731 dev_err(dev, "Unable to enable NFC clock!\n");
732 goto error;
733 }
734 prv->clk = clk;
735
736 /* Reset NAND Flash controller */
737 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
738 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
739 if (resettime++ >= NFC_RESET_TIMEOUT) {
740 dev_err(dev, "Timeout while resetting NFC!\n");
741 retval = -EINVAL;
742 goto error;
743 }
744
745 udelay(1);
746 }
747
748 /* Enable write to NFC memory */
749 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
750
751 /* Enable write to all NAND pages */
752 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
753 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
754 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
755
756 /*
757 * Setup NFC:
758 * - Big Endian transfers,
759 * - Interrupt after full page read/write.
760 */
761 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
762 NFC_FULL_PAGE_INT);
763
764 /* Set spare area size */
765 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
766
767 init_waitqueue_head(&prv->irq_waitq);
768 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
769 mtd);
770 if (retval) {
771 dev_err(dev, "Error requesting IRQ!\n");
772 goto error;
773 }
774
775 /* Detect NAND chips */
776 retval = nand_scan(chip, be32_to_cpup(chips_no));
777 if (retval) {
778 dev_err(dev, "NAND Flash not found !\n");
779 goto error;
780 }
781
782 /* Set erase block size */
783 switch (mtd->erasesize / mtd->writesize) {
784 case 32:
785 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
786 break;
787
788 case 64:
789 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
790 break;
791
792 case 128:
793 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
794 break;
795
796 case 256:
797 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
798 break;
799
800 default:
801 dev_err(dev, "Unsupported NAND flash!\n");
802 retval = -ENXIO;
803 goto error;
804 }
805
806 dev_set_drvdata(dev, mtd);
807
808 /* Register device in MTD */
809 retval = mtd_device_register(mtd, NULL, 0);
810 if (retval) {
811 dev_err(dev, "Error adding MTD device!\n");
812 goto error;
813 }
814
815 return 0;
816 error:
817 mpc5121_nfc_free(dev, mtd);
818 return retval;
819 }
820
mpc5121_nfc_remove(struct platform_device * op)821 static int mpc5121_nfc_remove(struct platform_device *op)
822 {
823 struct device *dev = &op->dev;
824 struct mtd_info *mtd = dev_get_drvdata(dev);
825 int ret;
826
827 ret = mtd_device_unregister(mtd);
828 WARN_ON(ret);
829 nand_cleanup(mtd_to_nand(mtd));
830 mpc5121_nfc_free(dev, mtd);
831
832 return 0;
833 }
834
835 static const struct of_device_id mpc5121_nfc_match[] = {
836 { .compatible = "fsl,mpc5121-nfc", },
837 {},
838 };
839 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
840
841 static struct platform_driver mpc5121_nfc_driver = {
842 .probe = mpc5121_nfc_probe,
843 .remove = mpc5121_nfc_remove,
844 .driver = {
845 .name = DRV_NAME,
846 .of_match_table = mpc5121_nfc_match,
847 },
848 };
849
850 module_platform_driver(mpc5121_nfc_driver);
851
852 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
853 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
854 MODULE_LICENSE("GPL");
855