1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MPU3050 gyroscope driver
4 *
5 * Copyright (C) 2016 Linaro Ltd.
6 * Author: Linus Walleij <linus.walleij@linaro.org>
7 *
8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
12 *
13 * TODO: add support for setting up the low pass 3dB frequency.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/random.h>
29 #include <linux/slab.h>
30
31 #include "mpu3050.h"
32
33 #define MPU3050_CHIP_ID 0x68
34 #define MPU3050_CHIP_ID_MASK 0x7E
35
36 /*
37 * Register map: anything suffixed *_H is a big-endian high byte and always
38 * followed by the corresponding low byte (*_L) even though these are not
39 * explicitly included in the register definitions.
40 */
41 #define MPU3050_CHIP_ID_REG 0x00
42 #define MPU3050_PRODUCT_ID_REG 0x01
43 #define MPU3050_XG_OFFS_TC 0x05
44 #define MPU3050_YG_OFFS_TC 0x08
45 #define MPU3050_ZG_OFFS_TC 0x0B
46 #define MPU3050_X_OFFS_USR_H 0x0C
47 #define MPU3050_Y_OFFS_USR_H 0x0E
48 #define MPU3050_Z_OFFS_USR_H 0x10
49 #define MPU3050_FIFO_EN 0x12
50 #define MPU3050_AUX_VDDIO 0x13
51 #define MPU3050_SLV_ADDR 0x14
52 #define MPU3050_SMPLRT_DIV 0x15
53 #define MPU3050_DLPF_FS_SYNC 0x16
54 #define MPU3050_INT_CFG 0x17
55 #define MPU3050_AUX_ADDR 0x18
56 #define MPU3050_INT_STATUS 0x1A
57 #define MPU3050_TEMP_H 0x1B
58 #define MPU3050_XOUT_H 0x1D
59 #define MPU3050_YOUT_H 0x1F
60 #define MPU3050_ZOUT_H 0x21
61 #define MPU3050_DMP_CFG1 0x35
62 #define MPU3050_DMP_CFG2 0x36
63 #define MPU3050_BANK_SEL 0x37
64 #define MPU3050_MEM_START_ADDR 0x38
65 #define MPU3050_MEM_R_W 0x39
66 #define MPU3050_FIFO_COUNT_H 0x3A
67 #define MPU3050_FIFO_R 0x3C
68 #define MPU3050_USR_CTRL 0x3D
69 #define MPU3050_PWR_MGM 0x3E
70
71 /* MPU memory bank read options */
72 #define MPU3050_MEM_PRFTCH BIT(5)
73 #define MPU3050_MEM_USER_BANK BIT(4)
74 /* Bits 8-11 select memory bank */
75 #define MPU3050_MEM_RAM_BANK_0 0
76 #define MPU3050_MEM_RAM_BANK_1 1
77 #define MPU3050_MEM_RAM_BANK_2 2
78 #define MPU3050_MEM_RAM_BANK_3 3
79 #define MPU3050_MEM_OTP_BANK_0 4
80
81 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
82
83 /* Register bits */
84
85 /* FIFO Enable */
86 #define MPU3050_FIFO_EN_FOOTER BIT(0)
87 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
88 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
89 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
90 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
91 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
92 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
93 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
94
95 /*
96 * Digital Low Pass filter (DLPF)
97 * Full Scale (FS)
98 * and Synchronization
99 */
100 #define MPU3050_EXT_SYNC_NONE 0x00
101 #define MPU3050_EXT_SYNC_TEMP 0x20
102 #define MPU3050_EXT_SYNC_GYROX 0x40
103 #define MPU3050_EXT_SYNC_GYROY 0x60
104 #define MPU3050_EXT_SYNC_GYROZ 0x80
105 #define MPU3050_EXT_SYNC_ACCELX 0xA0
106 #define MPU3050_EXT_SYNC_ACCELY 0xC0
107 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
108 #define MPU3050_EXT_SYNC_MASK 0xE0
109 #define MPU3050_EXT_SYNC_SHIFT 5
110
111 #define MPU3050_FS_250DPS 0x00
112 #define MPU3050_FS_500DPS 0x08
113 #define MPU3050_FS_1000DPS 0x10
114 #define MPU3050_FS_2000DPS 0x18
115 #define MPU3050_FS_MASK 0x18
116 #define MPU3050_FS_SHIFT 3
117
118 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
119 #define MPU3050_DLPF_CFG_188HZ 0x01
120 #define MPU3050_DLPF_CFG_98HZ 0x02
121 #define MPU3050_DLPF_CFG_42HZ 0x03
122 #define MPU3050_DLPF_CFG_20HZ 0x04
123 #define MPU3050_DLPF_CFG_10HZ 0x05
124 #define MPU3050_DLPF_CFG_5HZ 0x06
125 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
126 #define MPU3050_DLPF_CFG_MASK 0x07
127 #define MPU3050_DLPF_CFG_SHIFT 0
128
129 /* Interrupt config */
130 #define MPU3050_INT_RAW_RDY_EN BIT(0)
131 #define MPU3050_INT_DMP_DONE_EN BIT(1)
132 #define MPU3050_INT_MPU_RDY_EN BIT(2)
133 #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
134 #define MPU3050_INT_LATCH_EN BIT(5)
135 #define MPU3050_INT_OPEN BIT(6)
136 #define MPU3050_INT_ACTL BIT(7)
137 /* Interrupt status */
138 #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
139 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
140 #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
141 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
142 /* USR_CTRL */
143 #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
144 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
145 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
146 #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
147 #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
148 /* PWR_MGM */
149 #define MPU3050_PWR_MGM_PLL_X 0x01
150 #define MPU3050_PWR_MGM_PLL_Y 0x02
151 #define MPU3050_PWR_MGM_PLL_Z 0x03
152 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
153 #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
154 #define MPU3050_PWR_MGM_STBY_YG BIT(4)
155 #define MPU3050_PWR_MGM_STBY_XG BIT(5)
156 #define MPU3050_PWR_MGM_SLEEP BIT(6)
157 #define MPU3050_PWR_MGM_RESET BIT(7)
158 #define MPU3050_PWR_MGM_MASK 0xff
159
160 /*
161 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
162 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
163 * in two's complement.
164 */
165 static unsigned int mpu3050_fs_precision[] = {
166 IIO_DEGREE_TO_RAD(250),
167 IIO_DEGREE_TO_RAD(500),
168 IIO_DEGREE_TO_RAD(1000),
169 IIO_DEGREE_TO_RAD(2000)
170 };
171
172 /*
173 * Regulator names
174 */
175 static const char mpu3050_reg_vdd[] = "vdd";
176 static const char mpu3050_reg_vlogic[] = "vlogic";
177
mpu3050_get_freq(struct mpu3050 * mpu3050)178 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
179 {
180 unsigned int freq;
181
182 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
183 freq = 8000;
184 else
185 freq = 1000;
186 freq /= (mpu3050->divisor + 1);
187
188 return freq;
189 }
190
mpu3050_start_sampling(struct mpu3050 * mpu3050)191 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
192 {
193 __be16 raw_val[3];
194 int ret;
195 int i;
196
197 /* Reset */
198 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
199 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
200 if (ret)
201 return ret;
202
203 /* Turn on the Z-axis PLL */
204 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
205 MPU3050_PWR_MGM_CLKSEL_MASK,
206 MPU3050_PWR_MGM_PLL_Z);
207 if (ret)
208 return ret;
209
210 /* Write calibration offset registers */
211 for (i = 0; i < 3; i++)
212 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
213
214 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
215 sizeof(raw_val));
216 if (ret)
217 return ret;
218
219 /* Set low pass filter (sample rate), sync and full scale */
220 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
221 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
222 mpu3050->fullscale << MPU3050_FS_SHIFT |
223 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
224 if (ret)
225 return ret;
226
227 /* Set up sampling frequency */
228 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
229 if (ret)
230 return ret;
231
232 /*
233 * Max 50 ms start-up time after setting DLPF_FS_SYNC
234 * according to the data sheet, then wait for the next sample
235 * at this frequency T = 1000/f ms.
236 */
237 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
238
239 return 0;
240 }
241
mpu3050_set_8khz_samplerate(struct mpu3050 * mpu3050)242 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
243 {
244 int ret;
245 u8 divisor;
246 enum mpu3050_lpf lpf;
247
248 lpf = mpu3050->lpf;
249 divisor = mpu3050->divisor;
250
251 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
252 mpu3050->divisor = 0; /* Divide by 1 */
253 ret = mpu3050_start_sampling(mpu3050);
254
255 mpu3050->lpf = lpf;
256 mpu3050->divisor = divisor;
257
258 return ret;
259 }
260
mpu3050_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)261 static int mpu3050_read_raw(struct iio_dev *indio_dev,
262 struct iio_chan_spec const *chan,
263 int *val, int *val2,
264 long mask)
265 {
266 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
267 int ret;
268 __be16 raw_val;
269
270 switch (mask) {
271 case IIO_CHAN_INFO_OFFSET:
272 switch (chan->type) {
273 case IIO_TEMP:
274 /* The temperature scaling is (x+23000)/280 Celsius */
275 *val = 23000;
276 return IIO_VAL_INT;
277 default:
278 return -EINVAL;
279 }
280 case IIO_CHAN_INFO_CALIBBIAS:
281 switch (chan->type) {
282 case IIO_ANGL_VEL:
283 *val = mpu3050->calibration[chan->scan_index-1];
284 return IIO_VAL_INT;
285 default:
286 return -EINVAL;
287 }
288 case IIO_CHAN_INFO_SAMP_FREQ:
289 *val = mpu3050_get_freq(mpu3050);
290 return IIO_VAL_INT;
291 case IIO_CHAN_INFO_SCALE:
292 switch (chan->type) {
293 case IIO_TEMP:
294 /* Millidegrees, see about temperature scaling above */
295 *val = 1000;
296 *val2 = 280;
297 return IIO_VAL_FRACTIONAL;
298 case IIO_ANGL_VEL:
299 /*
300 * Convert to the corresponding full scale in
301 * radians. All 16 bits are used with sign to
302 * span the available scale: to account for the one
303 * missing value if we multiply by 1/S16_MAX, instead
304 * multiply with 2/U16_MAX.
305 */
306 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
307 *val2 = U16_MAX;
308 return IIO_VAL_FRACTIONAL;
309 default:
310 return -EINVAL;
311 }
312 case IIO_CHAN_INFO_RAW:
313 /* Resume device */
314 pm_runtime_get_sync(mpu3050->dev);
315 mutex_lock(&mpu3050->lock);
316
317 ret = mpu3050_set_8khz_samplerate(mpu3050);
318 if (ret)
319 goto out_read_raw_unlock;
320
321 switch (chan->type) {
322 case IIO_TEMP:
323 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
324 &raw_val, sizeof(raw_val));
325 if (ret) {
326 dev_err(mpu3050->dev,
327 "error reading temperature\n");
328 goto out_read_raw_unlock;
329 }
330
331 *val = be16_to_cpu(raw_val);
332 ret = IIO_VAL_INT;
333
334 goto out_read_raw_unlock;
335 case IIO_ANGL_VEL:
336 ret = regmap_bulk_read(mpu3050->map,
337 MPU3050_AXIS_REGS(chan->scan_index-1),
338 &raw_val,
339 sizeof(raw_val));
340 if (ret) {
341 dev_err(mpu3050->dev,
342 "error reading axis data\n");
343 goto out_read_raw_unlock;
344 }
345
346 *val = be16_to_cpu(raw_val);
347 ret = IIO_VAL_INT;
348
349 goto out_read_raw_unlock;
350 default:
351 ret = -EINVAL;
352 goto out_read_raw_unlock;
353 }
354 default:
355 break;
356 }
357
358 return -EINVAL;
359
360 out_read_raw_unlock:
361 mutex_unlock(&mpu3050->lock);
362 pm_runtime_mark_last_busy(mpu3050->dev);
363 pm_runtime_put_autosuspend(mpu3050->dev);
364
365 return ret;
366 }
367
mpu3050_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)368 static int mpu3050_write_raw(struct iio_dev *indio_dev,
369 const struct iio_chan_spec *chan,
370 int val, int val2, long mask)
371 {
372 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
373 /*
374 * Couldn't figure out a way to precalculate these at compile time.
375 */
376 unsigned int fs250 =
377 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
378 U16_MAX);
379 unsigned int fs500 =
380 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
381 U16_MAX);
382 unsigned int fs1000 =
383 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
384 U16_MAX);
385 unsigned int fs2000 =
386 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
387 U16_MAX);
388
389 switch (mask) {
390 case IIO_CHAN_INFO_CALIBBIAS:
391 if (chan->type != IIO_ANGL_VEL)
392 return -EINVAL;
393 mpu3050->calibration[chan->scan_index-1] = val;
394 return 0;
395 case IIO_CHAN_INFO_SAMP_FREQ:
396 /*
397 * The max samplerate is 8000 Hz, the minimum
398 * 1000 / 256 ~= 4 Hz
399 */
400 if (val < 4 || val > 8000)
401 return -EINVAL;
402
403 /*
404 * Above 1000 Hz we must turn off the digital low pass filter
405 * so we get a base frequency of 8kHz to the divider
406 */
407 if (val > 1000) {
408 mpu3050->lpf = LPF_256_HZ_NOLPF;
409 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
410 return 0;
411 }
412
413 mpu3050->lpf = LPF_188_HZ;
414 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
415 return 0;
416 case IIO_CHAN_INFO_SCALE:
417 if (chan->type != IIO_ANGL_VEL)
418 return -EINVAL;
419 /*
420 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
421 * which means we need to round to the closest radians
422 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
423 * rad/s. The scale is then for the 16 bits used to cover
424 * it 2/(2^16) of that.
425 */
426
427 /* Just too large, set the max range */
428 if (val != 0) {
429 mpu3050->fullscale = FS_2000_DPS;
430 return 0;
431 }
432
433 /*
434 * Now we're dealing with fractions below zero in millirad/s
435 * do some integer interpolation and match with the closest
436 * fullscale in the table.
437 */
438 if (val2 <= fs250 ||
439 val2 < ((fs500 + fs250) / 2))
440 mpu3050->fullscale = FS_250_DPS;
441 else if (val2 <= fs500 ||
442 val2 < ((fs1000 + fs500) / 2))
443 mpu3050->fullscale = FS_500_DPS;
444 else if (val2 <= fs1000 ||
445 val2 < ((fs2000 + fs1000) / 2))
446 mpu3050->fullscale = FS_1000_DPS;
447 else
448 /* Catch-all */
449 mpu3050->fullscale = FS_2000_DPS;
450 return 0;
451 default:
452 break;
453 }
454
455 return -EINVAL;
456 }
457
mpu3050_trigger_handler(int irq,void * p)458 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
459 {
460 const struct iio_poll_func *pf = p;
461 struct iio_dev *indio_dev = pf->indio_dev;
462 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
463 int ret;
464 /*
465 * Temperature 1*16 bits
466 * Three axes 3*16 bits
467 * Timestamp 64 bits (4*16 bits)
468 * Sum total 8*16 bits
469 */
470 __be16 hw_values[8];
471 s64 timestamp;
472 unsigned int datums_from_fifo = 0;
473
474 /*
475 * If we're using the hardware trigger, get the precise timestamp from
476 * the top half of the threaded IRQ handler. Otherwise get the
477 * timestamp here so it will be close in time to the actual values
478 * read from the registers.
479 */
480 if (iio_trigger_using_own(indio_dev))
481 timestamp = mpu3050->hw_timestamp;
482 else
483 timestamp = iio_get_time_ns(indio_dev);
484
485 mutex_lock(&mpu3050->lock);
486
487 /* Using the hardware IRQ trigger? Check the buffer then. */
488 if (mpu3050->hw_irq_trigger) {
489 __be16 raw_fifocnt;
490 u16 fifocnt;
491 /* X, Y, Z + temperature */
492 unsigned int bytes_per_datum = 8;
493 bool fifo_overflow = false;
494
495 ret = regmap_bulk_read(mpu3050->map,
496 MPU3050_FIFO_COUNT_H,
497 &raw_fifocnt,
498 sizeof(raw_fifocnt));
499 if (ret)
500 goto out_trigger_unlock;
501 fifocnt = be16_to_cpu(raw_fifocnt);
502
503 if (fifocnt == 512) {
504 dev_info(mpu3050->dev,
505 "FIFO overflow! Emptying and resetting FIFO\n");
506 fifo_overflow = true;
507 /* Reset and enable the FIFO */
508 ret = regmap_update_bits(mpu3050->map,
509 MPU3050_USR_CTRL,
510 MPU3050_USR_CTRL_FIFO_EN |
511 MPU3050_USR_CTRL_FIFO_RST,
512 MPU3050_USR_CTRL_FIFO_EN |
513 MPU3050_USR_CTRL_FIFO_RST);
514 if (ret) {
515 dev_info(mpu3050->dev, "error resetting FIFO\n");
516 goto out_trigger_unlock;
517 }
518 mpu3050->pending_fifo_footer = false;
519 }
520
521 if (fifocnt)
522 dev_dbg(mpu3050->dev,
523 "%d bytes in the FIFO\n",
524 fifocnt);
525
526 while (!fifo_overflow && fifocnt > bytes_per_datum) {
527 unsigned int toread;
528 unsigned int offset;
529 __be16 fifo_values[5];
530
531 /*
532 * If there is a FIFO footer in the pipe, first clear
533 * that out. This follows the complex algorithm in the
534 * datasheet that states that you may never leave the
535 * FIFO empty after the first reading: you have to
536 * always leave two footer bytes in it. The footer is
537 * in practice just two zero bytes.
538 */
539 if (mpu3050->pending_fifo_footer) {
540 toread = bytes_per_datum + 2;
541 offset = 0;
542 } else {
543 toread = bytes_per_datum;
544 offset = 1;
545 /* Put in some dummy value */
546 fifo_values[0] = cpu_to_be16(0xAAAA);
547 }
548
549 ret = regmap_bulk_read(mpu3050->map,
550 MPU3050_FIFO_R,
551 &fifo_values[offset],
552 toread);
553
554 dev_dbg(mpu3050->dev,
555 "%04x %04x %04x %04x %04x\n",
556 fifo_values[0],
557 fifo_values[1],
558 fifo_values[2],
559 fifo_values[3],
560 fifo_values[4]);
561
562 /* Index past the footer (fifo_values[0]) and push */
563 iio_push_to_buffers_with_timestamp(indio_dev,
564 &fifo_values[1],
565 timestamp);
566
567 fifocnt -= toread;
568 datums_from_fifo++;
569 mpu3050->pending_fifo_footer = true;
570
571 /*
572 * If we're emptying the FIFO, just make sure to
573 * check if something new appeared.
574 */
575 if (fifocnt < bytes_per_datum) {
576 ret = regmap_bulk_read(mpu3050->map,
577 MPU3050_FIFO_COUNT_H,
578 &raw_fifocnt,
579 sizeof(raw_fifocnt));
580 if (ret)
581 goto out_trigger_unlock;
582 fifocnt = be16_to_cpu(raw_fifocnt);
583 }
584
585 if (fifocnt < bytes_per_datum)
586 dev_dbg(mpu3050->dev,
587 "%d bytes left in the FIFO\n",
588 fifocnt);
589
590 /*
591 * At this point, the timestamp that triggered the
592 * hardware interrupt is no longer valid for what
593 * we are reading (the interrupt likely fired for
594 * the value on the top of the FIFO), so set the
595 * timestamp to zero and let userspace deal with it.
596 */
597 timestamp = 0;
598 }
599 }
600
601 /*
602 * If we picked some datums from the FIFO that's enough, else
603 * fall through and just read from the current value registers.
604 * This happens in two cases:
605 *
606 * - We are using some other trigger (external, like an HRTimer)
607 * than the sensor's own sample generator. In this case the
608 * sensor is just set to the max sampling frequency and we give
609 * the trigger a copy of the latest value every time we get here.
610 *
611 * - The hardware trigger is active but unused and we actually use
612 * another trigger which calls here with a frequency higher
613 * than what the device provides data. We will then just read
614 * duplicate values directly from the hardware registers.
615 */
616 if (datums_from_fifo) {
617 dev_dbg(mpu3050->dev,
618 "read %d datums from the FIFO\n",
619 datums_from_fifo);
620 goto out_trigger_unlock;
621 }
622
623 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
624 sizeof(hw_values));
625 if (ret) {
626 dev_err(mpu3050->dev,
627 "error reading axis data\n");
628 goto out_trigger_unlock;
629 }
630
631 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
632
633 out_trigger_unlock:
634 mutex_unlock(&mpu3050->lock);
635 iio_trigger_notify_done(indio_dev->trig);
636
637 return IRQ_HANDLED;
638 }
639
mpu3050_buffer_preenable(struct iio_dev * indio_dev)640 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
641 {
642 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
643
644 pm_runtime_get_sync(mpu3050->dev);
645
646 /* Unless we have OUR trigger active, run at full speed */
647 if (!mpu3050->hw_irq_trigger)
648 return mpu3050_set_8khz_samplerate(mpu3050);
649
650 return 0;
651 }
652
mpu3050_buffer_postdisable(struct iio_dev * indio_dev)653 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
654 {
655 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
656
657 pm_runtime_mark_last_busy(mpu3050->dev);
658 pm_runtime_put_autosuspend(mpu3050->dev);
659
660 return 0;
661 }
662
663 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
664 .preenable = mpu3050_buffer_preenable,
665 .postdisable = mpu3050_buffer_postdisable,
666 };
667
668 static const struct iio_mount_matrix *
mpu3050_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)669 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
670 const struct iio_chan_spec *chan)
671 {
672 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
673
674 return &mpu3050->orientation;
675 }
676
677 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
678 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
679 { },
680 };
681
682 #define MPU3050_AXIS_CHANNEL(axis, index) \
683 { \
684 .type = IIO_ANGL_VEL, \
685 .modified = 1, \
686 .channel2 = IIO_MOD_##axis, \
687 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
688 BIT(IIO_CHAN_INFO_CALIBBIAS), \
689 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
690 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
691 .ext_info = mpu3050_ext_info, \
692 .scan_index = index, \
693 .scan_type = { \
694 .sign = 's', \
695 .realbits = 16, \
696 .storagebits = 16, \
697 .endianness = IIO_BE, \
698 }, \
699 }
700
701 static const struct iio_chan_spec mpu3050_channels[] = {
702 {
703 .type = IIO_TEMP,
704 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
705 BIT(IIO_CHAN_INFO_SCALE) |
706 BIT(IIO_CHAN_INFO_OFFSET),
707 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
708 .scan_index = 0,
709 .scan_type = {
710 .sign = 's',
711 .realbits = 16,
712 .storagebits = 16,
713 .endianness = IIO_BE,
714 },
715 },
716 MPU3050_AXIS_CHANNEL(X, 1),
717 MPU3050_AXIS_CHANNEL(Y, 2),
718 MPU3050_AXIS_CHANNEL(Z, 3),
719 IIO_CHAN_SOFT_TIMESTAMP(4),
720 };
721
722 /* Four channels apart from timestamp, scan mask = 0x0f */
723 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
724
725 /*
726 * These are just the hardcoded factors resulting from the more elaborate
727 * calculations done with fractions in the scale raw get/set functions.
728 */
729 static IIO_CONST_ATTR(anglevel_scale_available,
730 "0.000122070 "
731 "0.000274658 "
732 "0.000518798 "
733 "0.001068115");
734
735 static struct attribute *mpu3050_attributes[] = {
736 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
737 NULL,
738 };
739
740 static const struct attribute_group mpu3050_attribute_group = {
741 .attrs = mpu3050_attributes,
742 };
743
744 static const struct iio_info mpu3050_info = {
745 .read_raw = mpu3050_read_raw,
746 .write_raw = mpu3050_write_raw,
747 .attrs = &mpu3050_attribute_group,
748 };
749
750 /**
751 * mpu3050_read_mem() - read MPU-3050 internal memory
752 * @mpu3050: device to read from
753 * @bank: target bank
754 * @addr: target address
755 * @len: number of bytes
756 * @buf: the buffer to store the read bytes in
757 */
mpu3050_read_mem(struct mpu3050 * mpu3050,u8 bank,u8 addr,u8 len,u8 * buf)758 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
759 u8 bank,
760 u8 addr,
761 u8 len,
762 u8 *buf)
763 {
764 int ret;
765
766 ret = regmap_write(mpu3050->map,
767 MPU3050_BANK_SEL,
768 bank);
769 if (ret)
770 return ret;
771
772 ret = regmap_write(mpu3050->map,
773 MPU3050_MEM_START_ADDR,
774 addr);
775 if (ret)
776 return ret;
777
778 return regmap_bulk_read(mpu3050->map,
779 MPU3050_MEM_R_W,
780 buf,
781 len);
782 }
783
mpu3050_hw_init(struct mpu3050 * mpu3050)784 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
785 {
786 int ret;
787 u8 otp[8];
788
789 /* Reset */
790 ret = regmap_update_bits(mpu3050->map,
791 MPU3050_PWR_MGM,
792 MPU3050_PWR_MGM_RESET,
793 MPU3050_PWR_MGM_RESET);
794 if (ret)
795 return ret;
796
797 /* Turn on the PLL */
798 ret = regmap_update_bits(mpu3050->map,
799 MPU3050_PWR_MGM,
800 MPU3050_PWR_MGM_CLKSEL_MASK,
801 MPU3050_PWR_MGM_PLL_Z);
802 if (ret)
803 return ret;
804
805 /* Disable IRQs */
806 ret = regmap_write(mpu3050->map,
807 MPU3050_INT_CFG,
808 0);
809 if (ret)
810 return ret;
811
812 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
813 ret = mpu3050_read_mem(mpu3050,
814 (MPU3050_MEM_PRFTCH |
815 MPU3050_MEM_USER_BANK |
816 MPU3050_MEM_OTP_BANK_0),
817 0,
818 sizeof(otp),
819 otp);
820 if (ret)
821 return ret;
822
823 /* This is device-unique data so it goes into the entropy pool */
824 add_device_randomness(otp, sizeof(otp));
825
826 dev_info(mpu3050->dev,
827 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
828 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
829 /* Die ID, bits 0-12 */
830 (otp[1] << 8 | otp[0]) & 0x1fff,
831 /* Wafer ID, bits 13-17 */
832 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
833 /* A lot ID, bits 18-33 */
834 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
835 /* W lot ID, bits 34-45 */
836 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
837 /* WP ID, bits 47-49 */
838 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
839 /* rev ID, bits 50-55 */
840 otp[6] >> 2);
841
842 return 0;
843 }
844
mpu3050_power_up(struct mpu3050 * mpu3050)845 static int mpu3050_power_up(struct mpu3050 *mpu3050)
846 {
847 int ret;
848
849 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
850 if (ret) {
851 dev_err(mpu3050->dev, "cannot enable regulators\n");
852 return ret;
853 }
854 /*
855 * 20-100 ms start-up time for register read/write according to
856 * the datasheet, be on the safe side and wait 200 ms.
857 */
858 msleep(200);
859
860 /* Take device out of sleep mode */
861 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
862 MPU3050_PWR_MGM_SLEEP, 0);
863 if (ret) {
864 dev_err(mpu3050->dev, "error setting power mode\n");
865 return ret;
866 }
867 usleep_range(10000, 20000);
868
869 return 0;
870 }
871
mpu3050_power_down(struct mpu3050 * mpu3050)872 static int mpu3050_power_down(struct mpu3050 *mpu3050)
873 {
874 int ret;
875
876 /*
877 * Put MPU-3050 into sleep mode before cutting regulators.
878 * This is important, because we may not be the sole user
879 * of the regulator so the power may stay on after this, and
880 * then we would be wasting power unless we go to sleep mode
881 * first.
882 */
883 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
884 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
885 if (ret)
886 dev_err(mpu3050->dev, "error putting to sleep\n");
887
888 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
889 if (ret)
890 dev_err(mpu3050->dev, "error disabling regulators\n");
891
892 return 0;
893 }
894
mpu3050_irq_handler(int irq,void * p)895 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
896 {
897 struct iio_trigger *trig = p;
898 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
899 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
900
901 if (!mpu3050->hw_irq_trigger)
902 return IRQ_NONE;
903
904 /* Get the time stamp as close in time as possible */
905 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
906
907 return IRQ_WAKE_THREAD;
908 }
909
mpu3050_irq_thread(int irq,void * p)910 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
911 {
912 struct iio_trigger *trig = p;
913 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
914 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
915 unsigned int val;
916 int ret;
917
918 /* ACK IRQ and check if it was from us */
919 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
920 if (ret) {
921 dev_err(mpu3050->dev, "error reading IRQ status\n");
922 return IRQ_HANDLED;
923 }
924 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
925 return IRQ_NONE;
926
927 iio_trigger_poll_chained(p);
928
929 return IRQ_HANDLED;
930 }
931
932 /**
933 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
934 * @trig: trigger instance
935 * @enable: true if trigger should be enabled, false to disable
936 */
mpu3050_drdy_trigger_set_state(struct iio_trigger * trig,bool enable)937 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
938 bool enable)
939 {
940 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
941 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
942 unsigned int val;
943 int ret;
944
945 /* Disabling trigger: disable interrupt and return */
946 if (!enable) {
947 /* Disable all interrupts */
948 ret = regmap_write(mpu3050->map,
949 MPU3050_INT_CFG,
950 0);
951 if (ret)
952 dev_err(mpu3050->dev, "error disabling IRQ\n");
953
954 /* Clear IRQ flag */
955 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
956 if (ret)
957 dev_err(mpu3050->dev, "error clearing IRQ status\n");
958
959 /* Disable all things in the FIFO and reset it */
960 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
961 if (ret)
962 dev_err(mpu3050->dev, "error disabling FIFO\n");
963
964 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
965 MPU3050_USR_CTRL_FIFO_RST);
966 if (ret)
967 dev_err(mpu3050->dev, "error resetting FIFO\n");
968
969 pm_runtime_mark_last_busy(mpu3050->dev);
970 pm_runtime_put_autosuspend(mpu3050->dev);
971 mpu3050->hw_irq_trigger = false;
972
973 return 0;
974 } else {
975 /* Else we're enabling the trigger from this point */
976 pm_runtime_get_sync(mpu3050->dev);
977 mpu3050->hw_irq_trigger = true;
978
979 /* Disable all things in the FIFO */
980 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
981 if (ret)
982 return ret;
983
984 /* Reset and enable the FIFO */
985 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
986 MPU3050_USR_CTRL_FIFO_EN |
987 MPU3050_USR_CTRL_FIFO_RST,
988 MPU3050_USR_CTRL_FIFO_EN |
989 MPU3050_USR_CTRL_FIFO_RST);
990 if (ret)
991 return ret;
992
993 mpu3050->pending_fifo_footer = false;
994
995 /* Turn on the FIFO for temp+X+Y+Z */
996 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
997 MPU3050_FIFO_EN_TEMP_OUT |
998 MPU3050_FIFO_EN_GYRO_XOUT |
999 MPU3050_FIFO_EN_GYRO_YOUT |
1000 MPU3050_FIFO_EN_GYRO_ZOUT |
1001 MPU3050_FIFO_EN_FOOTER);
1002 if (ret)
1003 return ret;
1004
1005 /* Configure the sample engine */
1006 ret = mpu3050_start_sampling(mpu3050);
1007 if (ret)
1008 return ret;
1009
1010 /* Clear IRQ flag */
1011 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1012 if (ret)
1013 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1014
1015 /* Give us interrupts whenever there is new data ready */
1016 val = MPU3050_INT_RAW_RDY_EN;
1017
1018 if (mpu3050->irq_actl)
1019 val |= MPU3050_INT_ACTL;
1020 if (mpu3050->irq_latch)
1021 val |= MPU3050_INT_LATCH_EN;
1022 if (mpu3050->irq_opendrain)
1023 val |= MPU3050_INT_OPEN;
1024
1025 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1026 if (ret)
1027 return ret;
1028 }
1029
1030 return 0;
1031 }
1032
1033 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1034 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1035 };
1036
mpu3050_trigger_probe(struct iio_dev * indio_dev,int irq)1037 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1038 {
1039 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1040 unsigned long irq_trig;
1041 int ret;
1042
1043 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1044 "%s-dev%d",
1045 indio_dev->name,
1046 indio_dev->id);
1047 if (!mpu3050->trig)
1048 return -ENOMEM;
1049
1050 /* Check if IRQ is open drain */
1051 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
1052 mpu3050->irq_opendrain = true;
1053
1054 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1055 /*
1056 * Configure the interrupt generator hardware to supply whatever
1057 * the interrupt is configured for, edges low/high level low/high,
1058 * we can provide it all.
1059 */
1060 switch (irq_trig) {
1061 case IRQF_TRIGGER_RISING:
1062 dev_info(&indio_dev->dev,
1063 "pulse interrupts on the rising edge\n");
1064 break;
1065 case IRQF_TRIGGER_FALLING:
1066 mpu3050->irq_actl = true;
1067 dev_info(&indio_dev->dev,
1068 "pulse interrupts on the falling edge\n");
1069 break;
1070 case IRQF_TRIGGER_HIGH:
1071 mpu3050->irq_latch = true;
1072 dev_info(&indio_dev->dev,
1073 "interrupts active high level\n");
1074 /*
1075 * With level IRQs, we mask the IRQ until it is processed,
1076 * but with edge IRQs (pulses) we can queue several interrupts
1077 * in the top half.
1078 */
1079 irq_trig |= IRQF_ONESHOT;
1080 break;
1081 case IRQF_TRIGGER_LOW:
1082 mpu3050->irq_latch = true;
1083 mpu3050->irq_actl = true;
1084 irq_trig |= IRQF_ONESHOT;
1085 dev_info(&indio_dev->dev,
1086 "interrupts active low level\n");
1087 break;
1088 default:
1089 /* This is the most preferred mode, if possible */
1090 dev_err(&indio_dev->dev,
1091 "unsupported IRQ trigger specified (%lx), enforce "
1092 "rising edge\n", irq_trig);
1093 irq_trig = IRQF_TRIGGER_RISING;
1094 break;
1095 }
1096
1097 /* An open drain line can be shared with several devices */
1098 if (mpu3050->irq_opendrain)
1099 irq_trig |= IRQF_SHARED;
1100
1101 ret = request_threaded_irq(irq,
1102 mpu3050_irq_handler,
1103 mpu3050_irq_thread,
1104 irq_trig,
1105 mpu3050->trig->name,
1106 mpu3050->trig);
1107 if (ret) {
1108 dev_err(mpu3050->dev,
1109 "can't get IRQ %d, error %d\n", irq, ret);
1110 return ret;
1111 }
1112
1113 mpu3050->irq = irq;
1114 mpu3050->trig->dev.parent = mpu3050->dev;
1115 mpu3050->trig->ops = &mpu3050_trigger_ops;
1116 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1117
1118 ret = iio_trigger_register(mpu3050->trig);
1119 if (ret)
1120 return ret;
1121
1122 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1123
1124 return 0;
1125 }
1126
mpu3050_common_probe(struct device * dev,struct regmap * map,int irq,const char * name)1127 int mpu3050_common_probe(struct device *dev,
1128 struct regmap *map,
1129 int irq,
1130 const char *name)
1131 {
1132 struct iio_dev *indio_dev;
1133 struct mpu3050 *mpu3050;
1134 unsigned int val;
1135 int ret;
1136
1137 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1138 if (!indio_dev)
1139 return -ENOMEM;
1140 mpu3050 = iio_priv(indio_dev);
1141
1142 mpu3050->dev = dev;
1143 mpu3050->map = map;
1144 mutex_init(&mpu3050->lock);
1145 /* Default fullscale: 2000 degrees per second */
1146 mpu3050->fullscale = FS_2000_DPS;
1147 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1148 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1149 mpu3050->divisor = 99;
1150
1151 /* Read the mounting matrix, if present */
1152 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation);
1153 if (ret)
1154 return ret;
1155
1156 /* Fetch and turn on regulators */
1157 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1158 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1159 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1160 mpu3050->regs);
1161 if (ret) {
1162 dev_err(dev, "Cannot get regulators\n");
1163 return ret;
1164 }
1165
1166 ret = mpu3050_power_up(mpu3050);
1167 if (ret)
1168 return ret;
1169
1170 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1171 if (ret) {
1172 dev_err(dev, "could not read device ID\n");
1173 ret = -ENODEV;
1174
1175 goto err_power_down;
1176 }
1177
1178 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1179 dev_err(dev, "unsupported chip id %02x\n",
1180 (u8)(val & MPU3050_CHIP_ID_MASK));
1181 ret = -ENODEV;
1182 goto err_power_down;
1183 }
1184
1185 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1186 if (ret) {
1187 dev_err(dev, "could not read device ID\n");
1188 ret = -ENODEV;
1189
1190 goto err_power_down;
1191 }
1192 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1193 ((val >> 4) & 0xf), (val & 0xf));
1194
1195 ret = mpu3050_hw_init(mpu3050);
1196 if (ret)
1197 goto err_power_down;
1198
1199 indio_dev->channels = mpu3050_channels;
1200 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1201 indio_dev->info = &mpu3050_info;
1202 indio_dev->available_scan_masks = mpu3050_scan_masks;
1203 indio_dev->modes = INDIO_DIRECT_MODE;
1204 indio_dev->name = name;
1205
1206 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1207 mpu3050_trigger_handler,
1208 &mpu3050_buffer_setup_ops);
1209 if (ret) {
1210 dev_err(dev, "triggered buffer setup failed\n");
1211 goto err_power_down;
1212 }
1213
1214 ret = iio_device_register(indio_dev);
1215 if (ret) {
1216 dev_err(dev, "device register failed\n");
1217 goto err_cleanup_buffer;
1218 }
1219
1220 dev_set_drvdata(dev, indio_dev);
1221
1222 /* Check if we have an assigned IRQ to use as trigger */
1223 if (irq) {
1224 ret = mpu3050_trigger_probe(indio_dev, irq);
1225 if (ret)
1226 dev_err(dev, "failed to register trigger\n");
1227 }
1228
1229 /* Enable runtime PM */
1230 pm_runtime_get_noresume(dev);
1231 pm_runtime_set_active(dev);
1232 pm_runtime_enable(dev);
1233 /*
1234 * Set autosuspend to two orders of magnitude larger than the
1235 * start-up time. 100ms start-up time means 10000ms autosuspend,
1236 * i.e. 10 seconds.
1237 */
1238 pm_runtime_set_autosuspend_delay(dev, 10000);
1239 pm_runtime_use_autosuspend(dev);
1240 pm_runtime_put(dev);
1241
1242 return 0;
1243
1244 err_cleanup_buffer:
1245 iio_triggered_buffer_cleanup(indio_dev);
1246 err_power_down:
1247 mpu3050_power_down(mpu3050);
1248
1249 return ret;
1250 }
1251 EXPORT_SYMBOL(mpu3050_common_probe);
1252
mpu3050_common_remove(struct device * dev)1253 int mpu3050_common_remove(struct device *dev)
1254 {
1255 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1256 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1257
1258 pm_runtime_get_sync(dev);
1259 pm_runtime_put_noidle(dev);
1260 pm_runtime_disable(dev);
1261 iio_triggered_buffer_cleanup(indio_dev);
1262 if (mpu3050->irq)
1263 free_irq(mpu3050->irq, mpu3050);
1264 iio_device_unregister(indio_dev);
1265 mpu3050_power_down(mpu3050);
1266
1267 return 0;
1268 }
1269 EXPORT_SYMBOL(mpu3050_common_remove);
1270
1271 #ifdef CONFIG_PM
mpu3050_runtime_suspend(struct device * dev)1272 static int mpu3050_runtime_suspend(struct device *dev)
1273 {
1274 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1275 }
1276
mpu3050_runtime_resume(struct device * dev)1277 static int mpu3050_runtime_resume(struct device *dev)
1278 {
1279 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1280 }
1281 #endif /* CONFIG_PM */
1282
1283 const struct dev_pm_ops mpu3050_dev_pm_ops = {
1284 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1285 pm_runtime_force_resume)
1286 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
1287 mpu3050_runtime_resume, NULL)
1288 };
1289 EXPORT_SYMBOL(mpu3050_dev_pm_ops);
1290
1291 MODULE_AUTHOR("Linus Walleij");
1292 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1293 MODULE_LICENSE("GPL");
1294