1 // SPDX-License-Identifier: GPL-2.0-only
2
3 /*
4 * Copyright (C) 2020 Advanced Micro Devices, Inc.
5 */
6 #include <asm/cpu_device_id.h>
7
8 #include <linux/bits.h>
9 #include <linux/cpu.h>
10 #include <linux/cpumask.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/hwmon.h>
14 #include <linux/kernel.h>
15 #include <linux/kthread.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/processor.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/topology.h>
24 #include <linux/types.h>
25
26 #define DRVNAME "amd_energy"
27
28 #define ENERGY_PWR_UNIT_MSR 0xC0010299
29 #define ENERGY_CORE_MSR 0xC001029A
30 #define ENERGY_PKG_MSR 0xC001029B
31
32 #define AMD_ENERGY_UNIT_MASK 0x01F00
33 #define AMD_ENERGY_MASK 0xFFFFFFFF
34
35 struct sensor_accumulator {
36 u64 energy_ctr;
37 u64 prev_value;
38 };
39
40 struct amd_energy_data {
41 struct hwmon_channel_info energy_info;
42 const struct hwmon_channel_info *info[2];
43 struct hwmon_chip_info chip;
44 struct task_struct *wrap_accumulate;
45 /* Lock around the accumulator */
46 struct mutex lock;
47 /* An accumulator for each core and socket */
48 struct sensor_accumulator *accums;
49 unsigned int timeout_ms;
50 /* Energy Status Units */
51 int energy_units;
52 int nr_cpus;
53 int nr_socks;
54 int core_id;
55 char (*label)[10];
56 };
57
amd_energy_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)58 static int amd_energy_read_labels(struct device *dev,
59 enum hwmon_sensor_types type,
60 u32 attr, int channel,
61 const char **str)
62 {
63 struct amd_energy_data *data = dev_get_drvdata(dev);
64
65 *str = data->label[channel];
66 return 0;
67 }
68
get_energy_units(struct amd_energy_data * data)69 static void get_energy_units(struct amd_energy_data *data)
70 {
71 u64 rapl_units;
72
73 rdmsrl_safe(ENERGY_PWR_UNIT_MSR, &rapl_units);
74 data->energy_units = (rapl_units & AMD_ENERGY_UNIT_MASK) >> 8;
75 }
76
accumulate_delta(struct amd_energy_data * data,int channel,int cpu,u32 reg)77 static void accumulate_delta(struct amd_energy_data *data,
78 int channel, int cpu, u32 reg)
79 {
80 struct sensor_accumulator *accum;
81 u64 input;
82
83 mutex_lock(&data->lock);
84 rdmsrl_safe_on_cpu(cpu, reg, &input);
85 input &= AMD_ENERGY_MASK;
86
87 accum = &data->accums[channel];
88 if (input >= accum->prev_value)
89 accum->energy_ctr +=
90 input - accum->prev_value;
91 else
92 accum->energy_ctr += UINT_MAX -
93 accum->prev_value + input;
94
95 accum->prev_value = input;
96 mutex_unlock(&data->lock);
97 }
98
read_accumulate(struct amd_energy_data * data)99 static void read_accumulate(struct amd_energy_data *data)
100 {
101 int sock, scpu, cpu;
102
103 for (sock = 0; sock < data->nr_socks; sock++) {
104 scpu = cpumask_first_and(cpu_online_mask,
105 cpumask_of_node(sock));
106
107 accumulate_delta(data, data->nr_cpus + sock,
108 scpu, ENERGY_PKG_MSR);
109 }
110
111 if (data->core_id >= data->nr_cpus)
112 data->core_id = 0;
113
114 cpu = data->core_id;
115 if (cpu_online(cpu))
116 accumulate_delta(data, cpu, cpu, ENERGY_CORE_MSR);
117
118 data->core_id++;
119 }
120
amd_add_delta(struct amd_energy_data * data,int ch,int cpu,long * val,u32 reg)121 static void amd_add_delta(struct amd_energy_data *data, int ch,
122 int cpu, long *val, u32 reg)
123 {
124 struct sensor_accumulator *accum;
125 u64 input;
126
127 mutex_lock(&data->lock);
128 rdmsrl_safe_on_cpu(cpu, reg, &input);
129 input &= AMD_ENERGY_MASK;
130
131 accum = &data->accums[ch];
132 if (input >= accum->prev_value)
133 input += accum->energy_ctr -
134 accum->prev_value;
135 else
136 input += UINT_MAX - accum->prev_value +
137 accum->energy_ctr;
138
139 /* Energy consumed = (1/(2^ESU) * RAW * 1000000UL) μJoules */
140 *val = div64_ul(input * 1000000UL, BIT(data->energy_units));
141
142 mutex_unlock(&data->lock);
143 }
144
amd_energy_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)145 static int amd_energy_read(struct device *dev,
146 enum hwmon_sensor_types type,
147 u32 attr, int channel, long *val)
148 {
149 struct amd_energy_data *data = dev_get_drvdata(dev);
150 u32 reg;
151 int cpu;
152
153 if (channel >= data->nr_cpus) {
154 cpu = cpumask_first_and(cpu_online_mask,
155 cpumask_of_node
156 (channel - data->nr_cpus));
157 reg = ENERGY_PKG_MSR;
158 } else {
159 cpu = channel;
160 if (!cpu_online(cpu))
161 return -ENODEV;
162
163 reg = ENERGY_CORE_MSR;
164 }
165 amd_add_delta(data, channel, cpu, val, reg);
166
167 return 0;
168 }
169
amd_energy_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)170 static umode_t amd_energy_is_visible(const void *_data,
171 enum hwmon_sensor_types type,
172 u32 attr, int channel)
173 {
174 return 0440;
175 }
176
energy_accumulator(void * p)177 static int energy_accumulator(void *p)
178 {
179 struct amd_energy_data *data = (struct amd_energy_data *)p;
180 unsigned int timeout = data->timeout_ms;
181
182 while (!kthread_should_stop()) {
183 /*
184 * Ignoring the conditions such as
185 * cpu being offline or rdmsr failure
186 */
187 read_accumulate(data);
188
189 set_current_state(TASK_INTERRUPTIBLE);
190 if (kthread_should_stop())
191 break;
192
193 schedule_timeout(msecs_to_jiffies(timeout));
194 }
195 return 0;
196 }
197
198 static const struct hwmon_ops amd_energy_ops = {
199 .is_visible = amd_energy_is_visible,
200 .read = amd_energy_read,
201 .read_string = amd_energy_read_labels,
202 };
203
amd_create_sensor(struct device * dev,struct amd_energy_data * data,enum hwmon_sensor_types type,u32 config)204 static int amd_create_sensor(struct device *dev,
205 struct amd_energy_data *data,
206 enum hwmon_sensor_types type, u32 config)
207 {
208 struct hwmon_channel_info *info = &data->energy_info;
209 struct sensor_accumulator *accums;
210 int i, num_siblings, cpus, sockets;
211 u32 *s_config;
212 char (*label_l)[10];
213
214 /* Identify the number of siblings per core */
215 num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
216
217 sockets = num_possible_nodes();
218
219 /*
220 * Energy counter register is accessed at core level.
221 * Hence, filterout the siblings.
222 */
223 cpus = num_present_cpus() / num_siblings;
224
225 s_config = devm_kcalloc(dev, cpus + sockets,
226 sizeof(u32), GFP_KERNEL);
227 if (!s_config)
228 return -ENOMEM;
229
230 accums = devm_kcalloc(dev, cpus + sockets,
231 sizeof(struct sensor_accumulator),
232 GFP_KERNEL);
233 if (!accums)
234 return -ENOMEM;
235
236 label_l = devm_kcalloc(dev, cpus + sockets,
237 sizeof(*label_l), GFP_KERNEL);
238 if (!label_l)
239 return -ENOMEM;
240
241 info->type = type;
242 info->config = s_config;
243
244 data->nr_cpus = cpus;
245 data->nr_socks = sockets;
246 data->accums = accums;
247 data->label = label_l;
248
249 for (i = 0; i < cpus + sockets; i++) {
250 s_config[i] = config;
251 if (i < cpus)
252 scnprintf(label_l[i], 10, "Ecore%03u", i);
253 else
254 scnprintf(label_l[i], 10, "Esocket%u", (i - cpus));
255 }
256
257 return 0;
258 }
259
amd_energy_probe(struct platform_device * pdev)260 static int amd_energy_probe(struct platform_device *pdev)
261 {
262 struct device *hwmon_dev;
263 struct amd_energy_data *data;
264 struct device *dev = &pdev->dev;
265 int ret;
266
267 data = devm_kzalloc(dev,
268 sizeof(struct amd_energy_data), GFP_KERNEL);
269 if (!data)
270 return -ENOMEM;
271
272 data->chip.ops = &amd_energy_ops;
273 data->chip.info = data->info;
274
275 dev_set_drvdata(dev, data);
276 /* Populate per-core energy reporting */
277 data->info[0] = &data->energy_info;
278 ret = amd_create_sensor(dev, data, hwmon_energy,
279 HWMON_E_INPUT | HWMON_E_LABEL);
280 if (ret)
281 return ret;
282
283 mutex_init(&data->lock);
284 get_energy_units(data);
285
286 hwmon_dev = devm_hwmon_device_register_with_info(dev, DRVNAME,
287 data,
288 &data->chip,
289 NULL);
290 if (IS_ERR(hwmon_dev))
291 return PTR_ERR(hwmon_dev);
292
293 /*
294 * On a system with peak wattage of 250W
295 * timeout = 2 ^ 32 / 2 ^ energy_units / 250 secs
296 */
297 data->timeout_ms = 1000 *
298 BIT(min(28, 31 - data->energy_units)) / 250;
299
300 data->wrap_accumulate = kthread_run(energy_accumulator, data,
301 "%s", dev_name(hwmon_dev));
302 return PTR_ERR_OR_ZERO(data->wrap_accumulate);
303 }
304
amd_energy_remove(struct platform_device * pdev)305 static int amd_energy_remove(struct platform_device *pdev)
306 {
307 struct amd_energy_data *data = dev_get_drvdata(&pdev->dev);
308
309 if (data && data->wrap_accumulate)
310 kthread_stop(data->wrap_accumulate);
311
312 return 0;
313 }
314
315 static const struct platform_device_id amd_energy_ids[] = {
316 { .name = DRVNAME, },
317 {}
318 };
319 MODULE_DEVICE_TABLE(platform, amd_energy_ids);
320
321 static struct platform_driver amd_energy_driver = {
322 .probe = amd_energy_probe,
323 .remove = amd_energy_remove,
324 .id_table = amd_energy_ids,
325 .driver = {
326 .name = DRVNAME,
327 },
328 };
329
330 static struct platform_device *amd_energy_platdev;
331
332 static const struct x86_cpu_id cpu_ids[] __initconst = {
333 X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x17, 0x31, NULL),
334 {}
335 };
336 MODULE_DEVICE_TABLE(x86cpu, cpu_ids);
337
amd_energy_init(void)338 static int __init amd_energy_init(void)
339 {
340 int ret;
341
342 if (!x86_match_cpu(cpu_ids))
343 return -ENODEV;
344
345 ret = platform_driver_register(&amd_energy_driver);
346 if (ret)
347 return ret;
348
349 amd_energy_platdev = platform_device_alloc(DRVNAME, 0);
350 if (!amd_energy_platdev) {
351 platform_driver_unregister(&amd_energy_driver);
352 return -ENOMEM;
353 }
354
355 ret = platform_device_add(amd_energy_platdev);
356 if (ret) {
357 platform_device_put(amd_energy_platdev);
358 platform_driver_unregister(&amd_energy_driver);
359 return ret;
360 }
361
362 return ret;
363 }
364
amd_energy_exit(void)365 static void __exit amd_energy_exit(void)
366 {
367 platform_device_unregister(amd_energy_platdev);
368 platform_driver_unregister(&amd_energy_driver);
369 }
370
371 module_init(amd_energy_init);
372 module_exit(amd_energy_exit);
373
374 MODULE_DESCRIPTION("Driver for AMD Energy reporting from RAPL MSR via HWMON interface");
375 MODULE_AUTHOR("Naveen Krishna Chatradhi <nchatrad@amd.com>");
376 MODULE_LICENSE("GPL");
377