1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "gen2_engine_cs.h"
31 #include "gen6_engine_cs.h"
32 #include "gen6_ppgtt.h"
33 #include "gen7_renderclear.h"
34 #include "i915_drv.h"
35 #include "intel_breadcrumbs.h"
36 #include "intel_context.h"
37 #include "intel_gt.h"
38 #include "intel_reset.h"
39 #include "intel_ring.h"
40 #include "shmem_utils.h"
41
42 /* Rough estimate of the typical request size, performing a flush,
43 * set-context and then emitting the batch.
44 */
45 #define LEGACY_REQUEST_SIZE 200
46
set_hwstam(struct intel_engine_cs * engine,u32 mask)47 static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
48 {
49 /*
50 * Keep the render interrupt unmasked as this papers over
51 * lost interrupts following a reset.
52 */
53 if (engine->class == RENDER_CLASS) {
54 if (INTEL_GEN(engine->i915) >= 6)
55 mask &= ~BIT(0);
56 else
57 mask &= ~I915_USER_INTERRUPT;
58 }
59
60 intel_engine_set_hwsp_writemask(engine, mask);
61 }
62
set_hws_pga(struct intel_engine_cs * engine,phys_addr_t phys)63 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
64 {
65 u32 addr;
66
67 addr = lower_32_bits(phys);
68 if (INTEL_GEN(engine->i915) >= 4)
69 addr |= (phys >> 28) & 0xf0;
70
71 intel_uncore_write(engine->uncore, HWS_PGA, addr);
72 }
73
status_page(struct intel_engine_cs * engine)74 static struct page *status_page(struct intel_engine_cs *engine)
75 {
76 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
77
78 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
79 return sg_page(obj->mm.pages->sgl);
80 }
81
ring_setup_phys_status_page(struct intel_engine_cs * engine)82 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
83 {
84 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
85 set_hwstam(engine, ~0u);
86 }
87
set_hwsp(struct intel_engine_cs * engine,u32 offset)88 static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
89 {
90 i915_reg_t hwsp;
91
92 /*
93 * The ring status page addresses are no longer next to the rest of
94 * the ring registers as of gen7.
95 */
96 if (IS_GEN(engine->i915, 7)) {
97 switch (engine->id) {
98 /*
99 * No more rings exist on Gen7. Default case is only to shut up
100 * gcc switch check warning.
101 */
102 default:
103 GEM_BUG_ON(engine->id);
104 fallthrough;
105 case RCS0:
106 hwsp = RENDER_HWS_PGA_GEN7;
107 break;
108 case BCS0:
109 hwsp = BLT_HWS_PGA_GEN7;
110 break;
111 case VCS0:
112 hwsp = BSD_HWS_PGA_GEN7;
113 break;
114 case VECS0:
115 hwsp = VEBOX_HWS_PGA_GEN7;
116 break;
117 }
118 } else if (IS_GEN(engine->i915, 6)) {
119 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
120 } else {
121 hwsp = RING_HWS_PGA(engine->mmio_base);
122 }
123
124 intel_uncore_write(engine->uncore, hwsp, offset);
125 intel_uncore_posting_read(engine->uncore, hwsp);
126 }
127
flush_cs_tlb(struct intel_engine_cs * engine)128 static void flush_cs_tlb(struct intel_engine_cs *engine)
129 {
130 struct drm_i915_private *dev_priv = engine->i915;
131
132 if (!IS_GEN_RANGE(dev_priv, 6, 7))
133 return;
134
135 /* ring should be idle before issuing a sync flush*/
136 drm_WARN_ON(&dev_priv->drm,
137 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
138
139 ENGINE_WRITE(engine, RING_INSTPM,
140 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
141 INSTPM_SYNC_FLUSH));
142 if (intel_wait_for_register(engine->uncore,
143 RING_INSTPM(engine->mmio_base),
144 INSTPM_SYNC_FLUSH, 0,
145 1000))
146 drm_err(&dev_priv->drm,
147 "%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
148 engine->name);
149 }
150
ring_setup_status_page(struct intel_engine_cs * engine)151 static void ring_setup_status_page(struct intel_engine_cs *engine)
152 {
153 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
154 set_hwstam(engine, ~0u);
155
156 flush_cs_tlb(engine);
157 }
158
stop_ring(struct intel_engine_cs * engine)159 static bool stop_ring(struct intel_engine_cs *engine)
160 {
161 struct drm_i915_private *dev_priv = engine->i915;
162
163 if (INTEL_GEN(dev_priv) > 2) {
164 ENGINE_WRITE(engine,
165 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
166 if (intel_wait_for_register(engine->uncore,
167 RING_MI_MODE(engine->mmio_base),
168 MODE_IDLE,
169 MODE_IDLE,
170 1000)) {
171 drm_err(&dev_priv->drm,
172 "%s : timed out trying to stop ring\n",
173 engine->name);
174
175 /*
176 * Sometimes we observe that the idle flag is not
177 * set even though the ring is empty. So double
178 * check before giving up.
179 */
180 if (ENGINE_READ(engine, RING_HEAD) !=
181 ENGINE_READ(engine, RING_TAIL))
182 return false;
183 }
184 }
185
186 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
187
188 ENGINE_WRITE(engine, RING_HEAD, 0);
189 ENGINE_WRITE(engine, RING_TAIL, 0);
190
191 /* The ring must be empty before it is disabled */
192 ENGINE_WRITE(engine, RING_CTL, 0);
193
194 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
195 }
196
vm_alias(struct i915_address_space * vm)197 static struct i915_address_space *vm_alias(struct i915_address_space *vm)
198 {
199 if (i915_is_ggtt(vm))
200 vm = &i915_vm_to_ggtt(vm)->alias->vm;
201
202 return vm;
203 }
204
pp_dir(struct i915_address_space * vm)205 static u32 pp_dir(struct i915_address_space *vm)
206 {
207 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir;
208 }
209
set_pp_dir(struct intel_engine_cs * engine)210 static void set_pp_dir(struct intel_engine_cs *engine)
211 {
212 struct i915_address_space *vm = vm_alias(engine->gt->vm);
213
214 if (vm) {
215 ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
216 ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
217 }
218 }
219
xcs_resume(struct intel_engine_cs * engine)220 static int xcs_resume(struct intel_engine_cs *engine)
221 {
222 struct drm_i915_private *dev_priv = engine->i915;
223 struct intel_ring *ring = engine->legacy.ring;
224 int ret = 0;
225
226 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
227 ring->head, ring->tail);
228
229 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
230
231 /* WaClearRingBufHeadRegAtInit:ctg,elk */
232 if (!stop_ring(engine)) {
233 /* G45 ring initialization often fails to reset head to zero */
234 drm_dbg(&dev_priv->drm, "%s head not reset to zero "
235 "ctl %08x head %08x tail %08x start %08x\n",
236 engine->name,
237 ENGINE_READ(engine, RING_CTL),
238 ENGINE_READ(engine, RING_HEAD),
239 ENGINE_READ(engine, RING_TAIL),
240 ENGINE_READ(engine, RING_START));
241
242 if (!stop_ring(engine)) {
243 drm_err(&dev_priv->drm,
244 "failed to set %s head to zero "
245 "ctl %08x head %08x tail %08x start %08x\n",
246 engine->name,
247 ENGINE_READ(engine, RING_CTL),
248 ENGINE_READ(engine, RING_HEAD),
249 ENGINE_READ(engine, RING_TAIL),
250 ENGINE_READ(engine, RING_START));
251 ret = -EIO;
252 goto out;
253 }
254 }
255
256 if (HWS_NEEDS_PHYSICAL(dev_priv))
257 ring_setup_phys_status_page(engine);
258 else
259 ring_setup_status_page(engine);
260
261 intel_breadcrumbs_reset(engine->breadcrumbs);
262
263 /* Enforce ordering by reading HEAD register back */
264 ENGINE_POSTING_READ(engine, RING_HEAD);
265
266 /*
267 * Initialize the ring. This must happen _after_ we've cleared the ring
268 * registers with the above sequence (the readback of the HEAD registers
269 * also enforces ordering), otherwise the hw might lose the new ring
270 * register values.
271 */
272 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
273
274 /* Check that the ring offsets point within the ring! */
275 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
276 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
277 intel_ring_update_space(ring);
278
279 set_pp_dir(engine);
280
281 /* First wake the ring up to an empty/idle ring */
282 ENGINE_WRITE(engine, RING_HEAD, ring->head);
283 ENGINE_WRITE(engine, RING_TAIL, ring->head);
284 ENGINE_POSTING_READ(engine, RING_TAIL);
285
286 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
287
288 /* If the head is still not zero, the ring is dead */
289 if (intel_wait_for_register(engine->uncore,
290 RING_CTL(engine->mmio_base),
291 RING_VALID, RING_VALID,
292 50)) {
293 drm_err(&dev_priv->drm, "%s initialization failed "
294 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
295 engine->name,
296 ENGINE_READ(engine, RING_CTL),
297 ENGINE_READ(engine, RING_CTL) & RING_VALID,
298 ENGINE_READ(engine, RING_HEAD), ring->head,
299 ENGINE_READ(engine, RING_TAIL), ring->tail,
300 ENGINE_READ(engine, RING_START),
301 i915_ggtt_offset(ring->vma));
302 ret = -EIO;
303 goto out;
304 }
305
306 if (INTEL_GEN(dev_priv) > 2)
307 ENGINE_WRITE(engine,
308 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
309
310 /* Now awake, let it get started */
311 if (ring->tail != ring->head) {
312 ENGINE_WRITE(engine, RING_TAIL, ring->tail);
313 ENGINE_POSTING_READ(engine, RING_TAIL);
314 }
315
316 /* Papering over lost _interrupts_ immediately following the restart */
317 intel_engine_signal_breadcrumbs(engine);
318 out:
319 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
320
321 return ret;
322 }
323
reset_prepare(struct intel_engine_cs * engine)324 static void reset_prepare(struct intel_engine_cs *engine)
325 {
326 struct intel_uncore *uncore = engine->uncore;
327 const u32 base = engine->mmio_base;
328
329 /*
330 * We stop engines, otherwise we might get failed reset and a
331 * dead gpu (on elk). Also as modern gpu as kbl can suffer
332 * from system hang if batchbuffer is progressing when
333 * the reset is issued, regardless of READY_TO_RESET ack.
334 * Thus assume it is best to stop engines on all gens
335 * where we have a gpu reset.
336 *
337 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
338 *
339 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
340 *
341 * FIXME: Wa for more modern gens needs to be validated
342 */
343 ENGINE_TRACE(engine, "\n");
344
345 if (intel_engine_stop_cs(engine))
346 ENGINE_TRACE(engine, "timed out on STOP_RING\n");
347
348 intel_uncore_write_fw(uncore,
349 RING_HEAD(base),
350 intel_uncore_read_fw(uncore, RING_TAIL(base)));
351 intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
352
353 intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
354 intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
355 intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
356
357 /* The ring must be empty before it is disabled */
358 intel_uncore_write_fw(uncore, RING_CTL(base), 0);
359
360 /* Check acts as a post */
361 if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
362 ENGINE_TRACE(engine, "ring head [%x] not parked\n",
363 intel_uncore_read_fw(uncore, RING_HEAD(base)));
364 }
365
reset_rewind(struct intel_engine_cs * engine,bool stalled)366 static void reset_rewind(struct intel_engine_cs *engine, bool stalled)
367 {
368 struct i915_request *pos, *rq;
369 unsigned long flags;
370 u32 head;
371
372 rq = NULL;
373 spin_lock_irqsave(&engine->active.lock, flags);
374 list_for_each_entry(pos, &engine->active.requests, sched.link) {
375 if (!i915_request_completed(pos)) {
376 rq = pos;
377 break;
378 }
379 }
380
381 /*
382 * The guilty request will get skipped on a hung engine.
383 *
384 * Users of client default contexts do not rely on logical
385 * state preserved between batches so it is safe to execute
386 * queued requests following the hang. Non default contexts
387 * rely on preserved state, so skipping a batch loses the
388 * evolution of the state and it needs to be considered corrupted.
389 * Executing more queued batches on top of corrupted state is
390 * risky. But we take the risk by trying to advance through
391 * the queued requests in order to make the client behaviour
392 * more predictable around resets, by not throwing away random
393 * amount of batches it has prepared for execution. Sophisticated
394 * clients can use gem_reset_stats_ioctl and dma fence status
395 * (exported via sync_file info ioctl on explicit fences) to observe
396 * when it loses the context state and should rebuild accordingly.
397 *
398 * The context ban, and ultimately the client ban, mechanism are safety
399 * valves if client submission ends up resulting in nothing more than
400 * subsequent hangs.
401 */
402
403 if (rq) {
404 /*
405 * Try to restore the logical GPU state to match the
406 * continuation of the request queue. If we skip the
407 * context/PD restore, then the next request may try to execute
408 * assuming that its context is valid and loaded on the GPU and
409 * so may try to access invalid memory, prompting repeated GPU
410 * hangs.
411 *
412 * If the request was guilty, we still restore the logical
413 * state in case the next request requires it (e.g. the
414 * aliasing ppgtt), but skip over the hung batch.
415 *
416 * If the request was innocent, we try to replay the request
417 * with the restored context.
418 */
419 __i915_request_reset(rq, stalled);
420
421 GEM_BUG_ON(rq->ring != engine->legacy.ring);
422 head = rq->head;
423 } else {
424 head = engine->legacy.ring->tail;
425 }
426 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);
427
428 spin_unlock_irqrestore(&engine->active.lock, flags);
429 }
430
reset_finish(struct intel_engine_cs * engine)431 static void reset_finish(struct intel_engine_cs *engine)
432 {
433 }
434
reset_cancel(struct intel_engine_cs * engine)435 static void reset_cancel(struct intel_engine_cs *engine)
436 {
437 struct i915_request *request;
438 unsigned long flags;
439
440 spin_lock_irqsave(&engine->active.lock, flags);
441
442 /* Mark all submitted requests as skipped. */
443 list_for_each_entry(request, &engine->active.requests, sched.link) {
444 i915_request_set_error_once(request, -EIO);
445 i915_request_mark_complete(request);
446 }
447
448 /* Remaining _unready_ requests will be nop'ed when submitted */
449
450 spin_unlock_irqrestore(&engine->active.lock, flags);
451 }
452
i9xx_submit_request(struct i915_request * request)453 static void i9xx_submit_request(struct i915_request *request)
454 {
455 i915_request_submit(request);
456 wmb(); /* paranoid flush writes out of the WCB before mmio */
457
458 ENGINE_WRITE(request->engine, RING_TAIL,
459 intel_ring_set_tail(request->ring, request->tail));
460 }
461
__ring_context_fini(struct intel_context * ce)462 static void __ring_context_fini(struct intel_context *ce)
463 {
464 i915_vma_put(ce->state);
465 }
466
ring_context_destroy(struct kref * ref)467 static void ring_context_destroy(struct kref *ref)
468 {
469 struct intel_context *ce = container_of(ref, typeof(*ce), ref);
470
471 GEM_BUG_ON(intel_context_is_pinned(ce));
472
473 if (ce->state)
474 __ring_context_fini(ce);
475
476 intel_context_fini(ce);
477 intel_context_free(ce);
478 }
479
ring_context_pre_pin(struct intel_context * ce,struct i915_gem_ww_ctx * ww,void ** unused)480 static int ring_context_pre_pin(struct intel_context *ce,
481 struct i915_gem_ww_ctx *ww,
482 void **unused)
483 {
484 struct i915_address_space *vm;
485 int err = 0;
486
487 vm = vm_alias(ce->vm);
488 if (vm)
489 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww);
490
491 return err;
492 }
493
__context_unpin_ppgtt(struct intel_context * ce)494 static void __context_unpin_ppgtt(struct intel_context *ce)
495 {
496 struct i915_address_space *vm;
497
498 vm = vm_alias(ce->vm);
499 if (vm)
500 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
501 }
502
ring_context_unpin(struct intel_context * ce)503 static void ring_context_unpin(struct intel_context *ce)
504 {
505 }
506
ring_context_post_unpin(struct intel_context * ce)507 static void ring_context_post_unpin(struct intel_context *ce)
508 {
509 __context_unpin_ppgtt(ce);
510 }
511
512 static struct i915_vma *
alloc_context_vma(struct intel_engine_cs * engine)513 alloc_context_vma(struct intel_engine_cs *engine)
514 {
515 struct drm_i915_private *i915 = engine->i915;
516 struct drm_i915_gem_object *obj;
517 struct i915_vma *vma;
518 int err;
519
520 obj = i915_gem_object_create_shmem(i915, engine->context_size);
521 if (IS_ERR(obj))
522 return ERR_CAST(obj);
523
524 /*
525 * Try to make the context utilize L3 as well as LLC.
526 *
527 * On VLV we don't have L3 controls in the PTEs so we
528 * shouldn't touch the cache level, especially as that
529 * would make the object snooped which might have a
530 * negative performance impact.
531 *
532 * Snooping is required on non-llc platforms in execlist
533 * mode, but since all GGTT accesses use PAT entry 0 we
534 * get snooping anyway regardless of cache_level.
535 *
536 * This is only applicable for Ivy Bridge devices since
537 * later platforms don't have L3 control bits in the PTE.
538 */
539 if (IS_IVYBRIDGE(i915))
540 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
541
542 if (engine->default_state) {
543 void *vaddr;
544
545 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
546 if (IS_ERR(vaddr)) {
547 err = PTR_ERR(vaddr);
548 goto err_obj;
549 }
550
551 shmem_read(engine->default_state, 0,
552 vaddr, engine->context_size);
553
554 i915_gem_object_flush_map(obj);
555 __i915_gem_object_release_map(obj);
556 }
557
558 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
559 if (IS_ERR(vma)) {
560 err = PTR_ERR(vma);
561 goto err_obj;
562 }
563
564 return vma;
565
566 err_obj:
567 i915_gem_object_put(obj);
568 return ERR_PTR(err);
569 }
570
ring_context_alloc(struct intel_context * ce)571 static int ring_context_alloc(struct intel_context *ce)
572 {
573 struct intel_engine_cs *engine = ce->engine;
574
575 /* One ringbuffer to rule them all */
576 GEM_BUG_ON(!engine->legacy.ring);
577 ce->ring = engine->legacy.ring;
578 ce->timeline = intel_timeline_get(engine->legacy.timeline);
579
580 GEM_BUG_ON(ce->state);
581 if (engine->context_size) {
582 struct i915_vma *vma;
583
584 vma = alloc_context_vma(engine);
585 if (IS_ERR(vma))
586 return PTR_ERR(vma);
587
588 ce->state = vma;
589 if (engine->default_state)
590 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
591 }
592
593 return 0;
594 }
595
ring_context_pin(struct intel_context * ce,void * unused)596 static int ring_context_pin(struct intel_context *ce, void *unused)
597 {
598 return 0;
599 }
600
ring_context_reset(struct intel_context * ce)601 static void ring_context_reset(struct intel_context *ce)
602 {
603 intel_ring_reset(ce->ring, ce->ring->emit);
604 }
605
606 static const struct intel_context_ops ring_context_ops = {
607 .alloc = ring_context_alloc,
608
609 .pre_pin = ring_context_pre_pin,
610 .pin = ring_context_pin,
611 .unpin = ring_context_unpin,
612 .post_unpin = ring_context_post_unpin,
613
614 .enter = intel_context_enter_engine,
615 .exit = intel_context_exit_engine,
616
617 .reset = ring_context_reset,
618 .destroy = ring_context_destroy,
619 };
620
load_pd_dir(struct i915_request * rq,struct i915_address_space * vm,u32 valid)621 static int load_pd_dir(struct i915_request *rq,
622 struct i915_address_space *vm,
623 u32 valid)
624 {
625 const struct intel_engine_cs * const engine = rq->engine;
626 u32 *cs;
627
628 cs = intel_ring_begin(rq, 12);
629 if (IS_ERR(cs))
630 return PTR_ERR(cs);
631
632 *cs++ = MI_LOAD_REGISTER_IMM(1);
633 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
634 *cs++ = valid;
635
636 *cs++ = MI_LOAD_REGISTER_IMM(1);
637 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
638 *cs++ = pp_dir(vm);
639
640 /* Stall until the page table load is complete? */
641 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
642 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
643 *cs++ = intel_gt_scratch_offset(engine->gt,
644 INTEL_GT_SCRATCH_FIELD_DEFAULT);
645
646 *cs++ = MI_LOAD_REGISTER_IMM(1);
647 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
648 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
649
650 intel_ring_advance(rq, cs);
651
652 return rq->engine->emit_flush(rq, EMIT_FLUSH);
653 }
654
mi_set_context(struct i915_request * rq,struct intel_context * ce,u32 flags)655 static inline int mi_set_context(struct i915_request *rq,
656 struct intel_context *ce,
657 u32 flags)
658 {
659 struct intel_engine_cs *engine = rq->engine;
660 struct drm_i915_private *i915 = engine->i915;
661 enum intel_engine_id id;
662 const int num_engines =
663 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
664 bool force_restore = false;
665 int len;
666 u32 *cs;
667
668 len = 4;
669 if (IS_GEN(i915, 7))
670 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
671 else if (IS_GEN(i915, 5))
672 len += 2;
673 if (flags & MI_FORCE_RESTORE) {
674 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
675 flags &= ~MI_FORCE_RESTORE;
676 force_restore = true;
677 len += 2;
678 }
679
680 cs = intel_ring_begin(rq, len);
681 if (IS_ERR(cs))
682 return PTR_ERR(cs);
683
684 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
685 if (IS_GEN(i915, 7)) {
686 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
687 if (num_engines) {
688 struct intel_engine_cs *signaller;
689
690 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
691 for_each_engine(signaller, engine->gt, id) {
692 if (signaller == engine)
693 continue;
694
695 *cs++ = i915_mmio_reg_offset(
696 RING_PSMI_CTL(signaller->mmio_base));
697 *cs++ = _MASKED_BIT_ENABLE(
698 GEN6_PSMI_SLEEP_MSG_DISABLE);
699 }
700 }
701 } else if (IS_GEN(i915, 5)) {
702 /*
703 * This w/a is only listed for pre-production ilk a/b steppings,
704 * but is also mentioned for programming the powerctx. To be
705 * safe, just apply the workaround; we do not use SyncFlush so
706 * this should never take effect and so be a no-op!
707 */
708 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
709 }
710
711 if (force_restore) {
712 /*
713 * The HW doesn't handle being told to restore the current
714 * context very well. Quite often it likes goes to go off and
715 * sulk, especially when it is meant to be reloading PP_DIR.
716 * A very simple fix to force the reload is to simply switch
717 * away from the current context and back again.
718 *
719 * Note that the kernel_context will contain random state
720 * following the INHIBIT_RESTORE. We accept this since we
721 * never use the kernel_context state; it is merely a
722 * placeholder we use to flush other contexts.
723 */
724 *cs++ = MI_SET_CONTEXT;
725 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
726 MI_MM_SPACE_GTT |
727 MI_RESTORE_INHIBIT;
728 }
729
730 *cs++ = MI_NOOP;
731 *cs++ = MI_SET_CONTEXT;
732 *cs++ = i915_ggtt_offset(ce->state) | flags;
733 /*
734 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
735 * WaMiSetContext_Hang:snb,ivb,vlv
736 */
737 *cs++ = MI_NOOP;
738
739 if (IS_GEN(i915, 7)) {
740 if (num_engines) {
741 struct intel_engine_cs *signaller;
742 i915_reg_t last_reg = {}; /* keep gcc quiet */
743
744 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
745 for_each_engine(signaller, engine->gt, id) {
746 if (signaller == engine)
747 continue;
748
749 last_reg = RING_PSMI_CTL(signaller->mmio_base);
750 *cs++ = i915_mmio_reg_offset(last_reg);
751 *cs++ = _MASKED_BIT_DISABLE(
752 GEN6_PSMI_SLEEP_MSG_DISABLE);
753 }
754
755 /* Insert a delay before the next switch! */
756 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
757 *cs++ = i915_mmio_reg_offset(last_reg);
758 *cs++ = intel_gt_scratch_offset(engine->gt,
759 INTEL_GT_SCRATCH_FIELD_DEFAULT);
760 *cs++ = MI_NOOP;
761 }
762 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
763 } else if (IS_GEN(i915, 5)) {
764 *cs++ = MI_SUSPEND_FLUSH;
765 }
766
767 intel_ring_advance(rq, cs);
768
769 return 0;
770 }
771
remap_l3_slice(struct i915_request * rq,int slice)772 static int remap_l3_slice(struct i915_request *rq, int slice)
773 {
774 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
775 int i;
776
777 if (!remap_info)
778 return 0;
779
780 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
781 if (IS_ERR(cs))
782 return PTR_ERR(cs);
783
784 /*
785 * Note: We do not worry about the concurrent register cacheline hang
786 * here because no other code should access these registers other than
787 * at initialization time.
788 */
789 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
790 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
791 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
792 *cs++ = remap_info[i];
793 }
794 *cs++ = MI_NOOP;
795 intel_ring_advance(rq, cs);
796
797 return 0;
798 }
799
remap_l3(struct i915_request * rq)800 static int remap_l3(struct i915_request *rq)
801 {
802 struct i915_gem_context *ctx = i915_request_gem_context(rq);
803 int i, err;
804
805 if (!ctx || !ctx->remap_slice)
806 return 0;
807
808 for (i = 0; i < MAX_L3_SLICES; i++) {
809 if (!(ctx->remap_slice & BIT(i)))
810 continue;
811
812 err = remap_l3_slice(rq, i);
813 if (err)
814 return err;
815 }
816
817 ctx->remap_slice = 0;
818 return 0;
819 }
820
switch_mm(struct i915_request * rq,struct i915_address_space * vm)821 static int switch_mm(struct i915_request *rq, struct i915_address_space *vm)
822 {
823 int ret;
824
825 if (!vm)
826 return 0;
827
828 ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
829 if (ret)
830 return ret;
831
832 /*
833 * Not only do we need a full barrier (post-sync write) after
834 * invalidating the TLBs, but we need to wait a little bit
835 * longer. Whether this is merely delaying us, or the
836 * subsequent flush is a key part of serialising with the
837 * post-sync op, this extra pass appears vital before a
838 * mm switch!
839 */
840 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G);
841 if (ret)
842 return ret;
843
844 return rq->engine->emit_flush(rq, EMIT_INVALIDATE);
845 }
846
clear_residuals(struct i915_request * rq)847 static int clear_residuals(struct i915_request *rq)
848 {
849 struct intel_engine_cs *engine = rq->engine;
850 int ret;
851
852 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));
853 if (ret)
854 return ret;
855
856 if (engine->kernel_context->state) {
857 ret = mi_set_context(rq,
858 engine->kernel_context,
859 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT);
860 if (ret)
861 return ret;
862 }
863
864 ret = engine->emit_bb_start(rq,
865 engine->wa_ctx.vma->node.start, 0,
866 0);
867 if (ret)
868 return ret;
869
870 ret = engine->emit_flush(rq, EMIT_FLUSH);
871 if (ret)
872 return ret;
873
874 /* Always invalidate before the next switch_mm() */
875 return engine->emit_flush(rq, EMIT_INVALIDATE);
876 }
877
switch_context(struct i915_request * rq)878 static int switch_context(struct i915_request *rq)
879 {
880 struct intel_engine_cs *engine = rq->engine;
881 struct intel_context *ce = rq->context;
882 void **residuals = NULL;
883 int ret;
884
885 GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
886
887 if (engine->wa_ctx.vma && ce != engine->kernel_context) {
888 if (engine->wa_ctx.vma->private != ce) {
889 ret = clear_residuals(rq);
890 if (ret)
891 return ret;
892
893 residuals = &engine->wa_ctx.vma->private;
894 }
895 }
896
897 ret = switch_mm(rq, vm_alias(ce->vm));
898 if (ret)
899 return ret;
900
901 if (ce->state) {
902 u32 flags;
903
904 GEM_BUG_ON(engine->id != RCS0);
905
906 /* For resource streamer on HSW+ and power context elsewhere */
907 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);
908 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);
909
910 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;
911 if (test_bit(CONTEXT_VALID_BIT, &ce->flags))
912 flags |= MI_RESTORE_EXT_STATE_EN;
913 else
914 flags |= MI_RESTORE_INHIBIT;
915
916 ret = mi_set_context(rq, ce, flags);
917 if (ret)
918 return ret;
919 }
920
921 ret = remap_l3(rq);
922 if (ret)
923 return ret;
924
925 /*
926 * Now past the point of no return, this request _will_ be emitted.
927 *
928 * Or at least this preamble will be emitted, the request may be
929 * interrupted prior to submitting the user payload. If so, we
930 * still submit the "empty" request in order to preserve global
931 * state tracking such as this, our tracking of the current
932 * dirty context.
933 */
934 if (residuals) {
935 intel_context_put(*residuals);
936 *residuals = intel_context_get(ce);
937 }
938
939 return 0;
940 }
941
ring_request_alloc(struct i915_request * request)942 static int ring_request_alloc(struct i915_request *request)
943 {
944 int ret;
945
946 GEM_BUG_ON(!intel_context_is_pinned(request->context));
947 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);
948
949 /*
950 * Flush enough space to reduce the likelihood of waiting after
951 * we start building the request - in which case we will just
952 * have to repeat work.
953 */
954 request->reserved_space += LEGACY_REQUEST_SIZE;
955
956 /* Unconditionally invalidate GPU caches and TLBs. */
957 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
958 if (ret)
959 return ret;
960
961 ret = switch_context(request);
962 if (ret)
963 return ret;
964
965 request->reserved_space -= LEGACY_REQUEST_SIZE;
966 return 0;
967 }
968
gen6_bsd_submit_request(struct i915_request * request)969 static void gen6_bsd_submit_request(struct i915_request *request)
970 {
971 struct intel_uncore *uncore = request->engine->uncore;
972
973 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
974
975 /* Every tail move must follow the sequence below */
976
977 /* Disable notification that the ring is IDLE. The GT
978 * will then assume that it is busy and bring it out of rc6.
979 */
980 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
981 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
982
983 /* Clear the context id. Here be magic! */
984 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
985
986 /* Wait for the ring not to be idle, i.e. for it to wake up. */
987 if (__intel_wait_for_register_fw(uncore,
988 GEN6_BSD_SLEEP_PSMI_CONTROL,
989 GEN6_BSD_SLEEP_INDICATOR,
990 0,
991 1000, 0, NULL))
992 drm_err(&uncore->i915->drm,
993 "timed out waiting for the BSD ring to wake up\n");
994
995 /* Now that the ring is fully powered up, update the tail */
996 i9xx_submit_request(request);
997
998 /* Let the ring send IDLE messages to the GT again,
999 * and so let it sleep to conserve power when idle.
1000 */
1001 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
1002 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1003
1004 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1005 }
1006
i9xx_set_default_submission(struct intel_engine_cs * engine)1007 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
1008 {
1009 engine->submit_request = i9xx_submit_request;
1010
1011 engine->park = NULL;
1012 engine->unpark = NULL;
1013 }
1014
gen6_bsd_set_default_submission(struct intel_engine_cs * engine)1015 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
1016 {
1017 i9xx_set_default_submission(engine);
1018 engine->submit_request = gen6_bsd_submit_request;
1019 }
1020
ring_release(struct intel_engine_cs * engine)1021 static void ring_release(struct intel_engine_cs *engine)
1022 {
1023 struct drm_i915_private *dev_priv = engine->i915;
1024
1025 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
1026 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
1027
1028 intel_engine_cleanup_common(engine);
1029
1030 if (engine->wa_ctx.vma) {
1031 intel_context_put(engine->wa_ctx.vma->private);
1032 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1033 }
1034
1035 intel_ring_unpin(engine->legacy.ring);
1036 intel_ring_put(engine->legacy.ring);
1037
1038 intel_timeline_unpin(engine->legacy.timeline);
1039 intel_timeline_put(engine->legacy.timeline);
1040 }
1041
setup_irq(struct intel_engine_cs * engine)1042 static void setup_irq(struct intel_engine_cs *engine)
1043 {
1044 struct drm_i915_private *i915 = engine->i915;
1045
1046 if (INTEL_GEN(i915) >= 6) {
1047 engine->irq_enable = gen6_irq_enable;
1048 engine->irq_disable = gen6_irq_disable;
1049 } else if (INTEL_GEN(i915) >= 5) {
1050 engine->irq_enable = gen5_irq_enable;
1051 engine->irq_disable = gen5_irq_disable;
1052 } else if (INTEL_GEN(i915) >= 3) {
1053 engine->irq_enable = gen3_irq_enable;
1054 engine->irq_disable = gen3_irq_disable;
1055 } else {
1056 engine->irq_enable = gen2_irq_enable;
1057 engine->irq_disable = gen2_irq_disable;
1058 }
1059 }
1060
setup_common(struct intel_engine_cs * engine)1061 static void setup_common(struct intel_engine_cs *engine)
1062 {
1063 struct drm_i915_private *i915 = engine->i915;
1064
1065 /* gen8+ are only supported with execlists */
1066 GEM_BUG_ON(INTEL_GEN(i915) >= 8);
1067
1068 setup_irq(engine);
1069
1070 engine->resume = xcs_resume;
1071 engine->reset.prepare = reset_prepare;
1072 engine->reset.rewind = reset_rewind;
1073 engine->reset.cancel = reset_cancel;
1074 engine->reset.finish = reset_finish;
1075
1076 engine->cops = &ring_context_ops;
1077 engine->request_alloc = ring_request_alloc;
1078
1079 /*
1080 * Using a global execution timeline; the previous final breadcrumb is
1081 * equivalent to our next initial bread so we can elide
1082 * engine->emit_init_breadcrumb().
1083 */
1084 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
1085 if (IS_GEN(i915, 5))
1086 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
1087
1088 engine->set_default_submission = i9xx_set_default_submission;
1089
1090 if (INTEL_GEN(i915) >= 6)
1091 engine->emit_bb_start = gen6_emit_bb_start;
1092 else if (INTEL_GEN(i915) >= 4)
1093 engine->emit_bb_start = gen4_emit_bb_start;
1094 else if (IS_I830(i915) || IS_I845G(i915))
1095 engine->emit_bb_start = i830_emit_bb_start;
1096 else
1097 engine->emit_bb_start = gen3_emit_bb_start;
1098 }
1099
setup_rcs(struct intel_engine_cs * engine)1100 static void setup_rcs(struct intel_engine_cs *engine)
1101 {
1102 struct drm_i915_private *i915 = engine->i915;
1103
1104 if (HAS_L3_DPF(i915))
1105 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1106
1107 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1108
1109 if (INTEL_GEN(i915) >= 7) {
1110 engine->emit_flush = gen7_emit_flush_rcs;
1111 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
1112 } else if (IS_GEN(i915, 6)) {
1113 engine->emit_flush = gen6_emit_flush_rcs;
1114 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
1115 } else if (IS_GEN(i915, 5)) {
1116 engine->emit_flush = gen4_emit_flush_rcs;
1117 } else {
1118 if (INTEL_GEN(i915) < 4)
1119 engine->emit_flush = gen2_emit_flush;
1120 else
1121 engine->emit_flush = gen4_emit_flush_rcs;
1122 engine->irq_enable_mask = I915_USER_INTERRUPT;
1123 }
1124
1125 if (IS_HASWELL(i915))
1126 engine->emit_bb_start = hsw_emit_bb_start;
1127 }
1128
setup_vcs(struct intel_engine_cs * engine)1129 static void setup_vcs(struct intel_engine_cs *engine)
1130 {
1131 struct drm_i915_private *i915 = engine->i915;
1132
1133 if (INTEL_GEN(i915) >= 6) {
1134 /* gen6 bsd needs a special wa for tail updates */
1135 if (IS_GEN(i915, 6))
1136 engine->set_default_submission = gen6_bsd_set_default_submission;
1137 engine->emit_flush = gen6_emit_flush_vcs;
1138 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1139
1140 if (IS_GEN(i915, 6))
1141 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1142 else
1143 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1144 } else {
1145 engine->emit_flush = gen4_emit_flush_vcs;
1146 if (IS_GEN(i915, 5))
1147 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1148 else
1149 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1150 }
1151 }
1152
setup_bcs(struct intel_engine_cs * engine)1153 static void setup_bcs(struct intel_engine_cs *engine)
1154 {
1155 struct drm_i915_private *i915 = engine->i915;
1156
1157 engine->emit_flush = gen6_emit_flush_xcs;
1158 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1159
1160 if (IS_GEN(i915, 6))
1161 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1162 else
1163 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1164 }
1165
setup_vecs(struct intel_engine_cs * engine)1166 static void setup_vecs(struct intel_engine_cs *engine)
1167 {
1168 struct drm_i915_private *i915 = engine->i915;
1169
1170 GEM_BUG_ON(INTEL_GEN(i915) < 7);
1171
1172 engine->emit_flush = gen6_emit_flush_xcs;
1173 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
1174 engine->irq_enable = hsw_irq_enable_vecs;
1175 engine->irq_disable = hsw_irq_disable_vecs;
1176
1177 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1178 }
1179
gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,struct i915_vma * const vma)1180 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,
1181 struct i915_vma * const vma)
1182 {
1183 return gen7_setup_clear_gpr_bb(engine, vma);
1184 }
1185
gen7_ctx_switch_bb_init(struct intel_engine_cs * engine)1186 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine)
1187 {
1188 struct drm_i915_gem_object *obj;
1189 struct i915_vma *vma;
1190 int size;
1191 int err;
1192
1193 size = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
1194 if (size <= 0)
1195 return size;
1196
1197 size = ALIGN(size, PAGE_SIZE);
1198 obj = i915_gem_object_create_internal(engine->i915, size);
1199 if (IS_ERR(obj))
1200 return PTR_ERR(obj);
1201
1202 vma = i915_vma_instance(obj, engine->gt->vm, NULL);
1203 if (IS_ERR(vma)) {
1204 err = PTR_ERR(vma);
1205 goto err_obj;
1206 }
1207
1208 vma->private = intel_context_create(engine); /* dummy residuals */
1209 if (IS_ERR(vma->private)) {
1210 err = PTR_ERR(vma->private);
1211 goto err_obj;
1212 }
1213
1214 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
1215 if (err)
1216 goto err_private;
1217
1218 err = i915_vma_sync(vma);
1219 if (err)
1220 goto err_unpin;
1221
1222 err = gen7_ctx_switch_bb_setup(engine, vma);
1223 if (err)
1224 goto err_unpin;
1225
1226 engine->wa_ctx.vma = vma;
1227 return 0;
1228
1229 err_unpin:
1230 i915_vma_unpin(vma);
1231 err_private:
1232 intel_context_put(vma->private);
1233 err_obj:
1234 i915_gem_object_put(obj);
1235 return err;
1236 }
1237
intel_ring_submission_setup(struct intel_engine_cs * engine)1238 int intel_ring_submission_setup(struct intel_engine_cs *engine)
1239 {
1240 struct intel_timeline *timeline;
1241 struct intel_ring *ring;
1242 int err;
1243
1244 setup_common(engine);
1245
1246 switch (engine->class) {
1247 case RENDER_CLASS:
1248 setup_rcs(engine);
1249 break;
1250 case VIDEO_DECODE_CLASS:
1251 setup_vcs(engine);
1252 break;
1253 case COPY_ENGINE_CLASS:
1254 setup_bcs(engine);
1255 break;
1256 case VIDEO_ENHANCEMENT_CLASS:
1257 setup_vecs(engine);
1258 break;
1259 default:
1260 MISSING_CASE(engine->class);
1261 return -ENODEV;
1262 }
1263
1264 timeline = intel_timeline_create_from_engine(engine,
1265 I915_GEM_HWS_SEQNO_ADDR);
1266 if (IS_ERR(timeline)) {
1267 err = PTR_ERR(timeline);
1268 goto err;
1269 }
1270 GEM_BUG_ON(timeline->has_initial_breadcrumb);
1271
1272 err = intel_timeline_pin(timeline, NULL);
1273 if (err)
1274 goto err_timeline;
1275
1276 ring = intel_engine_create_ring(engine, SZ_16K);
1277 if (IS_ERR(ring)) {
1278 err = PTR_ERR(ring);
1279 goto err_timeline_unpin;
1280 }
1281
1282 err = intel_ring_pin(ring, NULL);
1283 if (err)
1284 goto err_ring;
1285
1286 GEM_BUG_ON(engine->legacy.ring);
1287 engine->legacy.ring = ring;
1288 engine->legacy.timeline = timeline;
1289
1290 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
1291
1292 if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
1293 err = gen7_ctx_switch_bb_init(engine);
1294 if (err)
1295 goto err_ring_unpin;
1296 }
1297
1298 /* Finally, take ownership and responsibility for cleanup! */
1299 engine->release = ring_release;
1300
1301 return 0;
1302
1303 err_ring_unpin:
1304 intel_ring_unpin(ring);
1305 err_ring:
1306 intel_ring_put(ring);
1307 err_timeline_unpin:
1308 intel_timeline_unpin(timeline);
1309 err_timeline:
1310 intel_timeline_put(timeline);
1311 err:
1312 intel_engine_cleanup_common(engine);
1313 return err;
1314 }
1315
1316 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1317 #include "selftest_ring_submission.c"
1318 #endif
1319