1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dce100/dce_clk_mgr.h"
30 #include "dcn20_clk_mgr.h"
31 #include "reg_helper.h"
32 #include "core_types.h"
33 #include "dm_helpers.h"
34
35 #include "navi10_ip_offset.h"
36 #include "dcn/dcn_2_0_0_offset.h"
37 #include "dcn/dcn_2_0_0_sh_mask.h"
38 #include "clk/clk_11_0_0_offset.h"
39 #include "clk/clk_11_0_0_sh_mask.h"
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
44
45 #define REG(reg) \
46 (clk_mgr->regs->reg)
47
48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
49
50 #define BASE(seg) BASE_INNER(seg)
51
52 #define SR(reg_name)\
53 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
54 mm ## reg_name
55
56 #define CLK_BASE_INNER(seg) \
57 CLK_BASE__INST0_SEG ## seg
58
59
60 static const struct clk_mgr_registers clk_mgr_regs = {
61 CLK_REG_LIST_NV10()
62 };
63
64 static const struct clk_mgr_shift clk_mgr_shift = {
65 CLK_MASK_SH_LIST_NV10(__SHIFT)
66 };
67
68 static const struct clk_mgr_mask clk_mgr_mask = {
69 CLK_MASK_SH_LIST_NV10(_MASK)
70 };
71
dentist_get_did_from_divider(int divider)72 uint32_t dentist_get_did_from_divider(int divider)
73 {
74 uint32_t divider_id;
75
76 /* we want to floor here to get higher clock than required rather than lower */
77 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
78 if (divider < DENTIST_DIVIDER_RANGE_1_START)
79 divider_id = DENTIST_BASE_DID_1;
80 else
81 divider_id = DENTIST_BASE_DID_1
82 + (divider - DENTIST_DIVIDER_RANGE_1_START)
83 / DENTIST_DIVIDER_RANGE_1_STEP;
84 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
85 divider_id = DENTIST_BASE_DID_2
86 + (divider - DENTIST_DIVIDER_RANGE_2_START)
87 / DENTIST_DIVIDER_RANGE_2_STEP;
88 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
89 divider_id = DENTIST_BASE_DID_3
90 + (divider - DENTIST_DIVIDER_RANGE_3_START)
91 / DENTIST_DIVIDER_RANGE_3_STEP;
92 } else {
93 divider_id = DENTIST_BASE_DID_4
94 + (divider - DENTIST_DIVIDER_RANGE_4_START)
95 / DENTIST_DIVIDER_RANGE_4_STEP;
96 if (divider_id > DENTIST_MAX_DID)
97 divider_id = DENTIST_MAX_DID;
98 }
99
100 return divider_id;
101 }
102
dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
104 struct dc_state *context, bool safe_to_lower)
105 {
106 int i;
107
108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
110 int dpp_inst, dppclk_khz, prev_dppclk_khz;
111
112 /* Loop index will match dpp->inst if resource exists,
113 * and we want to avoid dependency on dpp object
114 */
115 dpp_inst = i;
116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
117
118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
119
120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
121 clk_mgr->dccg->funcs->update_dpp_dto(
122 clk_mgr->dccg, dpp_inst, dppclk_khz);
123 }
124 }
125
dcn20_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr)126 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
127 {
128 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
130 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
131 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
132
133 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
134 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
135
136 REG_UPDATE(DENTIST_DISPCLK_CNTL,
137 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
138 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
139 REG_UPDATE(DENTIST_DISPCLK_CNTL,
140 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
141 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
142 }
143
144
dcn2_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)145 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
146 struct dc_state *context,
147 bool safe_to_lower)
148 {
149 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
150 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
151 struct dc *dc = clk_mgr_base->ctx->dc;
152 struct pp_smu_funcs_nv *pp_smu = NULL;
153 int display_count;
154 bool update_dppclk = false;
155 bool update_dispclk = false;
156 bool enter_display_off = false;
157 bool dpp_clock_lowered = false;
158 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
159 bool force_reset = false;
160 bool p_state_change_support;
161 int total_plane_count;
162
163 if (dc->work_arounds.skip_clock_update)
164 return;
165
166 if (clk_mgr_base->clks.dispclk_khz == 0 ||
167 dc->debug.force_clock_mode & 0x1) {
168 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
169 force_reset = true;
170
171 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
172
173 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level.
174 }
175 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
176 if (dc->res_pool->pp_smu)
177 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
178
179 if (display_count == 0)
180 enter_display_off = true;
181
182 if (enter_display_off == safe_to_lower) {
183 if (pp_smu && pp_smu->set_display_count)
184 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
185 }
186
187 if (dc->debug.force_min_dcfclk_mhz > 0)
188 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
189 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
190
191 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
192 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
193 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
194 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
195 }
196
197 if (should_set_clock(safe_to_lower,
198 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
199 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
200 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
201 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
202 }
203
204 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
205 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
206 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
207 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
208 }
209
210 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
211 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
212 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
213 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
214 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
215 if (pp_smu && pp_smu->set_pstate_handshake_support)
216 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
217 }
218
219 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
220 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
221 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
222 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
223 }
224
225 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
226 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
227 dpp_clock_lowered = true;
228 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
229
230 update_dppclk = true;
231 }
232
233 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
234 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
235
236 update_dispclk = true;
237 }
238
239 if (update_dppclk || update_dispclk) {
240 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz;
241
242 if (update_dispclk)
243 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz;
244
245 clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz;
246 if (pp_smu && pp_smu->set_voltage_by_freq)
247 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.disp_dpp_voltage_level_khz / 1000);
248 }
249
250 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
251 if (dpp_clock_lowered) {
252 // if clock is being lowered, increase DTO before lowering refclk
253 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
254 dcn20_update_clocks_update_dentist(clk_mgr);
255 } else {
256 // if clock is being raised, increase refclk before lowering DTO
257 if (update_dppclk || update_dispclk)
258 dcn20_update_clocks_update_dentist(clk_mgr);
259 // always update dtos unless clock is lowered and not safe to lower
260 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
261 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
262 }
263 }
264
265 if (update_dispclk &&
266 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
267 /*update dmcu for wait_loop count*/
268 dmcu->funcs->set_psr_wait_loop(dmcu,
269 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
270 }
271 }
272
dcn2_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)273 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
274 struct dc_state *context,
275 bool safe_to_lower)
276 {
277 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
278
279 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
280 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
281 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
282
283 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
284 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
285 }
286
287 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
288 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
289 }
290
291 if (should_set_clock(safe_to_lower,
292 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
293 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
294 }
295
296 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
297 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
298 }
299
300 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
301 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
302 }
303
304 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
305 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
306 }
307
308 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
309 clk_mgr->clks.fclk_khz = fclk_adj;
310 }
311
312 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
313 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
314 }
315
316 /* Both fclk and ref_dppclk run on the same scemi clock.
317 * So take the higher value since the DPP DTO is typically programmed
318 * such that max dppclk is 1:1 with ref_dppclk.
319 */
320 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
321 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
322 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
323 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
324
325 // Both fclk and ref_dppclk run on the same scemi clock.
326 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
327
328 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
329 }
330
dcn2_init_clocks(struct clk_mgr * clk_mgr)331 void dcn2_init_clocks(struct clk_mgr *clk_mgr)
332 {
333 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
334 // Assumption is that boot state always supports pstate
335 clk_mgr->clks.p_state_change_support = true;
336 clk_mgr->clks.prev_p_state_change_support = true;
337 }
338
dcn2_enable_pme_wa(struct clk_mgr * clk_mgr_base)339 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
340 {
341 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
342 struct pp_smu_funcs_nv *pp_smu = NULL;
343
344 if (clk_mgr->pp_smu) {
345 pp_smu = &clk_mgr->pp_smu->nv_funcs;
346
347 if (pp_smu->set_pme_wa_enable)
348 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
349 }
350 }
351
352
dcn2_read_clocks_from_hw_dentist(struct clk_mgr * clk_mgr_base)353 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
354 {
355 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
356 uint32_t dispclk_wdivider;
357 uint32_t dppclk_wdivider;
358 int disp_divider;
359 int dpp_divider;
360
361 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
362 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
363
364 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
365 dpp_divider = dentist_get_divider_from_did(dispclk_wdivider);
366
367 if (disp_divider && dpp_divider) {
368 /* Calculate the current DFS clock, in kHz.*/
369 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
370 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
371
372 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
373 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
374 }
375
376 }
377
dcn2_get_clock(struct clk_mgr * clk_mgr,struct dc_state * context,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg)378 void dcn2_get_clock(struct clk_mgr *clk_mgr,
379 struct dc_state *context,
380 enum dc_clock_type clock_type,
381 struct dc_clock_config *clock_cfg)
382 {
383
384 if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
385 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
386 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
387 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
388 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
389 }
390 if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
391 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
392 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
393 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
394 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
395 }
396 }
397
dcn2_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)398 static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
399 struct dc_clocks *b)
400 {
401 if (a->dispclk_khz != b->dispclk_khz)
402 return false;
403 else if (a->dppclk_khz != b->dppclk_khz)
404 return false;
405 else if (a->disp_dpp_voltage_level_khz != b->disp_dpp_voltage_level_khz)
406 return false;
407 else if (a->dcfclk_khz != b->dcfclk_khz)
408 return false;
409 else if (a->socclk_khz != b->socclk_khz)
410 return false;
411 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
412 return false;
413 else if (a->dramclk_khz != b->dramclk_khz)
414 return false;
415 else if (a->p_state_change_support != b->p_state_change_support)
416 return false;
417
418 return true;
419 }
420
421 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
dcn2_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link)422 static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
423 {
424 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
425 unsigned int i, max_phyclk_req = 0;
426 struct pp_smu_funcs_nv *pp_smu = NULL;
427
428 if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)
429 return;
430
431 pp_smu = &clk_mgr->pp_smu->nv_funcs;
432
433 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
434
435 for (i = 0; i < MAX_PIPES * 2; i++) {
436 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
437 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
438 }
439
440 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
441 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
442 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
443 }
444 }
445
446 static struct clk_mgr_funcs dcn2_funcs = {
447 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
448 .update_clocks = dcn2_update_clocks,
449 .init_clocks = dcn2_init_clocks,
450 .enable_pme_wa = dcn2_enable_pme_wa,
451 .get_clock = dcn2_get_clock,
452 .are_clock_states_equal = dcn2_are_clock_states_equal,
453 .notify_link_rate_change = dcn2_notify_link_rate_change,
454 };
455
456
dcn20_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)457 void dcn20_clk_mgr_construct(
458 struct dc_context *ctx,
459 struct clk_mgr_internal *clk_mgr,
460 struct pp_smu_funcs *pp_smu,
461 struct dccg *dccg)
462 {
463 clk_mgr->base.ctx = ctx;
464 clk_mgr->pp_smu = pp_smu;
465 clk_mgr->base.funcs = &dcn2_funcs;
466 clk_mgr->regs = &clk_mgr_regs;
467 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
468 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
469
470 clk_mgr->dccg = dccg;
471 clk_mgr->dfs_bypass_disp_clk = 0;
472
473 clk_mgr->dprefclk_ss_percentage = 0;
474 clk_mgr->dprefclk_ss_divider = 1000;
475 clk_mgr->ss_on_dprefclk = false;
476
477 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
478
479 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
480 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
481 clk_mgr->base.dentist_vco_freq_khz = 3850000;
482
483 } else {
484 /* DFS Slice 2 should be used for DPREFCLK */
485 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
486 /* Convert DPREFCLK DFS Slice DID to actual divider*/
487 int target_div = dentist_get_divider_from_did(dprefclk_did);
488
489 /* get FbMult value */
490 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
491 struct fixed31_32 pll_req;
492
493 /* set up a fixed-point number
494 * this works because the int part is on the right edge of the register
495 * and the frac part is on the left edge
496 */
497
498 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
499 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
500
501 /* multiply by REFCLK period */
502 pll_req = dc_fixpt_mul_int(pll_req, 100000);
503
504 /* integer part is now VCO frequency in kHz */
505 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
506
507 /* in case we don't get a value from the register, use default */
508 if (clk_mgr->base.dentist_vco_freq_khz == 0)
509 clk_mgr->base.dentist_vco_freq_khz = 3850000;
510
511 /* Calculate the DPREFCLK in kHz.*/
512 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
513 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
514 }
515 //Integrated_info table does not exist on dGPU projects so should not be referenced
516 //anywhere in code for dGPUs.
517 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
518 clk_mgr->dfs_bypass_enabled = false;
519
520 dce_clock_read_ss_info(clk_mgr);
521 }
522
523