1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "atom.h"
29 
30 #include "include/bios_parser_types.h"
31 
32 #include "command_table_helper.h"
33 
dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper ** h,enum dce_version dce)34 bool dal_bios_parser_init_cmd_tbl_helper(
35 	const struct command_table_helper **h,
36 	enum dce_version dce)
37 {
38 	switch (dce) {
39 #if defined(CONFIG_DRM_AMD_DC_SI)
40 	case DCE_VERSION_6_0:
41 	case DCE_VERSION_6_1:
42 	case DCE_VERSION_6_4:
43 		*h = dal_cmd_tbl_helper_dce60_get_table();
44 		return true;
45 #endif
46 
47 	case DCE_VERSION_8_0:
48 	case DCE_VERSION_8_1:
49 	case DCE_VERSION_8_3:
50 		*h = dal_cmd_tbl_helper_dce80_get_table();
51 		return true;
52 
53 	case DCE_VERSION_10_0:
54 		*h = dal_cmd_tbl_helper_dce110_get_table();
55 		return true;
56 
57 	case DCE_VERSION_11_0:
58 		*h = dal_cmd_tbl_helper_dce110_get_table();
59 		return true;
60 
61 	case DCE_VERSION_11_2:
62 	case DCE_VERSION_11_22:
63 		*h = dal_cmd_tbl_helper_dce112_get_table();
64 		return true;
65 
66 	default:
67 		/* Unsupported DCE */
68 		BREAK_TO_DEBUGGER();
69 		return false;
70 	}
71 }
72 
73 /* real implementations */
74 
dal_cmd_table_helper_controller_id_to_atom(enum controller_id id,uint8_t * atom_id)75 bool dal_cmd_table_helper_controller_id_to_atom(
76 	enum controller_id id,
77 	uint8_t *atom_id)
78 {
79 	if (atom_id == NULL) {
80 		BREAK_TO_DEBUGGER();
81 		return false;
82 	}
83 
84 	switch (id) {
85 	case CONTROLLER_ID_D0:
86 		*atom_id = ATOM_CRTC1;
87 		return true;
88 	case CONTROLLER_ID_D1:
89 		*atom_id = ATOM_CRTC2;
90 		return true;
91 	case CONTROLLER_ID_D2:
92 		*atom_id = ATOM_CRTC3;
93 		return true;
94 	case CONTROLLER_ID_D3:
95 		*atom_id = ATOM_CRTC4;
96 		return true;
97 	case CONTROLLER_ID_D4:
98 		*atom_id = ATOM_CRTC5;
99 		return true;
100 	case CONTROLLER_ID_D5:
101 		*atom_id = ATOM_CRTC6;
102 		return true;
103 	case CONTROLLER_ID_UNDERLAY0:
104 		*atom_id = ATOM_UNDERLAY_PIPE0;
105 		return true;
106 	case CONTROLLER_ID_UNDEFINED:
107 		*atom_id = ATOM_CRTC_INVALID;
108 		return true;
109 	default:
110 		/* Wrong controller id */
111 		BREAK_TO_DEBUGGER();
112 		return false;
113 	}
114 }
115 
116 /**
117 * translate_transmitter_bp_to_atom
118 *
119 * @brief
120 *  Translate the Transmitter to the corresponding ATOM BIOS value
121 *
122 * @param
123 *   input transmitter
124 *   output digitalTransmitter
125 *    // =00: Digital Transmitter1 ( UNIPHY linkAB )
126 *    // =01: Digital Transmitter2 ( UNIPHY linkCD )
127 *    // =02: Digital Transmitter3 ( UNIPHY linkEF )
128 */
dal_cmd_table_helper_transmitter_bp_to_atom(enum transmitter t)129 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
130 	enum transmitter t)
131 {
132 	switch (t) {
133 	case TRANSMITTER_UNIPHY_A:
134 	case TRANSMITTER_UNIPHY_B:
135 	case TRANSMITTER_TRAVIS_LCD:
136 		return 0;
137 	case TRANSMITTER_UNIPHY_C:
138 	case TRANSMITTER_UNIPHY_D:
139 		return 1;
140 	case TRANSMITTER_UNIPHY_E:
141 	case TRANSMITTER_UNIPHY_F:
142 		return 2;
143 	default:
144 		/* Invalid Transmitter Type! */
145 		BREAK_TO_DEBUGGER();
146 		return 0;
147 	}
148 }
149 
dal_cmd_table_helper_encoder_mode_bp_to_atom(enum signal_type s,bool enable_dp_audio)150 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
151 	enum signal_type s,
152 	bool enable_dp_audio)
153 {
154 	switch (s) {
155 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
156 	case SIGNAL_TYPE_DVI_DUAL_LINK:
157 		return ATOM_ENCODER_MODE_DVI;
158 	case SIGNAL_TYPE_HDMI_TYPE_A:
159 		return ATOM_ENCODER_MODE_HDMI;
160 	case SIGNAL_TYPE_LVDS:
161 		return ATOM_ENCODER_MODE_LVDS;
162 	case SIGNAL_TYPE_EDP:
163 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
164 	case SIGNAL_TYPE_DISPLAY_PORT:
165 	case SIGNAL_TYPE_VIRTUAL:
166 		if (enable_dp_audio)
167 			return ATOM_ENCODER_MODE_DP_AUDIO;
168 		else
169 			return ATOM_ENCODER_MODE_DP;
170 	case SIGNAL_TYPE_RGB:
171 		return ATOM_ENCODER_MODE_CRT;
172 	default:
173 		return ATOM_ENCODER_MODE_CRT;
174 	}
175 }
176 
dal_cmd_table_helper_assign_control_parameter(const struct command_table_helper * h,struct bp_encoder_control * control,DIG_ENCODER_CONTROL_PARAMETERS_V2 * ctrl_param)177 void dal_cmd_table_helper_assign_control_parameter(
178 	const struct command_table_helper *h,
179 	struct bp_encoder_control *control,
180 	DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
181 {
182 	/* there are three transmitter blocks, each one has two links 4-lanes
183 	 * each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
184 	 * each transmitter block B, D and F as link 1, third transmitter block
185 	 * has non splitable links (UniphyE and UniphyF can not be configured
186 	 * separately to drive two different streams)
187 	 */
188 	if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
189 		(control->transmitter == TRANSMITTER_UNIPHY_D) ||
190 		(control->transmitter == TRANSMITTER_UNIPHY_F)) {
191 		/* Bit2: Link Select
192 		 * =0: PHY linkA/C/E
193 		 * =1: PHY linkB/D/F
194 		 */
195 		ctrl_param->acConfig.ucLinkSel = 1;
196 	}
197 
198 	/* Bit[4:3]: Transmitter Selection
199 	 * =00: Digital Transmitter1 ( UNIPHY linkAB )
200 	 * =01: Digital Transmitter2 ( UNIPHY linkCD )
201 	 * =02: Digital Transmitter3 ( UNIPHY linkEF )
202 	 * =03: Reserved
203 	 */
204 	ctrl_param->acConfig.ucTransmitterSel =
205 		(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
206 
207 	/* We need to convert from KHz units into 10KHz units */
208 	ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
209 	ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
210 	ctrl_param->ucEncoderMode =
211 		(uint8_t)(h->encoder_mode_bp_to_atom(
212 			control->signal, control->enable_dp_audio));
213 	ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
214 }
215 
dal_cmd_table_helper_clock_source_id_to_ref_clk_src(enum clock_source_id id,uint32_t * ref_clk_src_id)216 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
217 	enum clock_source_id id,
218 	uint32_t *ref_clk_src_id)
219 {
220 	if (ref_clk_src_id == NULL) {
221 		BREAK_TO_DEBUGGER();
222 		return false;
223 	}
224 
225 	switch (id) {
226 	case CLOCK_SOURCE_ID_PLL1:
227 		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
228 		return true;
229 	case CLOCK_SOURCE_ID_PLL2:
230 		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
231 		return true;
232 	case CLOCK_SOURCE_ID_DCPLL:
233 		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
234 		return true;
235 	case CLOCK_SOURCE_ID_EXTERNAL:
236 		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
237 		return true;
238 	case CLOCK_SOURCE_ID_UNDEFINED:
239 		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
240 		return true;
241 	default:
242 		/* Unsupported clock source id */
243 		BREAK_TO_DEBUGGER();
244 		return false;
245 	}
246 }
247 
dal_cmd_table_helper_encoder_id_to_atom(enum encoder_id id)248 uint8_t dal_cmd_table_helper_encoder_id_to_atom(
249 	enum encoder_id id)
250 {
251 	switch (id) {
252 	case ENCODER_ID_INTERNAL_LVDS:
253 		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
254 	case ENCODER_ID_INTERNAL_TMDS1:
255 		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
256 	case ENCODER_ID_INTERNAL_TMDS2:
257 		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
258 	case ENCODER_ID_INTERNAL_DAC1:
259 		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
260 	case ENCODER_ID_INTERNAL_DAC2:
261 		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
262 	case ENCODER_ID_INTERNAL_LVTM1:
263 		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
264 	case ENCODER_ID_INTERNAL_HDMI:
265 		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
266 	case ENCODER_ID_EXTERNAL_TRAVIS:
267 		return ENCODER_OBJECT_ID_TRAVIS;
268 	case ENCODER_ID_EXTERNAL_NUTMEG:
269 		return ENCODER_OBJECT_ID_NUTMEG;
270 	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
271 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
272 	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
273 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
274 	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
275 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
276 	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
277 		return ENCODER_OBJECT_ID_MVPU_FPGA;
278 	case ENCODER_ID_INTERNAL_DDI:
279 		return ENCODER_OBJECT_ID_INTERNAL_DDI;
280 	case ENCODER_ID_INTERNAL_UNIPHY:
281 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
282 	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
283 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
284 	case ENCODER_ID_INTERNAL_UNIPHY1:
285 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
286 	case ENCODER_ID_INTERNAL_UNIPHY2:
287 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
288 	case ENCODER_ID_INTERNAL_UNIPHY3:
289 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
290 	case ENCODER_ID_INTERNAL_WIRELESS:
291 		return ENCODER_OBJECT_ID_INTERNAL_VCE;
292 	case ENCODER_ID_UNKNOWN:
293 		return ENCODER_OBJECT_ID_NONE;
294 	default:
295 		/* Invalid encoder id */
296 		BREAK_TO_DEBUGGER();
297 		return ENCODER_OBJECT_ID_NONE;
298 	}
299 }
300