1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "hdp/hdp_5_0_0_offset.h"
36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
38
39 #include "soc15_common.h"
40 #include "soc15.h"
41 #include "navi10_sdma_pkt_open.h"
42 #include "nbio_v2_3.h"
43 #include "sdma_common.h"
44 #include "sdma_v5_0.h"
45
46 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
47 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
48
49 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
51
52 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
54
55 #define SDMA1_REG_OFFSET 0x600
56 #define SDMA0_HYP_DEC_REG_START 0x5880
57 #define SDMA0_HYP_DEC_REG_END 0x5893
58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
59
60 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
61 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
62 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
63 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
64
65 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
90 };
91
92 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 };
114
115 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
118 };
119
120 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
123 };
124
125 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 };
129
sdma_v5_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)130 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
131 {
132 u32 base;
133
134 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
135 internal_offset <= SDMA0_HYP_DEC_REG_END) {
136 base = adev->reg_offset[GC_HWIP][0][1];
137 if (instance == 1)
138 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
139 } else {
140 base = adev->reg_offset[GC_HWIP][0][0];
141 if (instance == 1)
142 internal_offset += SDMA1_REG_OFFSET;
143 }
144
145 return base + internal_offset;
146 }
147
sdma_v5_0_init_golden_registers(struct amdgpu_device * adev)148 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
149 {
150 switch (adev->asic_type) {
151 case CHIP_NAVI10:
152 soc15_program_register_sequence(adev,
153 golden_settings_sdma_5,
154 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
155 soc15_program_register_sequence(adev,
156 golden_settings_sdma_nv10,
157 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
158 break;
159 case CHIP_NAVI14:
160 soc15_program_register_sequence(adev,
161 golden_settings_sdma_5,
162 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
163 soc15_program_register_sequence(adev,
164 golden_settings_sdma_nv14,
165 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
166 break;
167 case CHIP_NAVI12:
168 if (amdgpu_sriov_vf(adev))
169 soc15_program_register_sequence(adev,
170 golden_settings_sdma_5_sriov,
171 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
172 else
173 soc15_program_register_sequence(adev,
174 golden_settings_sdma_5,
175 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
176 soc15_program_register_sequence(adev,
177 golden_settings_sdma_nv12,
178 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
179 break;
180 default:
181 break;
182 }
183 }
184
185 /**
186 * sdma_v5_0_init_microcode - load ucode images from disk
187 *
188 * @adev: amdgpu_device pointer
189 *
190 * Use the firmware interface to load the ucode images into
191 * the driver (not loaded into hw).
192 * Returns 0 on success, error on failure.
193 */
194
195 // emulation only, won't work on real chip
196 // navi10 real chip need to use PSP to load firmware
sdma_v5_0_init_microcode(struct amdgpu_device * adev)197 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
198 {
199 const char *chip_name;
200 char fw_name[30];
201 int err = 0, i;
202 struct amdgpu_firmware_info *info = NULL;
203 const struct common_firmware_header *header = NULL;
204 const struct sdma_firmware_header_v1_0 *hdr;
205
206 if (amdgpu_sriov_vf(adev))
207 return 0;
208
209 DRM_DEBUG("\n");
210
211 switch (adev->asic_type) {
212 case CHIP_NAVI10:
213 chip_name = "navi10";
214 break;
215 case CHIP_NAVI14:
216 chip_name = "navi14";
217 break;
218 case CHIP_NAVI12:
219 chip_name = "navi12";
220 break;
221 default:
222 BUG();
223 }
224
225 for (i = 0; i < adev->sdma.num_instances; i++) {
226 if (i == 0)
227 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
228 else
229 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
230 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
231 if (err)
232 goto out;
233 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
234 if (err)
235 goto out;
236 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
237 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
238 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
239 if (adev->sdma.instance[i].feature_version >= 20)
240 adev->sdma.instance[i].burst_nop = true;
241 DRM_DEBUG("psp_load == '%s'\n",
242 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
243
244 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
245 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
246 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
247 info->fw = adev->sdma.instance[i].fw;
248 header = (const struct common_firmware_header *)info->fw->data;
249 adev->firmware.fw_size +=
250 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
251 }
252 }
253 out:
254 if (err) {
255 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
256 for (i = 0; i < adev->sdma.num_instances; i++) {
257 release_firmware(adev->sdma.instance[i].fw);
258 adev->sdma.instance[i].fw = NULL;
259 }
260 }
261 return err;
262 }
263
sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring * ring)264 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
265 {
266 unsigned ret;
267
268 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
269 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
270 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
271 amdgpu_ring_write(ring, 1);
272 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
273 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
274
275 return ret;
276 }
277
sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)278 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
279 unsigned offset)
280 {
281 unsigned cur;
282
283 BUG_ON(offset > ring->buf_mask);
284 BUG_ON(ring->ring[offset] != 0x55aa55aa);
285
286 cur = (ring->wptr - 1) & ring->buf_mask;
287 if (cur > offset)
288 ring->ring[offset] = cur - offset;
289 else
290 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
291 }
292
293 /**
294 * sdma_v5_0_ring_get_rptr - get the current read pointer
295 *
296 * @ring: amdgpu ring pointer
297 *
298 * Get the current rptr from the hardware (NAVI10+).
299 */
sdma_v5_0_ring_get_rptr(struct amdgpu_ring * ring)300 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
301 {
302 u64 *rptr;
303
304 /* XXX check if swapping is necessary on BE */
305 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
306
307 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
308 return ((*rptr) >> 2);
309 }
310
311 /**
312 * sdma_v5_0_ring_get_wptr - get the current write pointer
313 *
314 * @ring: amdgpu ring pointer
315 *
316 * Get the current wptr from the hardware (NAVI10+).
317 */
sdma_v5_0_ring_get_wptr(struct amdgpu_ring * ring)318 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
319 {
320 struct amdgpu_device *adev = ring->adev;
321 u64 wptr;
322
323 if (ring->use_doorbell) {
324 /* XXX check if swapping is necessary on BE */
325 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
326 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
327 } else {
328 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
329 wptr = wptr << 32;
330 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
331 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
332 }
333
334 return wptr >> 2;
335 }
336
337 /**
338 * sdma_v5_0_ring_set_wptr - commit the write pointer
339 *
340 * @ring: amdgpu ring pointer
341 *
342 * Write the wptr back to the hardware (NAVI10+).
343 */
sdma_v5_0_ring_set_wptr(struct amdgpu_ring * ring)344 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
345 {
346 struct amdgpu_device *adev = ring->adev;
347
348 DRM_DEBUG("Setting write pointer\n");
349 if (ring->use_doorbell) {
350 DRM_DEBUG("Using doorbell -- "
351 "wptr_offs == 0x%08x "
352 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
353 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
354 ring->wptr_offs,
355 lower_32_bits(ring->wptr << 2),
356 upper_32_bits(ring->wptr << 2));
357 /* XXX check if swapping is necessary on BE */
358 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
359 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
360 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
361 ring->doorbell_index, ring->wptr << 2);
362 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
363 } else {
364 DRM_DEBUG("Not using doorbell -- "
365 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
366 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
367 ring->me,
368 lower_32_bits(ring->wptr << 2),
369 ring->me,
370 upper_32_bits(ring->wptr << 2));
371 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
372 lower_32_bits(ring->wptr << 2));
373 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
374 upper_32_bits(ring->wptr << 2));
375 }
376 }
377
sdma_v5_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)378 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
379 {
380 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
381 int i;
382
383 for (i = 0; i < count; i++)
384 if (sdma && sdma->burst_nop && (i == 0))
385 amdgpu_ring_write(ring, ring->funcs->nop |
386 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
387 else
388 amdgpu_ring_write(ring, ring->funcs->nop);
389 }
390
391 /**
392 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
393 *
394 * @ring: amdgpu ring pointer
395 * @ib: IB object to schedule
396 *
397 * Schedule an IB in the DMA ring (NAVI10).
398 */
sdma_v5_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)399 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
400 struct amdgpu_job *job,
401 struct amdgpu_ib *ib,
402 uint32_t flags)
403 {
404 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
405 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
406
407 /* Invalidate L2, because if we don't do it, we might get stale cache
408 * lines from previous IBs.
409 */
410 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
411 amdgpu_ring_write(ring, 0);
412 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
413 SDMA_GCR_GL2_WB |
414 SDMA_GCR_GLM_INV |
415 SDMA_GCR_GLM_WB) << 16);
416 amdgpu_ring_write(ring, 0xffffff80);
417 amdgpu_ring_write(ring, 0xffff);
418
419 /* An IB packet must end on a 8 DW boundary--the next dword
420 * must be on a 8-dword boundary. Our IB packet below is 6
421 * dwords long, thus add x number of NOPs, such that, in
422 * modular arithmetic,
423 * wptr + 6 + x = 8k, k >= 0, which in C is,
424 * (wptr + 6 + x) % 8 = 0.
425 * The expression below, is a solution of x.
426 */
427 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
428
429 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
430 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
431 /* base must be 32 byte aligned */
432 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
433 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
434 amdgpu_ring_write(ring, ib->length_dw);
435 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
436 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
437 }
438
439 /**
440 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
441 *
442 * @ring: amdgpu ring pointer
443 *
444 * Emit an hdp flush packet on the requested DMA ring.
445 */
sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)446 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
447 {
448 struct amdgpu_device *adev = ring->adev;
449 u32 ref_and_mask = 0;
450 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
451
452 if (ring->me == 0)
453 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
454 else
455 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
456
457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
458 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
459 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
460 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
461 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
462 amdgpu_ring_write(ring, ref_and_mask); /* reference */
463 amdgpu_ring_write(ring, ref_and_mask); /* mask */
464 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
466 }
467
468 /**
469 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
470 *
471 * @ring: amdgpu ring pointer
472 * @fence: amdgpu fence object
473 *
474 * Add a DMA fence packet to the ring to write
475 * the fence seq number and DMA trap packet to generate
476 * an interrupt if needed (NAVI10).
477 */
sdma_v5_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)478 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
479 unsigned flags)
480 {
481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
482 /* write the fence */
483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
484 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
485 /* zero in first two bits */
486 BUG_ON(addr & 0x3);
487 amdgpu_ring_write(ring, lower_32_bits(addr));
488 amdgpu_ring_write(ring, upper_32_bits(addr));
489 amdgpu_ring_write(ring, lower_32_bits(seq));
490
491 /* optionally write high bits as well */
492 if (write64bit) {
493 addr += 4;
494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
495 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
496 /* zero in first two bits */
497 BUG_ON(addr & 0x3);
498 amdgpu_ring_write(ring, lower_32_bits(addr));
499 amdgpu_ring_write(ring, upper_32_bits(addr));
500 amdgpu_ring_write(ring, upper_32_bits(seq));
501 }
502
503 if (flags & AMDGPU_FENCE_FLAG_INT) {
504 /* generate an interrupt */
505 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
506 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
507 }
508 }
509
510
511 /**
512 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
513 *
514 * @adev: amdgpu_device pointer
515 *
516 * Stop the gfx async dma ring buffers (NAVI10).
517 */
sdma_v5_0_gfx_stop(struct amdgpu_device * adev)518 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
519 {
520 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
521 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
522 u32 rb_cntl, ib_cntl;
523 int i;
524
525 if ((adev->mman.buffer_funcs_ring == sdma0) ||
526 (adev->mman.buffer_funcs_ring == sdma1))
527 amdgpu_ttm_set_buffer_funcs_status(adev, false);
528
529 for (i = 0; i < adev->sdma.num_instances; i++) {
530 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
531 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
532 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
533 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
534 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
535 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
536 }
537 }
538
539 /**
540 * sdma_v5_0_rlc_stop - stop the compute async dma engines
541 *
542 * @adev: amdgpu_device pointer
543 *
544 * Stop the compute async dma queues (NAVI10).
545 */
sdma_v5_0_rlc_stop(struct amdgpu_device * adev)546 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
547 {
548 /* XXX todo */
549 }
550
551 /**
552 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
553 *
554 * @adev: amdgpu_device pointer
555 * @enable: enable/disable the DMA MEs context switch.
556 *
557 * Halt or unhalt the async dma engines context switch (NAVI10).
558 */
sdma_v5_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)559 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
560 {
561 u32 f32_cntl = 0, phase_quantum = 0;
562 int i;
563
564 if (amdgpu_sdma_phase_quantum) {
565 unsigned value = amdgpu_sdma_phase_quantum;
566 unsigned unit = 0;
567
568 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
569 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
570 value = (value + 1) >> 1;
571 unit++;
572 }
573 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
574 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
575 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
576 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
577 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
578 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
579 WARN_ONCE(1,
580 "clamping sdma_phase_quantum to %uK clock cycles\n",
581 value << unit);
582 }
583 phase_quantum =
584 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
585 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
586 }
587
588 for (i = 0; i < adev->sdma.num_instances; i++) {
589 if (!amdgpu_sriov_vf(adev)) {
590 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
592 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
593 }
594
595 if (enable && amdgpu_sdma_phase_quantum) {
596 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
597 phase_quantum);
598 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
599 phase_quantum);
600 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
601 phase_quantum);
602 }
603 if (!amdgpu_sriov_vf(adev))
604 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
605 }
606
607 }
608
609 /**
610 * sdma_v5_0_enable - stop the async dma engines
611 *
612 * @adev: amdgpu_device pointer
613 * @enable: enable/disable the DMA MEs.
614 *
615 * Halt or unhalt the async dma engines (NAVI10).
616 */
sdma_v5_0_enable(struct amdgpu_device * adev,bool enable)617 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
618 {
619 u32 f32_cntl;
620 int i;
621
622 if (!enable) {
623 sdma_v5_0_gfx_stop(adev);
624 sdma_v5_0_rlc_stop(adev);
625 }
626
627 if (amdgpu_sriov_vf(adev))
628 return;
629
630 for (i = 0; i < adev->sdma.num_instances; i++) {
631 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
632 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
634 }
635 }
636
637 /**
638 * sdma_v5_0_gfx_resume - setup and start the async dma engines
639 *
640 * @adev: amdgpu_device pointer
641 *
642 * Set up the gfx DMA ring buffers and enable them (NAVI10).
643 * Returns 0 for success, error for failure.
644 */
sdma_v5_0_gfx_resume(struct amdgpu_device * adev)645 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
646 {
647 struct amdgpu_ring *ring;
648 u32 rb_cntl, ib_cntl;
649 u32 rb_bufsz;
650 u32 wb_offset;
651 u32 doorbell;
652 u32 doorbell_offset;
653 u32 temp;
654 u32 wptr_poll_cntl;
655 u64 wptr_gpu_addr;
656 int i, r;
657
658 for (i = 0; i < adev->sdma.num_instances; i++) {
659 ring = &adev->sdma.instance[i].ring;
660 wb_offset = (ring->rptr_offs * 4);
661
662 if (!amdgpu_sriov_vf(adev))
663 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
664
665 /* Set ring buffer size in dwords */
666 rb_bufsz = order_base_2(ring->ring_size / 4);
667 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
669 #ifdef __BIG_ENDIAN
670 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
672 RPTR_WRITEBACK_SWAP_ENABLE, 1);
673 #endif
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
675
676 /* Initialize the ring buffer's read and write pointers */
677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
678 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
680 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
681
682 /* setup the wptr shadow polling */
683 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
685 lower_32_bits(wptr_gpu_addr));
686 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
687 upper_32_bits(wptr_gpu_addr));
688 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
689 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
690 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
691 SDMA0_GFX_RB_WPTR_POLL_CNTL,
692 F32_POLL_ENABLE, 1);
693 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
694 wptr_poll_cntl);
695
696 /* set the wb address whether it's enabled or not */
697 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
698 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
699 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
700 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
701
702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
703
704 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
705 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
706
707 ring->wptr = 0;
708
709 /* before programing wptr to a less value, need set minor_ptr_update first */
710 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
711
712 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
713 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
714 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
715 }
716
717 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
718 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
719
720 if (ring->use_doorbell) {
721 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
722 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
723 OFFSET, ring->doorbell_index);
724 } else {
725 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
726 }
727 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
728 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
729
730 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
731 ring->doorbell_index, 20);
732
733 if (amdgpu_sriov_vf(adev))
734 sdma_v5_0_ring_set_wptr(ring);
735
736 /* set minor_ptr_update to 0 after wptr programed */
737 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
738
739 if (!amdgpu_sriov_vf(adev)) {
740 /* set utc l1 enable flag always to 1 */
741 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
742 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
743
744 /* enable MCBP */
745 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
746 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
747
748 /* Set up RESP_MODE to non-copy addresses */
749 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
750 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
751 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
752 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
753
754 /* program default cache read and write policy */
755 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
756 /* clean read policy and write policy bits */
757 temp &= 0xFF0FFF;
758 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
759 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
760 }
761
762 if (!amdgpu_sriov_vf(adev)) {
763 /* unhalt engine */
764 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
765 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
766 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
767 }
768
769 /* enable DMA RB */
770 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
771 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
772
773 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
774 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
775 #ifdef __BIG_ENDIAN
776 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
777 #endif
778 /* enable DMA IBs */
779 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
780
781 ring->sched.ready = true;
782
783 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
784 sdma_v5_0_ctx_switch_enable(adev, true);
785 sdma_v5_0_enable(adev, true);
786 }
787
788 r = amdgpu_ring_test_helper(ring);
789 if (r)
790 return r;
791
792 if (adev->mman.buffer_funcs_ring == ring)
793 amdgpu_ttm_set_buffer_funcs_status(adev, true);
794 }
795
796 return 0;
797 }
798
799 /**
800 * sdma_v5_0_rlc_resume - setup and start the async dma engines
801 *
802 * @adev: amdgpu_device pointer
803 *
804 * Set up the compute DMA queues and enable them (NAVI10).
805 * Returns 0 for success, error for failure.
806 */
sdma_v5_0_rlc_resume(struct amdgpu_device * adev)807 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
808 {
809 return 0;
810 }
811
812 /**
813 * sdma_v5_0_load_microcode - load the sDMA ME ucode
814 *
815 * @adev: amdgpu_device pointer
816 *
817 * Loads the sDMA0/1 ucode.
818 * Returns 0 for success, -EINVAL if the ucode is not available.
819 */
sdma_v5_0_load_microcode(struct amdgpu_device * adev)820 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
821 {
822 const struct sdma_firmware_header_v1_0 *hdr;
823 const __le32 *fw_data;
824 u32 fw_size;
825 int i, j;
826
827 /* halt the MEs */
828 sdma_v5_0_enable(adev, false);
829
830 for (i = 0; i < adev->sdma.num_instances; i++) {
831 if (!adev->sdma.instance[i].fw)
832 return -EINVAL;
833
834 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
835 amdgpu_ucode_print_sdma_hdr(&hdr->header);
836 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
837
838 fw_data = (const __le32 *)
839 (adev->sdma.instance[i].fw->data +
840 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
841
842 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
843
844 for (j = 0; j < fw_size; j++) {
845 if (amdgpu_emu_mode == 1 && j % 500 == 0)
846 msleep(1);
847 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
848 }
849
850 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
851 }
852
853 return 0;
854 }
855
856 /**
857 * sdma_v5_0_start - setup and start the async dma engines
858 *
859 * @adev: amdgpu_device pointer
860 *
861 * Set up the DMA engines and enable them (NAVI10).
862 * Returns 0 for success, error for failure.
863 */
sdma_v5_0_start(struct amdgpu_device * adev)864 static int sdma_v5_0_start(struct amdgpu_device *adev)
865 {
866 int r = 0;
867
868 if (amdgpu_sriov_vf(adev)) {
869 sdma_v5_0_ctx_switch_enable(adev, false);
870 sdma_v5_0_enable(adev, false);
871
872 /* set RB registers */
873 r = sdma_v5_0_gfx_resume(adev);
874 return r;
875 }
876
877 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
878 r = sdma_v5_0_load_microcode(adev);
879 if (r)
880 return r;
881 }
882
883 /* unhalt the MEs */
884 sdma_v5_0_enable(adev, true);
885 /* enable sdma ring preemption */
886 sdma_v5_0_ctx_switch_enable(adev, true);
887
888 /* start the gfx rings and rlc compute queues */
889 r = sdma_v5_0_gfx_resume(adev);
890 if (r)
891 return r;
892 r = sdma_v5_0_rlc_resume(adev);
893
894 return r;
895 }
896
897 /**
898 * sdma_v5_0_ring_test_ring - simple async dma engine test
899 *
900 * @ring: amdgpu_ring structure holding ring information
901 *
902 * Test the DMA engine by writing using it to write an
903 * value to memory. (NAVI10).
904 * Returns 0 for success, error for failure.
905 */
sdma_v5_0_ring_test_ring(struct amdgpu_ring * ring)906 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
907 {
908 struct amdgpu_device *adev = ring->adev;
909 unsigned i;
910 unsigned index;
911 int r;
912 u32 tmp;
913 u64 gpu_addr;
914
915 r = amdgpu_device_wb_get(adev, &index);
916 if (r) {
917 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
918 return r;
919 }
920
921 gpu_addr = adev->wb.gpu_addr + (index * 4);
922 tmp = 0xCAFEDEAD;
923 adev->wb.wb[index] = cpu_to_le32(tmp);
924
925 r = amdgpu_ring_alloc(ring, 5);
926 if (r) {
927 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
928 amdgpu_device_wb_free(adev, index);
929 return r;
930 }
931
932 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
933 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
934 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
935 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
936 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
937 amdgpu_ring_write(ring, 0xDEADBEEF);
938 amdgpu_ring_commit(ring);
939
940 for (i = 0; i < adev->usec_timeout; i++) {
941 tmp = le32_to_cpu(adev->wb.wb[index]);
942 if (tmp == 0xDEADBEEF)
943 break;
944 if (amdgpu_emu_mode == 1)
945 msleep(1);
946 else
947 udelay(1);
948 }
949
950 if (i >= adev->usec_timeout)
951 r = -ETIMEDOUT;
952
953 amdgpu_device_wb_free(adev, index);
954
955 return r;
956 }
957
958 /**
959 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
960 *
961 * @ring: amdgpu_ring structure holding ring information
962 *
963 * Test a simple IB in the DMA ring (NAVI10).
964 * Returns 0 on success, error on failure.
965 */
sdma_v5_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)966 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
967 {
968 struct amdgpu_device *adev = ring->adev;
969 struct amdgpu_ib ib;
970 struct dma_fence *f = NULL;
971 unsigned index;
972 long r;
973 u32 tmp = 0;
974 u64 gpu_addr;
975
976 r = amdgpu_device_wb_get(adev, &index);
977 if (r) {
978 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
979 return r;
980 }
981
982 gpu_addr = adev->wb.gpu_addr + (index * 4);
983 tmp = 0xCAFEDEAD;
984 adev->wb.wb[index] = cpu_to_le32(tmp);
985 memset(&ib, 0, sizeof(ib));
986 r = amdgpu_ib_get(adev, NULL, 256,
987 AMDGPU_IB_POOL_DIRECT, &ib);
988 if (r) {
989 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
990 goto err0;
991 }
992
993 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
994 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
995 ib.ptr[1] = lower_32_bits(gpu_addr);
996 ib.ptr[2] = upper_32_bits(gpu_addr);
997 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
998 ib.ptr[4] = 0xDEADBEEF;
999 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1000 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1001 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1002 ib.length_dw = 8;
1003
1004 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1005 if (r)
1006 goto err1;
1007
1008 r = dma_fence_wait_timeout(f, false, timeout);
1009 if (r == 0) {
1010 DRM_ERROR("amdgpu: IB test timed out\n");
1011 r = -ETIMEDOUT;
1012 goto err1;
1013 } else if (r < 0) {
1014 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1015 goto err1;
1016 }
1017 tmp = le32_to_cpu(adev->wb.wb[index]);
1018 if (tmp == 0xDEADBEEF)
1019 r = 0;
1020 else
1021 r = -EINVAL;
1022
1023 err1:
1024 amdgpu_ib_free(adev, &ib, NULL);
1025 dma_fence_put(f);
1026 err0:
1027 amdgpu_device_wb_free(adev, index);
1028 return r;
1029 }
1030
1031
1032 /**
1033 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1034 *
1035 * @ib: indirect buffer to fill with commands
1036 * @pe: addr of the page entry
1037 * @src: src addr to copy from
1038 * @count: number of page entries to update
1039 *
1040 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1041 */
sdma_v5_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1042 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1043 uint64_t pe, uint64_t src,
1044 unsigned count)
1045 {
1046 unsigned bytes = count * 8;
1047
1048 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1049 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1050 ib->ptr[ib->length_dw++] = bytes - 1;
1051 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1052 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1053 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1054 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1055 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1056
1057 }
1058
1059 /**
1060 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1061 *
1062 * @ib: indirect buffer to fill with commands
1063 * @pe: addr of the page entry
1064 * @addr: dst addr to write into pe
1065 * @count: number of page entries to update
1066 * @incr: increase next addr by incr bytes
1067 * @flags: access flags
1068 *
1069 * Update PTEs by writing them manually using sDMA (NAVI10).
1070 */
sdma_v5_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1071 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1072 uint64_t value, unsigned count,
1073 uint32_t incr)
1074 {
1075 unsigned ndw = count * 2;
1076
1077 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1078 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1079 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1080 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1081 ib->ptr[ib->length_dw++] = ndw - 1;
1082 for (; ndw > 0; ndw -= 2) {
1083 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1084 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1085 value += incr;
1086 }
1087 }
1088
1089 /**
1090 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1091 *
1092 * @ib: indirect buffer to fill with commands
1093 * @pe: addr of the page entry
1094 * @addr: dst addr to write into pe
1095 * @count: number of page entries to update
1096 * @incr: increase next addr by incr bytes
1097 * @flags: access flags
1098 *
1099 * Update the page tables using sDMA (NAVI10).
1100 */
sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1101 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1102 uint64_t pe,
1103 uint64_t addr, unsigned count,
1104 uint32_t incr, uint64_t flags)
1105 {
1106 /* for physically contiguous pages (vram) */
1107 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1108 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1109 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1110 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1111 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1112 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1113 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1114 ib->ptr[ib->length_dw++] = incr; /* increment size */
1115 ib->ptr[ib->length_dw++] = 0;
1116 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1117 }
1118
1119 /**
1120 * sdma_v5_0_ring_pad_ib - pad the IB
1121 * @ib: indirect buffer to fill with padding
1122 *
1123 * Pad the IB with NOPs to a boundary multiple of 8.
1124 */
sdma_v5_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1125 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1126 {
1127 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1128 u32 pad_count;
1129 int i;
1130
1131 pad_count = (-ib->length_dw) & 0x7;
1132 for (i = 0; i < pad_count; i++)
1133 if (sdma && sdma->burst_nop && (i == 0))
1134 ib->ptr[ib->length_dw++] =
1135 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1136 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1137 else
1138 ib->ptr[ib->length_dw++] =
1139 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1140 }
1141
1142
1143 /**
1144 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1145 *
1146 * @ring: amdgpu_ring pointer
1147 *
1148 * Make sure all previous operations are completed (CIK).
1149 */
sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1150 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1151 {
1152 uint32_t seq = ring->fence_drv.sync_seq;
1153 uint64_t addr = ring->fence_drv.gpu_addr;
1154
1155 /* wait for idle */
1156 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1157 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1158 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1159 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1160 amdgpu_ring_write(ring, addr & 0xfffffffc);
1161 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1162 amdgpu_ring_write(ring, seq); /* reference */
1163 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1164 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1165 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1166 }
1167
1168
1169 /**
1170 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1171 *
1172 * @ring: amdgpu_ring pointer
1173 * @vm: amdgpu_vm pointer
1174 *
1175 * Update the page table base and flush the VM TLB
1176 * using sDMA (NAVI10).
1177 */
sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1178 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1179 unsigned vmid, uint64_t pd_addr)
1180 {
1181 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1182 }
1183
sdma_v5_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1184 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1185 uint32_t reg, uint32_t val)
1186 {
1187 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1188 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1189 amdgpu_ring_write(ring, reg);
1190 amdgpu_ring_write(ring, val);
1191 }
1192
sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1193 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1194 uint32_t val, uint32_t mask)
1195 {
1196 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1197 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1198 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1199 amdgpu_ring_write(ring, reg << 2);
1200 amdgpu_ring_write(ring, 0);
1201 amdgpu_ring_write(ring, val); /* reference */
1202 amdgpu_ring_write(ring, mask); /* mask */
1203 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1204 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1205 }
1206
sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1207 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1208 uint32_t reg0, uint32_t reg1,
1209 uint32_t ref, uint32_t mask)
1210 {
1211 amdgpu_ring_emit_wreg(ring, reg0, ref);
1212 /* wait for a cycle to reset vm_inv_eng*_ack */
1213 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1214 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1215 }
1216
sdma_v5_0_early_init(void * handle)1217 static int sdma_v5_0_early_init(void *handle)
1218 {
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221 adev->sdma.num_instances = 2;
1222
1223 sdma_v5_0_set_ring_funcs(adev);
1224 sdma_v5_0_set_buffer_funcs(adev);
1225 sdma_v5_0_set_vm_pte_funcs(adev);
1226 sdma_v5_0_set_irq_funcs(adev);
1227
1228 return 0;
1229 }
1230
1231
sdma_v5_0_sw_init(void * handle)1232 static int sdma_v5_0_sw_init(void *handle)
1233 {
1234 struct amdgpu_ring *ring;
1235 int r, i;
1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237
1238 /* SDMA trap event */
1239 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1240 SDMA0_5_0__SRCID__SDMA_TRAP,
1241 &adev->sdma.trap_irq);
1242 if (r)
1243 return r;
1244
1245 /* SDMA trap event */
1246 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1247 SDMA1_5_0__SRCID__SDMA_TRAP,
1248 &adev->sdma.trap_irq);
1249 if (r)
1250 return r;
1251
1252 r = sdma_v5_0_init_microcode(adev);
1253 if (r) {
1254 DRM_ERROR("Failed to load sdma firmware!\n");
1255 return r;
1256 }
1257
1258 for (i = 0; i < adev->sdma.num_instances; i++) {
1259 ring = &adev->sdma.instance[i].ring;
1260 ring->ring_obj = NULL;
1261 ring->use_doorbell = true;
1262
1263 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1264 ring->use_doorbell?"true":"false");
1265
1266 ring->doorbell_index = (i == 0) ?
1267 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1268 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1269
1270 sprintf(ring->name, "sdma%d", i);
1271 r = amdgpu_ring_init(adev, ring, 1024,
1272 &adev->sdma.trap_irq,
1273 (i == 0) ?
1274 AMDGPU_SDMA_IRQ_INSTANCE0 :
1275 AMDGPU_SDMA_IRQ_INSTANCE1,
1276 AMDGPU_RING_PRIO_DEFAULT);
1277 if (r)
1278 return r;
1279 }
1280
1281 return r;
1282 }
1283
sdma_v5_0_sw_fini(void * handle)1284 static int sdma_v5_0_sw_fini(void *handle)
1285 {
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 int i;
1288
1289 for (i = 0; i < adev->sdma.num_instances; i++) {
1290 release_firmware(adev->sdma.instance[i].fw);
1291 adev->sdma.instance[i].fw = NULL;
1292
1293 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1294 }
1295
1296 return 0;
1297 }
1298
sdma_v5_0_hw_init(void * handle)1299 static int sdma_v5_0_hw_init(void *handle)
1300 {
1301 int r;
1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304 sdma_v5_0_init_golden_registers(adev);
1305
1306 r = sdma_v5_0_start(adev);
1307
1308 return r;
1309 }
1310
sdma_v5_0_hw_fini(void * handle)1311 static int sdma_v5_0_hw_fini(void *handle)
1312 {
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315 if (amdgpu_sriov_vf(adev))
1316 return 0;
1317
1318 sdma_v5_0_ctx_switch_enable(adev, false);
1319 sdma_v5_0_enable(adev, false);
1320
1321 return 0;
1322 }
1323
sdma_v5_0_suspend(void * handle)1324 static int sdma_v5_0_suspend(void *handle)
1325 {
1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327
1328 return sdma_v5_0_hw_fini(adev);
1329 }
1330
sdma_v5_0_resume(void * handle)1331 static int sdma_v5_0_resume(void *handle)
1332 {
1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334
1335 return sdma_v5_0_hw_init(adev);
1336 }
1337
sdma_v5_0_is_idle(void * handle)1338 static bool sdma_v5_0_is_idle(void *handle)
1339 {
1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341 u32 i;
1342
1343 for (i = 0; i < adev->sdma.num_instances; i++) {
1344 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1345
1346 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1347 return false;
1348 }
1349
1350 return true;
1351 }
1352
sdma_v5_0_wait_for_idle(void * handle)1353 static int sdma_v5_0_wait_for_idle(void *handle)
1354 {
1355 unsigned i;
1356 u32 sdma0, sdma1;
1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358
1359 for (i = 0; i < adev->usec_timeout; i++) {
1360 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1361 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1362
1363 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1364 return 0;
1365 udelay(1);
1366 }
1367 return -ETIMEDOUT;
1368 }
1369
sdma_v5_0_soft_reset(void * handle)1370 static int sdma_v5_0_soft_reset(void *handle)
1371 {
1372 /* todo */
1373
1374 return 0;
1375 }
1376
sdma_v5_0_ring_preempt_ib(struct amdgpu_ring * ring)1377 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1378 {
1379 int i, r = 0;
1380 struct amdgpu_device *adev = ring->adev;
1381 u32 index = 0;
1382 u64 sdma_gfx_preempt;
1383
1384 amdgpu_sdma_get_index_from_ring(ring, &index);
1385 if (index == 0)
1386 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1387 else
1388 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1389
1390 /* assert preemption condition */
1391 amdgpu_ring_set_preempt_cond_exec(ring, false);
1392
1393 /* emit the trailing fence */
1394 ring->trail_seq += 1;
1395 amdgpu_ring_alloc(ring, 10);
1396 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1397 ring->trail_seq, 0);
1398 amdgpu_ring_commit(ring);
1399
1400 /* assert IB preemption */
1401 WREG32(sdma_gfx_preempt, 1);
1402
1403 /* poll the trailing fence */
1404 for (i = 0; i < adev->usec_timeout; i++) {
1405 if (ring->trail_seq ==
1406 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1407 break;
1408 udelay(1);
1409 }
1410
1411 if (i >= adev->usec_timeout) {
1412 r = -EINVAL;
1413 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1414 }
1415
1416 /* deassert IB preemption */
1417 WREG32(sdma_gfx_preempt, 0);
1418
1419 /* deassert the preemption condition */
1420 amdgpu_ring_set_preempt_cond_exec(ring, true);
1421 return r;
1422 }
1423
sdma_v5_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1424 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1425 struct amdgpu_irq_src *source,
1426 unsigned type,
1427 enum amdgpu_interrupt_state state)
1428 {
1429 u32 sdma_cntl;
1430
1431 if (!amdgpu_sriov_vf(adev)) {
1432 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1433 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1434 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1435
1436 sdma_cntl = RREG32(reg_offset);
1437 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1438 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1439 WREG32(reg_offset, sdma_cntl);
1440 }
1441
1442 return 0;
1443 }
1444
sdma_v5_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1445 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1446 struct amdgpu_irq_src *source,
1447 struct amdgpu_iv_entry *entry)
1448 {
1449 DRM_DEBUG("IH: SDMA trap\n");
1450 switch (entry->client_id) {
1451 case SOC15_IH_CLIENTID_SDMA0:
1452 switch (entry->ring_id) {
1453 case 0:
1454 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1455 break;
1456 case 1:
1457 /* XXX compute */
1458 break;
1459 case 2:
1460 /* XXX compute */
1461 break;
1462 case 3:
1463 /* XXX page queue*/
1464 break;
1465 }
1466 break;
1467 case SOC15_IH_CLIENTID_SDMA1:
1468 switch (entry->ring_id) {
1469 case 0:
1470 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1471 break;
1472 case 1:
1473 /* XXX compute */
1474 break;
1475 case 2:
1476 /* XXX compute */
1477 break;
1478 case 3:
1479 /* XXX page queue*/
1480 break;
1481 }
1482 break;
1483 }
1484 return 0;
1485 }
1486
sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1487 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1488 struct amdgpu_irq_src *source,
1489 struct amdgpu_iv_entry *entry)
1490 {
1491 return 0;
1492 }
1493
sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1494 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1495 bool enable)
1496 {
1497 uint32_t data, def;
1498 int i;
1499
1500 for (i = 0; i < adev->sdma.num_instances; i++) {
1501 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1502 /* Enable sdma clock gating */
1503 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1504 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1511 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1512 if (def != data)
1513 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1514 } else {
1515 /* Disable sdma clock gating */
1516 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1517 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1525 if (def != data)
1526 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1527 }
1528 }
1529 }
1530
sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1531 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1532 bool enable)
1533 {
1534 uint32_t data, def;
1535 int i;
1536
1537 for (i = 0; i < adev->sdma.num_instances; i++) {
1538 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1539 /* Enable sdma mem light sleep */
1540 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1541 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1542 if (def != data)
1543 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1544
1545 } else {
1546 /* Disable sdma mem light sleep */
1547 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1548 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1549 if (def != data)
1550 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1551
1552 }
1553 }
1554 }
1555
sdma_v5_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1556 static int sdma_v5_0_set_clockgating_state(void *handle,
1557 enum amd_clockgating_state state)
1558 {
1559 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560
1561 if (amdgpu_sriov_vf(adev))
1562 return 0;
1563
1564 switch (adev->asic_type) {
1565 case CHIP_NAVI10:
1566 case CHIP_NAVI14:
1567 case CHIP_NAVI12:
1568 sdma_v5_0_update_medium_grain_clock_gating(adev,
1569 state == AMD_CG_STATE_GATE);
1570 sdma_v5_0_update_medium_grain_light_sleep(adev,
1571 state == AMD_CG_STATE_GATE);
1572 break;
1573 default:
1574 break;
1575 }
1576
1577 return 0;
1578 }
1579
sdma_v5_0_set_powergating_state(void * handle,enum amd_powergating_state state)1580 static int sdma_v5_0_set_powergating_state(void *handle,
1581 enum amd_powergating_state state)
1582 {
1583 return 0;
1584 }
1585
sdma_v5_0_get_clockgating_state(void * handle,u32 * flags)1586 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1587 {
1588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1589 int data;
1590
1591 if (amdgpu_sriov_vf(adev))
1592 *flags = 0;
1593
1594 /* AMD_CG_SUPPORT_SDMA_MGCG */
1595 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1596 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1597 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1598
1599 /* AMD_CG_SUPPORT_SDMA_LS */
1600 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1601 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1602 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1603 }
1604
1605 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1606 .name = "sdma_v5_0",
1607 .early_init = sdma_v5_0_early_init,
1608 .late_init = NULL,
1609 .sw_init = sdma_v5_0_sw_init,
1610 .sw_fini = sdma_v5_0_sw_fini,
1611 .hw_init = sdma_v5_0_hw_init,
1612 .hw_fini = sdma_v5_0_hw_fini,
1613 .suspend = sdma_v5_0_suspend,
1614 .resume = sdma_v5_0_resume,
1615 .is_idle = sdma_v5_0_is_idle,
1616 .wait_for_idle = sdma_v5_0_wait_for_idle,
1617 .soft_reset = sdma_v5_0_soft_reset,
1618 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1619 .set_powergating_state = sdma_v5_0_set_powergating_state,
1620 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1621 };
1622
1623 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1624 .type = AMDGPU_RING_TYPE_SDMA,
1625 .align_mask = 0xf,
1626 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1627 .support_64bit_ptrs = true,
1628 .vmhub = AMDGPU_GFXHUB_0,
1629 .get_rptr = sdma_v5_0_ring_get_rptr,
1630 .get_wptr = sdma_v5_0_ring_get_wptr,
1631 .set_wptr = sdma_v5_0_ring_set_wptr,
1632 .emit_frame_size =
1633 5 + /* sdma_v5_0_ring_init_cond_exec */
1634 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1635 3 + /* hdp_invalidate */
1636 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1637 /* sdma_v5_0_ring_emit_vm_flush */
1638 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1639 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1640 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1641 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1642 .emit_ib = sdma_v5_0_ring_emit_ib,
1643 .emit_fence = sdma_v5_0_ring_emit_fence,
1644 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1645 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1646 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1647 .test_ring = sdma_v5_0_ring_test_ring,
1648 .test_ib = sdma_v5_0_ring_test_ib,
1649 .insert_nop = sdma_v5_0_ring_insert_nop,
1650 .pad_ib = sdma_v5_0_ring_pad_ib,
1651 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1652 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1653 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1654 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1655 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1656 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1657 };
1658
sdma_v5_0_set_ring_funcs(struct amdgpu_device * adev)1659 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1660 {
1661 int i;
1662
1663 for (i = 0; i < adev->sdma.num_instances; i++) {
1664 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1665 adev->sdma.instance[i].ring.me = i;
1666 }
1667 }
1668
1669 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1670 .set = sdma_v5_0_set_trap_irq_state,
1671 .process = sdma_v5_0_process_trap_irq,
1672 };
1673
1674 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1675 .process = sdma_v5_0_process_illegal_inst_irq,
1676 };
1677
sdma_v5_0_set_irq_funcs(struct amdgpu_device * adev)1678 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1679 {
1680 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1681 adev->sdma.num_instances;
1682 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1683 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1684 }
1685
1686 /**
1687 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1688 *
1689 * @ring: amdgpu_ring structure holding ring information
1690 * @src_offset: src GPU address
1691 * @dst_offset: dst GPU address
1692 * @byte_count: number of bytes to xfer
1693 *
1694 * Copy GPU buffers using the DMA engine (NAVI10).
1695 * Used by the amdgpu ttm implementation to move pages if
1696 * registered as the asic copy callback.
1697 */
sdma_v5_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1698 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1699 uint64_t src_offset,
1700 uint64_t dst_offset,
1701 uint32_t byte_count,
1702 bool tmz)
1703 {
1704 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1705 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1706 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1707 ib->ptr[ib->length_dw++] = byte_count - 1;
1708 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1709 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1710 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1711 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1712 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1713 }
1714
1715 /**
1716 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1717 *
1718 * @ring: amdgpu_ring structure holding ring information
1719 * @src_data: value to write to buffer
1720 * @dst_offset: dst GPU address
1721 * @byte_count: number of bytes to xfer
1722 *
1723 * Fill GPU buffers using the DMA engine (NAVI10).
1724 */
sdma_v5_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1725 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1726 uint32_t src_data,
1727 uint64_t dst_offset,
1728 uint32_t byte_count)
1729 {
1730 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1731 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1732 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1733 ib->ptr[ib->length_dw++] = src_data;
1734 ib->ptr[ib->length_dw++] = byte_count - 1;
1735 }
1736
1737 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1738 .copy_max_bytes = 0x400000,
1739 .copy_num_dw = 7,
1740 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1741
1742 .fill_max_bytes = 0x400000,
1743 .fill_num_dw = 5,
1744 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1745 };
1746
sdma_v5_0_set_buffer_funcs(struct amdgpu_device * adev)1747 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1748 {
1749 if (adev->mman.buffer_funcs == NULL) {
1750 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1751 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1752 }
1753 }
1754
1755 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1756 .copy_pte_num_dw = 7,
1757 .copy_pte = sdma_v5_0_vm_copy_pte,
1758 .write_pte = sdma_v5_0_vm_write_pte,
1759 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1760 };
1761
sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device * adev)1762 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1763 {
1764 unsigned i;
1765
1766 if (adev->vm_manager.vm_pte_funcs == NULL) {
1767 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1768 for (i = 0; i < adev->sdma.num_instances; i++) {
1769 adev->vm_manager.vm_pte_scheds[i] =
1770 &adev->sdma.instance[i].ring.sched;
1771 }
1772 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1773 }
1774 }
1775
1776 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1777 .type = AMD_IP_BLOCK_TYPE_SDMA,
1778 .major = 5,
1779 .minor = 0,
1780 .rev = 0,
1781 .funcs = &sdma_v5_0_ip_funcs,
1782 };
1783