1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2015 Atmel Corporation,
4 * Nicolas Ferre <nicolas.ferre@atmel.com>
5 *
6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk/at91_pmc.h>
13 #include <linux/of.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16
17 #include "pmc.h"
18
19 #define GENERATED_MAX_DIV 255
20
21 struct clk_generated {
22 struct clk_hw hw;
23 struct regmap *regmap;
24 struct clk_range range;
25 spinlock_t *lock;
26 u32 *mux_table;
27 u32 id;
28 u32 gckdiv;
29 const struct clk_pcr_layout *layout;
30 u8 parent_id;
31 int chg_pid;
32 };
33
34 #define to_clk_generated(hw) \
35 container_of(hw, struct clk_generated, hw)
36
clk_generated_enable(struct clk_hw * hw)37 static int clk_generated_enable(struct clk_hw *hw)
38 {
39 struct clk_generated *gck = to_clk_generated(hw);
40 unsigned long flags;
41
42 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
43 __func__, gck->gckdiv, gck->parent_id);
44
45 spin_lock_irqsave(gck->lock, flags);
46 regmap_write(gck->regmap, gck->layout->offset,
47 (gck->id & gck->layout->pid_mask));
48 regmap_update_bits(gck->regmap, gck->layout->offset,
49 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
50 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
51 field_prep(gck->layout->gckcss_mask, gck->parent_id) |
52 gck->layout->cmd |
53 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
54 AT91_PMC_PCR_GCKEN);
55 spin_unlock_irqrestore(gck->lock, flags);
56 return 0;
57 }
58
clk_generated_disable(struct clk_hw * hw)59 static void clk_generated_disable(struct clk_hw *hw)
60 {
61 struct clk_generated *gck = to_clk_generated(hw);
62 unsigned long flags;
63
64 spin_lock_irqsave(gck->lock, flags);
65 regmap_write(gck->regmap, gck->layout->offset,
66 (gck->id & gck->layout->pid_mask));
67 regmap_update_bits(gck->regmap, gck->layout->offset,
68 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
69 gck->layout->cmd);
70 spin_unlock_irqrestore(gck->lock, flags);
71 }
72
clk_generated_is_enabled(struct clk_hw * hw)73 static int clk_generated_is_enabled(struct clk_hw *hw)
74 {
75 struct clk_generated *gck = to_clk_generated(hw);
76 unsigned long flags;
77 unsigned int status;
78
79 spin_lock_irqsave(gck->lock, flags);
80 regmap_write(gck->regmap, gck->layout->offset,
81 (gck->id & gck->layout->pid_mask));
82 regmap_read(gck->regmap, gck->layout->offset, &status);
83 spin_unlock_irqrestore(gck->lock, flags);
84
85 return !!(status & AT91_PMC_PCR_GCKEN);
86 }
87
88 static unsigned long
clk_generated_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)89 clk_generated_recalc_rate(struct clk_hw *hw,
90 unsigned long parent_rate)
91 {
92 struct clk_generated *gck = to_clk_generated(hw);
93
94 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
95 }
96
clk_generated_best_diff(struct clk_rate_request * req,struct clk_hw * parent,unsigned long parent_rate,u32 div,int * best_diff,long * best_rate)97 static void clk_generated_best_diff(struct clk_rate_request *req,
98 struct clk_hw *parent,
99 unsigned long parent_rate, u32 div,
100 int *best_diff, long *best_rate)
101 {
102 unsigned long tmp_rate;
103 int tmp_diff;
104
105 if (!div)
106 tmp_rate = parent_rate;
107 else
108 tmp_rate = parent_rate / div;
109 tmp_diff = abs(req->rate - tmp_rate);
110
111 if (*best_diff < 0 || *best_diff >= tmp_diff) {
112 *best_rate = tmp_rate;
113 *best_diff = tmp_diff;
114 req->best_parent_rate = parent_rate;
115 req->best_parent_hw = parent;
116 }
117 }
118
clk_generated_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)119 static int clk_generated_determine_rate(struct clk_hw *hw,
120 struct clk_rate_request *req)
121 {
122 struct clk_generated *gck = to_clk_generated(hw);
123 struct clk_hw *parent = NULL;
124 struct clk_rate_request req_parent = *req;
125 long best_rate = -EINVAL;
126 unsigned long min_rate, parent_rate;
127 int best_diff = -1;
128 int i;
129 u32 div;
130
131 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
132 if (gck->chg_pid == i)
133 continue;
134
135 parent = clk_hw_get_parent_by_index(hw, i);
136 if (!parent)
137 continue;
138
139 parent_rate = clk_hw_get_rate(parent);
140 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
141 if (!parent_rate ||
142 (gck->range.max && min_rate > gck->range.max))
143 continue;
144
145 div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
146 if (div > GENERATED_MAX_DIV + 1)
147 div = GENERATED_MAX_DIV + 1;
148
149 clk_generated_best_diff(req, parent, parent_rate, div,
150 &best_diff, &best_rate);
151
152 if (!best_diff)
153 break;
154 }
155
156 /*
157 * The audio_pll rate can be modified, unlike the five others clocks
158 * that should never be altered.
159 * The audio_pll can technically be used by multiple consumers. However,
160 * with the rate locking, the first consumer to enable to clock will be
161 * the one definitely setting the rate of the clock.
162 * Since audio IPs are most likely to request the same rate, we enforce
163 * that the only clks able to modify gck rate are those of audio IPs.
164 */
165
166 if (gck->chg_pid < 0)
167 goto end;
168
169 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
170 if (!parent)
171 goto end;
172
173 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
174 req_parent.rate = req->rate * div;
175 if (__clk_determine_rate(parent, &req_parent))
176 continue;
177 clk_generated_best_diff(req, parent, req_parent.rate, div,
178 &best_diff, &best_rate);
179
180 if (!best_diff)
181 break;
182 }
183
184 end:
185 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
186 __func__, best_rate,
187 __clk_get_name((req->best_parent_hw)->clk),
188 req->best_parent_rate);
189
190 if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
191 return -EINVAL;
192
193 req->rate = best_rate;
194 return 0;
195 }
196
197 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
clk_generated_set_parent(struct clk_hw * hw,u8 index)198 static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
199 {
200 struct clk_generated *gck = to_clk_generated(hw);
201
202 if (index >= clk_hw_get_num_parents(hw))
203 return -EINVAL;
204
205 if (gck->mux_table)
206 gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
207 else
208 gck->parent_id = index;
209
210 return 0;
211 }
212
clk_generated_get_parent(struct clk_hw * hw)213 static u8 clk_generated_get_parent(struct clk_hw *hw)
214 {
215 struct clk_generated *gck = to_clk_generated(hw);
216
217 return gck->parent_id;
218 }
219
220 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
clk_generated_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)221 static int clk_generated_set_rate(struct clk_hw *hw,
222 unsigned long rate,
223 unsigned long parent_rate)
224 {
225 struct clk_generated *gck = to_clk_generated(hw);
226 u32 div;
227
228 if (!rate)
229 return -EINVAL;
230
231 if (gck->range.max && rate > gck->range.max)
232 return -EINVAL;
233
234 div = DIV_ROUND_CLOSEST(parent_rate, rate);
235 if (div > GENERATED_MAX_DIV + 1 || !div)
236 return -EINVAL;
237
238 gck->gckdiv = div - 1;
239 return 0;
240 }
241
242 static const struct clk_ops generated_ops = {
243 .enable = clk_generated_enable,
244 .disable = clk_generated_disable,
245 .is_enabled = clk_generated_is_enabled,
246 .recalc_rate = clk_generated_recalc_rate,
247 .determine_rate = clk_generated_determine_rate,
248 .get_parent = clk_generated_get_parent,
249 .set_parent = clk_generated_set_parent,
250 .set_rate = clk_generated_set_rate,
251 };
252
253 /**
254 * clk_generated_startup - Initialize a given clock to its default parent and
255 * divisor parameter.
256 *
257 * @gck: Generated clock to set the startup parameters for.
258 *
259 * Take parameters from the hardware and update local clock configuration
260 * accordingly.
261 */
clk_generated_startup(struct clk_generated * gck)262 static void clk_generated_startup(struct clk_generated *gck)
263 {
264 u32 tmp;
265 unsigned long flags;
266
267 spin_lock_irqsave(gck->lock, flags);
268 regmap_write(gck->regmap, gck->layout->offset,
269 (gck->id & gck->layout->pid_mask));
270 regmap_read(gck->regmap, gck->layout->offset, &tmp);
271 spin_unlock_irqrestore(gck->lock, flags);
272
273 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
274 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
275 }
276
277 struct clk_hw * __init
at91_clk_register_generated(struct regmap * regmap,spinlock_t * lock,const struct clk_pcr_layout * layout,const char * name,const char ** parent_names,u32 * mux_table,u8 num_parents,u8 id,const struct clk_range * range,int chg_pid)278 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
279 const struct clk_pcr_layout *layout,
280 const char *name, const char **parent_names,
281 u32 *mux_table, u8 num_parents, u8 id,
282 const struct clk_range *range,
283 int chg_pid)
284 {
285 struct clk_generated *gck;
286 struct clk_init_data init;
287 struct clk_hw *hw;
288 int ret;
289
290 gck = kzalloc(sizeof(*gck), GFP_KERNEL);
291 if (!gck)
292 return ERR_PTR(-ENOMEM);
293
294 init.name = name;
295 init.ops = &generated_ops;
296 init.parent_names = parent_names;
297 init.num_parents = num_parents;
298 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
299 if (chg_pid >= 0)
300 init.flags |= CLK_SET_RATE_PARENT;
301
302 gck->id = id;
303 gck->hw.init = &init;
304 gck->regmap = regmap;
305 gck->lock = lock;
306 gck->range = *range;
307 gck->chg_pid = chg_pid;
308 gck->layout = layout;
309 gck->mux_table = mux_table;
310
311 clk_generated_startup(gck);
312 hw = &gck->hw;
313 ret = clk_hw_register(NULL, &gck->hw);
314 if (ret) {
315 kfree(gck);
316 hw = ERR_PTR(ret);
317 } else {
318 pmc_register_id(id);
319 }
320
321 return hw;
322 }
323