1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Alt board
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 */
7
8/dts-v1/;
9#include "r8a7794.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	model = "Alt";
14	compatible = "renesas,alt", "renesas,r8a7794";
15
16	aliases {
17		serial0 = &scif2;
18		i2c9 = &gpioi2c1;
19		i2c10 = &gpioi2c4;
20		i2c11 = &i2chdmi;
21		i2c12 = &i2cexio4;
22	};
23
24	chosen {
25		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
26		stdout-path = "serial0:115200n8";
27	};
28
29	memory@40000000 {
30		device_type = "memory";
31		reg = <0 0x40000000 0 0x40000000>;
32	};
33
34	d3_3v: regulator-d3-3v {
35		compatible = "regulator-fixed";
36		regulator-name = "D3.3V";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-boot-on;
40		regulator-always-on;
41	};
42
43	vcc_sdhi0: regulator-vcc-sdhi0 {
44		compatible = "regulator-fixed";
45
46		regulator-name = "SDHI0 Vcc";
47		regulator-min-microvolt = <3300000>;
48		regulator-max-microvolt = <3300000>;
49
50		gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
51		enable-active-high;
52	};
53
54	vccq_sdhi0: regulator-vccq-sdhi0 {
55		compatible = "regulator-gpio";
56
57		regulator-name = "SDHI0 VccQ";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <3300000>;
60
61		gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
62		gpios-states = <1>;
63		states = <3300000 1>, <1800000 0>;
64	};
65
66	vcc_sdhi1: regulator-vcc-sdhi1 {
67		compatible = "regulator-fixed";
68
69		regulator-name = "SDHI1 Vcc";
70		regulator-min-microvolt = <3300000>;
71		regulator-max-microvolt = <3300000>;
72
73		gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
74		enable-active-high;
75	};
76
77	vccq_sdhi1: regulator-vccq-sdhi1 {
78		compatible = "regulator-gpio";
79
80		regulator-name = "SDHI1 VccQ";
81		regulator-min-microvolt = <1800000>;
82		regulator-max-microvolt = <3300000>;
83
84		gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
85		gpios-states = <1>;
86		states = <3300000 1>, <1800000 0>;
87	};
88
89	lbsc {
90		#address-cells = <1>;
91		#size-cells = <1>;
92	};
93
94	vga-encoder {
95		compatible = "adi,adv7123";
96
97		ports {
98			#address-cells = <1>;
99			#size-cells = <0>;
100
101			port@0 {
102				reg = <0>;
103				adv7123_in: endpoint {
104					remote-endpoint = <&du_out_rgb1>;
105				};
106			};
107			port@1 {
108				reg = <1>;
109				adv7123_out: endpoint {
110					remote-endpoint = <&vga_in>;
111				};
112			};
113		};
114	};
115
116	vga {
117		compatible = "vga-connector";
118
119		port {
120			vga_in: endpoint {
121				remote-endpoint = <&adv7123_out>;
122			};
123		};
124	};
125
126	x2_clk: x2-clock {
127		compatible = "fixed-clock";
128		#clock-cells = <0>;
129		clock-frequency = <74250000>;
130	};
131
132	x13_clk: x13-clock {
133		compatible = "fixed-clock";
134		#clock-cells = <0>;
135		clock-frequency = <148500000>;
136	};
137
138	gpioi2c1: i2c-9 {
139		#address-cells = <1>;
140		#size-cells = <0>;
141		compatible = "i2c-gpio";
142		status = "disabled";
143		scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
144		sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
145	};
146
147	gpioi2c4: i2c-10 {
148		#address-cells = <1>;
149		#size-cells = <0>;
150		compatible = "i2c-gpio";
151		status = "disabled";
152		scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153		sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
154		i2c-gpio,delay-us = <5>;
155	};
156
157	/*
158	 * A fallback to GPIO is provided for I2C1.
159	 */
160	i2chdmi: i2c-11 {
161		compatible = "i2c-demux-pinctrl";
162		i2c-parent = <&i2c1>, <&gpioi2c1>;
163		i2c-bus-name = "i2c-hdmi";
164		#address-cells = <1>;
165		#size-cells = <0>;
166
167		composite-in@20 {
168			compatible = "adi,adv7180";
169			reg = <0x20>;
170
171			port {
172				adv7180: endpoint {
173					bus-width = <8>;
174					remote-endpoint = <&vin0ep>;
175				};
176			};
177		};
178
179		eeprom@50 {
180			compatible = "renesas,r1ex24002", "atmel,24c02";
181			reg = <0x50>;
182			pagesize = <16>;
183		};
184	};
185
186	/*
187	 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
188	 * A fallback to GPIO is provided.
189	 */
190	i2cexio4: i2c-14 {
191		compatible = "i2c-demux-pinctrl";
192		i2c-parent = <&i2c4>, <&gpioi2c4>;
193		i2c-bus-name = "i2c-exio4";
194		#address-cells = <1>;
195		#size-cells = <0>;
196	};
197};
198
199&pci0 {
200	status = "okay";
201	pinctrl-0 = <&usb0_pins>;
202	pinctrl-names = "default";
203};
204
205&pci1 {
206	status = "okay";
207	pinctrl-0 = <&usb1_pins>;
208	pinctrl-names = "default";
209};
210
211&usbphy {
212	status = "okay";
213};
214
215&du {
216	pinctrl-0 = <&du_pins>;
217	pinctrl-names = "default";
218	status = "okay";
219
220	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
221		 <&x13_clk>, <&x2_clk>;
222	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
223
224	ports {
225		port@1 {
226			endpoint {
227				remote-endpoint = <&adv7123_in>;
228			};
229		};
230	};
231};
232
233&extal_clk {
234	clock-frequency = <20000000>;
235};
236
237&pfc {
238	pinctrl-0 = <&scif_clk_pins>;
239	pinctrl-names = "default";
240
241	du_pins: du {
242		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
243		function = "du1";
244	};
245
246	scif2_pins: scif2 {
247		groups = "scif2_data";
248		function = "scif2";
249	};
250
251	scif_clk_pins: scif_clk {
252		groups = "scif_clk";
253		function = "scif_clk";
254	};
255
256	ether_pins: ether {
257		groups = "eth_link", "eth_mdio", "eth_rmii";
258		function = "eth";
259	};
260
261	phy1_pins: phy1 {
262		groups = "intc_irq8";
263		function = "intc";
264	};
265
266	i2c1_pins: i2c1 {
267		groups = "i2c1";
268		function = "i2c1";
269	};
270
271	i2c4_pins: i2c4 {
272		groups = "i2c4";
273		function = "i2c4";
274	};
275
276	vin0_pins: vin0 {
277		groups = "vin0_data8", "vin0_clk";
278		function = "vin0";
279	};
280
281	mmcif0_pins: mmcif0 {
282		groups = "mmc_data8", "mmc_ctrl";
283		function = "mmc";
284	};
285
286	sdhi0_pins: sd0 {
287		groups = "sdhi0_data4", "sdhi0_ctrl";
288		function = "sdhi0";
289		power-source = <3300>;
290	};
291
292	sdhi0_pins_uhs: sd0_uhs {
293		groups = "sdhi0_data4", "sdhi0_ctrl";
294		function = "sdhi0";
295		power-source = <1800>;
296	};
297
298	sdhi1_pins: sd1 {
299		groups = "sdhi1_data4", "sdhi1_ctrl";
300		function = "sdhi1";
301		power-source = <3300>;
302	};
303
304	sdhi1_pins_uhs: sd1_uhs {
305		groups = "sdhi1_data4", "sdhi1_ctrl";
306		function = "sdhi1";
307		power-source = <1800>;
308	};
309
310	usb0_pins: usb0 {
311		groups = "usb0";
312		function = "usb0";
313	};
314
315	usb1_pins: usb1 {
316		groups = "usb1";
317		function = "usb1";
318	};
319};
320
321&cmt0 {
322	status = "okay";
323};
324
325&pfc {
326	qspi_pins: qspi {
327		groups = "qspi_ctrl", "qspi_data4";
328		function = "qspi";
329	};
330};
331
332&ether {
333	pinctrl-0 = <&ether_pins &phy1_pins>;
334	pinctrl-names = "default";
335
336	phy-handle = <&phy1>;
337	renesas,ether-link-active-low;
338	status = "okay";
339
340	phy1: ethernet-phy@1 {
341		reg = <1>;
342		interrupt-parent = <&irqc0>;
343		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
344		micrel,led-mode = <1>;
345		reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
346	};
347};
348
349&mmcif0 {
350	pinctrl-0 = <&mmcif0_pins>;
351	pinctrl-names = "default";
352
353	vmmc-supply = <&d3_3v>;
354	vqmmc-supply = <&d3_3v>;
355	bus-width = <8>;
356	non-removable;
357	status = "okay";
358};
359
360&rwdt {
361	timeout-sec = <60>;
362	status = "okay";
363};
364
365&sdhi0 {
366	pinctrl-0 = <&sdhi0_pins>;
367	pinctrl-1 = <&sdhi0_pins_uhs>;
368	pinctrl-names = "default", "state_uhs";
369
370	vmmc-supply = <&vcc_sdhi0>;
371	vqmmc-supply = <&vccq_sdhi0>;
372	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
373	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
374	sd-uhs-sdr50;
375	sd-uhs-sdr104;
376	status = "okay";
377};
378
379&sdhi1 {
380	pinctrl-0 = <&sdhi1_pins>;
381	pinctrl-1 = <&sdhi1_pins_uhs>;
382	pinctrl-names = "default", "state_uhs";
383
384	vmmc-supply = <&vcc_sdhi1>;
385	vqmmc-supply = <&vccq_sdhi1>;
386	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
387	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
388	sd-uhs-sdr50;
389	status = "okay";
390};
391
392&i2c1 {
393	pinctrl-0 = <&i2c1_pins>;
394	pinctrl-names = "i2c-hdmi";
395
396	clock-frequency = <400000>;
397};
398
399&i2c4 {
400	pinctrl-0 = <&i2c4_pins>;
401	pinctrl-names = "i2c-exio4";
402};
403
404&i2c7 {
405	status = "okay";
406	clock-frequency = <100000>;
407
408	pmic@58 {
409		compatible = "dlg,da9063";
410		reg = <0x58>;
411		interrupt-parent = <&gpio3>;
412		interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
413		interrupt-controller;
414
415		rtc {
416			compatible = "dlg,da9063-rtc";
417		};
418
419		wdt {
420			compatible = "dlg,da9063-watchdog";
421		};
422	};
423};
424
425&vin0 {
426	status = "okay";
427	pinctrl-0 = <&vin0_pins>;
428	pinctrl-names = "default";
429
430	port {
431		vin0ep: endpoint {
432			remote-endpoint = <&adv7180>;
433			bus-width = <8>;
434		};
435	};
436};
437
438&scif2 {
439	pinctrl-0 = <&scif2_pins>;
440	pinctrl-names = "default";
441
442	status = "okay";
443};
444
445&scif_clk {
446	clock-frequency = <14745600>;
447};
448
449&qspi {
450	pinctrl-0 = <&qspi_pins>;
451	pinctrl-names = "default";
452
453	status = "okay";
454
455	flash@0 {
456		compatible = "spansion,s25fl512s", "jedec,spi-nor";
457		reg = <0>;
458		spi-max-frequency = <30000000>;
459		spi-tx-bus-width = <4>;
460		spi-rx-bus-width = <4>;
461		spi-cpol;
462		spi-cpha;
463		m25p,fast-read;
464
465		partitions {
466			compatible = "fixed-partitions";
467			#address-cells = <1>;
468			#size-cells = <1>;
469
470			partition@0 {
471				label = "loader";
472				reg = <0x00000000 0x00040000>;
473				read-only;
474			};
475			partition@40000 {
476				label = "system";
477				reg = <0x00040000 0x00040000>;
478				read-only;
479			};
480			partition@80000 {
481				label = "user";
482				reg = <0x00080000 0x03f80000>;
483			};
484		};
485	};
486};
487