1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/clock/dra7.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12#include <dt-bindings/clock/dra7.h> 13 14#define MAX_SOURCES 400 15 16/ { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 compatible = "ti,dra7xx"; 21 interrupt-parent = <&crossbar_mpu>; 22 chosen { }; 23 24 aliases { 25 i2c0 = &i2c1; 26 i2c1 = &i2c2; 27 i2c2 = &i2c3; 28 i2c3 = &i2c4; 29 i2c4 = &i2c5; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 ethernet0 = &cpsw_port1; 41 ethernet1 = &cpsw_port2; 42 d_can0 = &dcan1; 43 d_can1 = &dcan2; 44 spi0 = &qspi; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&gic>; 54 }; 55 56 gic: interrupt-controller@48211000 { 57 compatible = "arm,cortex-a15-gic"; 58 interrupt-controller; 59 #interrupt-cells = <3>; 60 reg = <0x0 0x48211000 0x0 0x1000>, 61 <0x0 0x48212000 0x0 0x2000>, 62 <0x0 0x48214000 0x0 0x2000>, 63 <0x0 0x48216000 0x0 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 65 interrupt-parent = <&gic>; 66 }; 67 68 wakeupgen: interrupt-controller@48281000 { 69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 70 interrupt-controller; 71 #interrupt-cells = <3>; 72 reg = <0x0 0x48281000 0x0 0x1000>; 73 interrupt-parent = <&gic>; 74 }; 75 76 cpus { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a15"; 83 reg = <0>; 84 85 operating-points-v2 = <&cpu0_opp_table>; 86 87 clocks = <&dpll_mpu_ck>; 88 clock-names = "cpu"; 89 90 clock-latency = <300000>; /* From omap-cpufreq driver */ 91 92 /* cooling options */ 93 #cooling-cells = <2>; /* min followed by max */ 94 95 vbb-supply = <&abb_mpu>; 96 }; 97 }; 98 99 cpu0_opp_table: opp-table { 100 compatible = "operating-points-v2-ti-cpu"; 101 syscon = <&scm_wkup>; 102 103 opp_nom-1000000000 { 104 opp-hz = /bits/ 64 <1000000000>; 105 opp-microvolt = <1060000 850000 1150000>, 106 <1060000 850000 1150000>; 107 opp-supported-hw = <0xFF 0x01>; 108 opp-suspend; 109 }; 110 111 opp_od-1176000000 { 112 opp-hz = /bits/ 64 <1176000000>; 113 opp-microvolt = <1160000 885000 1160000>, 114 <1160000 885000 1160000>; 115 116 opp-supported-hw = <0xFF 0x02>; 117 }; 118 119 opp_high@1500000000 { 120 opp-hz = /bits/ 64 <1500000000>; 121 opp-microvolt = <1210000 950000 1250000>, 122 <1210000 950000 1250000>; 123 opp-supported-hw = <0xFF 0x04>; 124 }; 125 }; 126 127 /* 128 * The soc node represents the soc top level view. It is used for IPs 129 * that are not memory mapped in the MPU view or for the MPU itself. 130 */ 131 soc { 132 compatible = "ti,omap-infra"; 133 mpu { 134 compatible = "ti,omap5-mpu"; 135 ti,hwmods = "mpu"; 136 }; 137 }; 138 139 /* 140 * XXX: Use a flat representation of the SOC interconnect. 141 * The real OMAP interconnect network is quite complex. 142 * Since it will not bring real advantage to represent that in DT for 143 * the moment, just use a fake OCP bus entry to represent the whole bus 144 * hierarchy. 145 */ 146 ocp: ocp { 147 compatible = "ti,dra7-l3-noc", "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0x0 0x0 0x0 0xc0000000>; 151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 152 ti,hwmods = "l3_main_1", "l3_main_2"; 153 reg = <0x0 0x44000000 0x0 0x1000000>, 154 <0x0 0x45000000 0x0 0x1000>; 155 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 156 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 157 158 l4_cfg: interconnect@4a000000 { 159 }; 160 l4_wkup: interconnect@4ae00000 { 161 }; 162 l4_per1: interconnect@48000000 { 163 }; 164 l4_per2: interconnect@48400000 { 165 }; 166 l4_per3: interconnect@48800000 { 167 }; 168 169 axi@0 { 170 compatible = "simple-bus"; 171 #size-cells = <1>; 172 #address-cells = <1>; 173 ranges = <0x51000000 0x51000000 0x3000 174 0x0 0x20000000 0x10000000>; 175 dma-ranges; 176 /** 177 * To enable PCI endpoint mode, disable the pcie1_rc 178 * node and enable pcie1_ep mode. 179 */ 180 pcie1_rc: pcie@51000000 { 181 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 182 reg-names = "rc_dbics", "ti_conf", "config"; 183 interrupts = <0 232 0x4>, <0 233 0x4>; 184 #address-cells = <3>; 185 #size-cells = <2>; 186 device_type = "pci"; 187 ranges = <0x81000000 0 0 0x03000 0 0x00010000 188 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 189 bus-range = <0x00 0xff>; 190 #interrupt-cells = <1>; 191 num-lanes = <1>; 192 linux,pci-domain = <0>; 193 ti,hwmods = "pcie1"; 194 phys = <&pcie1_phy>; 195 phy-names = "pcie-phy0"; 196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 197 interrupt-map-mask = <0 0 0 7>; 198 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 199 <0 0 0 2 &pcie1_intc 2>, 200 <0 0 0 3 &pcie1_intc 3>, 201 <0 0 0 4 &pcie1_intc 4>; 202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 203 status = "disabled"; 204 pcie1_intc: interrupt-controller { 205 interrupt-controller; 206 #address-cells = <0>; 207 #interrupt-cells = <1>; 208 }; 209 }; 210 211 pcie1_ep: pcie_ep@51000000 { 212 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 213 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 214 interrupts = <0 232 0x4>; 215 num-lanes = <1>; 216 num-ib-windows = <4>; 217 num-ob-windows = <16>; 218 ti,hwmods = "pcie1"; 219 phys = <&pcie1_phy>; 220 phy-names = "pcie-phy0"; 221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 223 status = "disabled"; 224 }; 225 }; 226 227 axi@1 { 228 compatible = "simple-bus"; 229 #size-cells = <1>; 230 #address-cells = <1>; 231 ranges = <0x51800000 0x51800000 0x3000 232 0x0 0x30000000 0x10000000>; 233 dma-ranges; 234 status = "disabled"; 235 pcie2_rc: pcie@51800000 { 236 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 237 reg-names = "rc_dbics", "ti_conf", "config"; 238 interrupts = <0 355 0x4>, <0 356 0x4>; 239 #address-cells = <3>; 240 #size-cells = <2>; 241 device_type = "pci"; 242 ranges = <0x81000000 0 0 0x03000 0 0x00010000 243 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 244 bus-range = <0x00 0xff>; 245 #interrupt-cells = <1>; 246 num-lanes = <1>; 247 linux,pci-domain = <1>; 248 ti,hwmods = "pcie2"; 249 phys = <&pcie2_phy>; 250 phy-names = "pcie-phy0"; 251 interrupt-map-mask = <0 0 0 7>; 252 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 253 <0 0 0 2 &pcie2_intc 2>, 254 <0 0 0 3 &pcie2_intc 3>, 255 <0 0 0 4 &pcie2_intc 4>; 256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 257 pcie2_intc: interrupt-controller { 258 interrupt-controller; 259 #address-cells = <0>; 260 #interrupt-cells = <1>; 261 }; 262 }; 263 }; 264 265 ocmcram1: ocmcram@40300000 { 266 compatible = "mmio-sram"; 267 reg = <0x40300000 0x80000>; 268 ranges = <0x0 0x40300000 0x80000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 /* 272 * This is a placeholder for an optional reserved 273 * region for use by secure software. The size 274 * of this region is not known until runtime so it 275 * is set as zero to either be updated to reserve 276 * space or left unchanged to leave all SRAM for use. 277 * On HS parts that that require the reserved region 278 * either the bootloader can update the size to 279 * the required amount or the node can be overridden 280 * from the board dts file for the secure platform. 281 */ 282 sram-hs@0 { 283 compatible = "ti,secure-ram"; 284 reg = <0x0 0x0>; 285 }; 286 }; 287 288 /* 289 * NOTE: ocmcram2 and ocmcram3 are not available on all 290 * DRA7xx and AM57xx variants. Confirm availability in 291 * the data manual for the exact part number in use 292 * before enabling these nodes in the board dts file. 293 */ 294 ocmcram2: ocmcram@40400000 { 295 status = "disabled"; 296 compatible = "mmio-sram"; 297 reg = <0x40400000 0x100000>; 298 ranges = <0x0 0x40400000 0x100000>; 299 #address-cells = <1>; 300 #size-cells = <1>; 301 }; 302 303 ocmcram3: ocmcram@40500000 { 304 status = "disabled"; 305 compatible = "mmio-sram"; 306 reg = <0x40500000 0x100000>; 307 ranges = <0x0 0x40500000 0x100000>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 }; 311 312 bandgap: bandgap@4a0021e0 { 313 reg = <0x4a0021e0 0xc 314 0x4a00232c 0xc 315 0x4a002380 0x2c 316 0x4a0023C0 0x3c 317 0x4a002564 0x8 318 0x4a002574 0x50>; 319 compatible = "ti,dra752-bandgap"; 320 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 321 #thermal-sensor-cells = <1>; 322 }; 323 324 dsp1_system: dsp_system@40d00000 { 325 compatible = "syscon"; 326 reg = <0x40d00000 0x100>; 327 }; 328 329 dra7_iodelay_core: padconf@4844a000 { 330 compatible = "ti,dra7-iodelay"; 331 reg = <0x4844a000 0x0d1c>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 #pinctrl-cells = <2>; 335 }; 336 337 target-module@43300000 { 338 compatible = "ti,sysc-omap4", "ti,sysc"; 339 reg = <0x43300000 0x4>; 340 reg-names = "rev"; 341 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; 342 clock-names = "fck"; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 ranges = <0x0 0x43300000 0x100000>; 346 347 edma: dma@0 { 348 compatible = "ti,edma3-tpcc"; 349 reg = <0 0x100000>; 350 reg-names = "edma3_cc"; 351 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-names = "edma3_ccint", "edma3_mperr", 355 "edma3_ccerrint"; 356 dma-requests = <64>; 357 #dma-cells = <2>; 358 359 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 360 361 /* 362 * memcpy is disabled, can be enabled with: 363 * ti,edma-memcpy-channels = <20 21>; 364 * for example. Note that these channels need to be 365 * masked in the xbar as well. 366 */ 367 }; 368 }; 369 370 target-module@43400000 { 371 compatible = "ti,sysc-omap4", "ti,sysc"; 372 reg = <0x43400000 0x4>; 373 reg-names = "rev"; 374 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; 375 clock-names = "fck"; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 ranges = <0x0 0x43400000 0x100000>; 379 380 edma_tptc0: dma@0 { 381 compatible = "ti,edma3-tptc"; 382 reg = <0 0x100000>; 383 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 384 interrupt-names = "edma3_tcerrint"; 385 }; 386 }; 387 388 target-module@43500000 { 389 compatible = "ti,sysc-omap4", "ti,sysc"; 390 reg = <0x43500000 0x4>; 391 reg-names = "rev"; 392 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; 393 clock-names = "fck"; 394 #address-cells = <1>; 395 #size-cells = <1>; 396 ranges = <0x0 0x43500000 0x100000>; 397 398 edma_tptc1: dma@0 { 399 compatible = "ti,edma3-tptc"; 400 reg = <0 0x100000>; 401 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "edma3_tcerrint"; 403 }; 404 }; 405 406 dmm@4e000000 { 407 compatible = "ti,omap5-dmm"; 408 reg = <0x4e000000 0x800>; 409 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 410 ti,hwmods = "dmm"; 411 }; 412 413 ipu1: ipu@58820000 { 414 compatible = "ti,dra7-ipu"; 415 reg = <0x58820000 0x10000>; 416 reg-names = "l2ram"; 417 iommus = <&mmu_ipu1>; 418 status = "disabled"; 419 resets = <&prm_ipu 0>, <&prm_ipu 1>; 420 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 421 firmware-name = "dra7-ipu1-fw.xem4"; 422 }; 423 424 ipu2: ipu@55020000 { 425 compatible = "ti,dra7-ipu"; 426 reg = <0x55020000 0x10000>; 427 reg-names = "l2ram"; 428 iommus = <&mmu_ipu2>; 429 status = "disabled"; 430 resets = <&prm_core 0>, <&prm_core 1>; 431 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 432 firmware-name = "dra7-ipu2-fw.xem4"; 433 }; 434 435 dsp1: dsp@40800000 { 436 compatible = "ti,dra7-dsp"; 437 reg = <0x40800000 0x48000>, 438 <0x40e00000 0x8000>, 439 <0x40f00000 0x8000>; 440 reg-names = "l2ram", "l1pram", "l1dram"; 441 ti,bootreg = <&scm_conf 0x55c 10>; 442 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 443 status = "disabled"; 444 resets = <&prm_dsp1 0>; 445 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 446 firmware-name = "dra7-dsp1-fw.xe66"; 447 }; 448 449 target-module@40d01000 { 450 compatible = "ti,sysc-omap2", "ti,sysc"; 451 reg = <0x40d01000 0x4>, 452 <0x40d01010 0x4>, 453 <0x40d01014 0x4>; 454 reg-names = "rev", "sysc", "syss"; 455 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 456 <SYSC_IDLE_NO>, 457 <SYSC_IDLE_SMART>; 458 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 459 SYSC_OMAP2_SOFTRESET | 460 SYSC_OMAP2_AUTOIDLE)>; 461 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 462 clock-names = "fck"; 463 resets = <&prm_dsp1 1>; 464 reset-names = "rstctrl"; 465 ranges = <0x0 0x40d01000 0x1000>; 466 #size-cells = <1>; 467 #address-cells = <1>; 468 469 mmu0_dsp1: mmu@0 { 470 compatible = "ti,dra7-dsp-iommu"; 471 reg = <0x0 0x100>; 472 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 473 #iommu-cells = <0>; 474 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 475 }; 476 }; 477 478 target-module@40d02000 { 479 compatible = "ti,sysc-omap2", "ti,sysc"; 480 reg = <0x40d02000 0x4>, 481 <0x40d02010 0x4>, 482 <0x40d02014 0x4>; 483 reg-names = "rev", "sysc", "syss"; 484 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 485 <SYSC_IDLE_NO>, 486 <SYSC_IDLE_SMART>; 487 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 488 SYSC_OMAP2_SOFTRESET | 489 SYSC_OMAP2_AUTOIDLE)>; 490 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 491 clock-names = "fck"; 492 resets = <&prm_dsp1 1>; 493 reset-names = "rstctrl"; 494 ranges = <0x0 0x40d02000 0x1000>; 495 #size-cells = <1>; 496 #address-cells = <1>; 497 498 mmu1_dsp1: mmu@0 { 499 compatible = "ti,dra7-dsp-iommu"; 500 reg = <0x0 0x100>; 501 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 502 #iommu-cells = <0>; 503 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 504 }; 505 }; 506 507 target-module@58882000 { 508 compatible = "ti,sysc-omap2", "ti,sysc"; 509 reg = <0x58882000 0x4>, 510 <0x58882010 0x4>, 511 <0x58882014 0x4>; 512 reg-names = "rev", "sysc", "syss"; 513 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 514 <SYSC_IDLE_NO>, 515 <SYSC_IDLE_SMART>; 516 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 517 SYSC_OMAP2_SOFTRESET | 518 SYSC_OMAP2_AUTOIDLE)>; 519 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 520 clock-names = "fck"; 521 resets = <&prm_ipu 2>; 522 reset-names = "rstctrl"; 523 #address-cells = <1>; 524 #size-cells = <1>; 525 ranges = <0x0 0x58882000 0x100>; 526 527 mmu_ipu1: mmu@0 { 528 compatible = "ti,dra7-iommu"; 529 reg = <0x0 0x100>; 530 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 531 #iommu-cells = <0>; 532 ti,iommu-bus-err-back; 533 }; 534 }; 535 536 target-module@55082000 { 537 compatible = "ti,sysc-omap2", "ti,sysc"; 538 reg = <0x55082000 0x4>, 539 <0x55082010 0x4>, 540 <0x55082014 0x4>; 541 reg-names = "rev", "sysc", "syss"; 542 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 543 <SYSC_IDLE_NO>, 544 <SYSC_IDLE_SMART>; 545 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 546 SYSC_OMAP2_SOFTRESET | 547 SYSC_OMAP2_AUTOIDLE)>; 548 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 549 clock-names = "fck"; 550 resets = <&prm_core 2>; 551 reset-names = "rstctrl"; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 ranges = <0x0 0x55082000 0x100>; 555 556 mmu_ipu2: mmu@0 { 557 compatible = "ti,dra7-iommu"; 558 reg = <0x0 0x100>; 559 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 560 #iommu-cells = <0>; 561 ti,iommu-bus-err-back; 562 }; 563 }; 564 565 abb_mpu: regulator-abb-mpu { 566 compatible = "ti,abb-v3"; 567 regulator-name = "abb_mpu"; 568 #address-cells = <0>; 569 #size-cells = <0>; 570 clocks = <&sys_clkin1>; 571 ti,settling-time = <50>; 572 ti,clock-cycles = <16>; 573 574 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 575 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 576 <0x4ae0c158 0x4>; 577 reg-names = "setup-address", "control-address", 578 "int-address", "efuse-address", 579 "ldo-address"; 580 ti,tranxdone-status-mask = <0x80>; 581 /* LDOVBBMPU_FBB_MUX_CTRL */ 582 ti,ldovbb-override-mask = <0x400>; 583 /* LDOVBBMPU_FBB_VSET_OUT */ 584 ti,ldovbb-vset-mask = <0x1F>; 585 586 /* 587 * NOTE: only FBB mode used but actual vset will 588 * determine final biasing 589 */ 590 ti,abb_info = < 591 /*uV ABB efuse rbb_m fbb_m vset_m*/ 592 1060000 0 0x0 0 0x02000000 0x01F00000 593 1160000 0 0x4 0 0x02000000 0x01F00000 594 1210000 0 0x8 0 0x02000000 0x01F00000 595 >; 596 }; 597 598 abb_ivahd: regulator-abb-ivahd { 599 compatible = "ti,abb-v3"; 600 regulator-name = "abb_ivahd"; 601 #address-cells = <0>; 602 #size-cells = <0>; 603 clocks = <&sys_clkin1>; 604 ti,settling-time = <50>; 605 ti,clock-cycles = <16>; 606 607 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 608 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 609 <0x4a002470 0x4>; 610 reg-names = "setup-address", "control-address", 611 "int-address", "efuse-address", 612 "ldo-address"; 613 ti,tranxdone-status-mask = <0x40000000>; 614 /* LDOVBBIVA_FBB_MUX_CTRL */ 615 ti,ldovbb-override-mask = <0x400>; 616 /* LDOVBBIVA_FBB_VSET_OUT */ 617 ti,ldovbb-vset-mask = <0x1F>; 618 619 /* 620 * NOTE: only FBB mode used but actual vset will 621 * determine final biasing 622 */ 623 ti,abb_info = < 624 /*uV ABB efuse rbb_m fbb_m vset_m*/ 625 1055000 0 0x0 0 0x02000000 0x01F00000 626 1150000 0 0x4 0 0x02000000 0x01F00000 627 1250000 0 0x8 0 0x02000000 0x01F00000 628 >; 629 }; 630 631 abb_dspeve: regulator-abb-dspeve { 632 compatible = "ti,abb-v3"; 633 regulator-name = "abb_dspeve"; 634 #address-cells = <0>; 635 #size-cells = <0>; 636 clocks = <&sys_clkin1>; 637 ti,settling-time = <50>; 638 ti,clock-cycles = <16>; 639 640 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 641 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 642 <0x4a00246c 0x4>; 643 reg-names = "setup-address", "control-address", 644 "int-address", "efuse-address", 645 "ldo-address"; 646 ti,tranxdone-status-mask = <0x20000000>; 647 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 648 ti,ldovbb-override-mask = <0x400>; 649 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 650 ti,ldovbb-vset-mask = <0x1F>; 651 652 /* 653 * NOTE: only FBB mode used but actual vset will 654 * determine final biasing 655 */ 656 ti,abb_info = < 657 /*uV ABB efuse rbb_m fbb_m vset_m*/ 658 1055000 0 0x0 0 0x02000000 0x01F00000 659 1150000 0 0x4 0 0x02000000 0x01F00000 660 1250000 0 0x8 0 0x02000000 0x01F00000 661 >; 662 }; 663 664 abb_gpu: regulator-abb-gpu { 665 compatible = "ti,abb-v3"; 666 regulator-name = "abb_gpu"; 667 #address-cells = <0>; 668 #size-cells = <0>; 669 clocks = <&sys_clkin1>; 670 ti,settling-time = <50>; 671 ti,clock-cycles = <16>; 672 673 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 674 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 675 <0x4ae0c154 0x4>; 676 reg-names = "setup-address", "control-address", 677 "int-address", "efuse-address", 678 "ldo-address"; 679 ti,tranxdone-status-mask = <0x10000000>; 680 /* LDOVBBGPU_FBB_MUX_CTRL */ 681 ti,ldovbb-override-mask = <0x400>; 682 /* LDOVBBGPU_FBB_VSET_OUT */ 683 ti,ldovbb-vset-mask = <0x1F>; 684 685 /* 686 * NOTE: only FBB mode used but actual vset will 687 * determine final biasing 688 */ 689 ti,abb_info = < 690 /*uV ABB efuse rbb_m fbb_m vset_m*/ 691 1090000 0 0x0 0 0x02000000 0x01F00000 692 1210000 0 0x4 0 0x02000000 0x01F00000 693 1280000 0 0x8 0 0x02000000 0x01F00000 694 >; 695 }; 696 697 qspi: spi@4b300000 { 698 compatible = "ti,dra7xxx-qspi"; 699 reg = <0x4b300000 0x100>, 700 <0x5c000000 0x4000000>; 701 reg-names = "qspi_base", "qspi_mmap"; 702 syscon-chipselects = <&scm_conf 0x558>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 ti,hwmods = "qspi"; 706 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; 707 clock-names = "fck"; 708 num-cs = <4>; 709 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 710 status = "disabled"; 711 }; 712 713 /* OCP2SCP3 */ 714 sata: sata@4a141100 { 715 compatible = "snps,dwc-ahci"; 716 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 717 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 718 phys = <&sata_phy>; 719 phy-names = "sata-phy"; 720 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 721 ti,hwmods = "sata"; 722 ports-implemented = <0x1>; 723 }; 724 725 /* OCP2SCP1 */ 726 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 727 gpmc: gpmc@50000000 { 728 compatible = "ti,am3352-gpmc"; 729 ti,hwmods = "gpmc"; 730 reg = <0x50000000 0x37c>; /* device IO registers */ 731 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 732 dmas = <&edma_xbar 4 0>; 733 dma-names = "rxtx"; 734 gpmc,num-cs = <8>; 735 gpmc,num-waitpins = <2>; 736 #address-cells = <2>; 737 #size-cells = <1>; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 gpio-controller; 741 #gpio-cells = <2>; 742 status = "disabled"; 743 }; 744 745 target-module@56000000 { 746 compatible = "ti,sysc-omap4", "ti,sysc"; 747 reg = <0x5600fe00 0x4>, 748 <0x5600fe10 0x4>; 749 reg-names = "rev", "sysc"; 750 ti,sysc-midle = <SYSC_IDLE_FORCE>, 751 <SYSC_IDLE_NO>, 752 <SYSC_IDLE_SMART>; 753 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 754 <SYSC_IDLE_NO>, 755 <SYSC_IDLE_SMART>; 756 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; 757 clock-names = "fck"; 758 #address-cells = <1>; 759 #size-cells = <1>; 760 ranges = <0 0x56000000 0x2000000>; 761 }; 762 763 crossbar_mpu: crossbar@4a002a48 { 764 compatible = "ti,irq-crossbar"; 765 reg = <0x4a002a48 0x130>; 766 interrupt-controller; 767 interrupt-parent = <&wakeupgen>; 768 #interrupt-cells = <3>; 769 ti,max-irqs = <160>; 770 ti,max-crossbar-sources = <MAX_SOURCES>; 771 ti,reg-size = <2>; 772 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 773 ti,irqs-skip = <10 133 139 140>; 774 ti,irqs-safe-map = <0>; 775 }; 776 777 target-module@58000000 { 778 compatible = "ti,sysc-omap2", "ti,sysc"; 779 reg = <0x58000000 4>, 780 <0x58000014 4>; 781 reg-names = "rev", "syss"; 782 ti,syss-mask = <1>; 783 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, 784 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 785 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, 786 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; 787 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 788 #address-cells = <1>; 789 #size-cells = <1>; 790 ranges = <0 0x58000000 0x800000>; 791 792 dss: dss@0 { 793 compatible = "ti,dra7-dss"; 794 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 795 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 796 status = "disabled"; 797 /* CTRL_CORE_DSS_PLL_CONTROL */ 798 syscon-pll-ctrl = <&scm_conf 0x538>; 799 #address-cells = <1>; 800 #size-cells = <1>; 801 ranges = <0 0 0x800000>; 802 803 target-module@1000 { 804 compatible = "ti,sysc-omap2", "ti,sysc"; 805 reg = <0x1000 0x4>, 806 <0x1010 0x4>, 807 <0x1014 0x4>; 808 reg-names = "rev", "sysc", "syss"; 809 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 810 <SYSC_IDLE_NO>, 811 <SYSC_IDLE_SMART>; 812 ti,sysc-midle = <SYSC_IDLE_FORCE>, 813 <SYSC_IDLE_NO>, 814 <SYSC_IDLE_SMART>; 815 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 816 SYSC_OMAP2_ENAWAKEUP | 817 SYSC_OMAP2_SOFTRESET | 818 SYSC_OMAP2_AUTOIDLE)>; 819 ti,syss-mask = <1>; 820 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 821 clock-names = "fck"; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 ranges = <0 0x1000 0x1000>; 825 826 dispc@0 { 827 compatible = "ti,dra7-dispc"; 828 reg = <0 0x1000>; 829 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 831 clock-names = "fck"; 832 /* CTRL_CORE_SMA_SW_1 */ 833 syscon-pol = <&scm_conf 0x534>; 834 }; 835 }; 836 837 target-module@40000 { 838 compatible = "ti,sysc-omap4", "ti,sysc"; 839 reg = <0x40000 0x4>, 840 <0x40010 0x4>; 841 reg-names = "rev", "sysc"; 842 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 843 <SYSC_IDLE_NO>, 844 <SYSC_IDLE_SMART>, 845 <SYSC_IDLE_SMART_WKUP>; 846 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 847 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 848 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 849 clock-names = "fck", "dss_clk"; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 ranges = <0 0x40000 0x40000>; 853 854 hdmi: encoder@0 { 855 compatible = "ti,dra7-hdmi"; 856 reg = <0 0x200>, 857 <0x200 0x80>, 858 <0x300 0x80>, 859 <0x20000 0x19000>; 860 reg-names = "wp", "pll", "phy", "core"; 861 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 862 status = "disabled"; 863 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 864 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; 865 clock-names = "fck", "sys_clk"; 866 dmas = <&sdma_xbar 76>; 867 dma-names = "audio_tx"; 868 }; 869 }; 870 }; 871 }; 872 873 aes1_target: target-module@4b500000 { 874 compatible = "ti,sysc-omap2", "ti,sysc"; 875 reg = <0x4b500080 0x4>, 876 <0x4b500084 0x4>, 877 <0x4b500088 0x4>; 878 reg-names = "rev", "sysc", "syss"; 879 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 880 SYSC_OMAP2_AUTOIDLE)>; 881 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 882 <SYSC_IDLE_NO>, 883 <SYSC_IDLE_SMART>, 884 <SYSC_IDLE_SMART_WKUP>; 885 ti,syss-mask = <1>; 886 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 887 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; 888 clock-names = "fck"; 889 #address-cells = <1>; 890 #size-cells = <1>; 891 ranges = <0x0 0x4b500000 0x1000>; 892 893 aes1: aes@0 { 894 compatible = "ti,omap4-aes"; 895 reg = <0 0xa0>; 896 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 897 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 898 dma-names = "tx", "rx"; 899 clocks = <&l3_iclk_div>; 900 clock-names = "fck"; 901 }; 902 }; 903 904 aes2_target: target-module@4b700000 { 905 compatible = "ti,sysc-omap2", "ti,sysc"; 906 reg = <0x4b700080 0x4>, 907 <0x4b700084 0x4>, 908 <0x4b700088 0x4>; 909 reg-names = "rev", "sysc", "syss"; 910 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 911 SYSC_OMAP2_AUTOIDLE)>; 912 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 913 <SYSC_IDLE_NO>, 914 <SYSC_IDLE_SMART>, 915 <SYSC_IDLE_SMART_WKUP>; 916 ti,syss-mask = <1>; 917 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 918 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; 919 clock-names = "fck"; 920 #address-cells = <1>; 921 #size-cells = <1>; 922 ranges = <0x0 0x4b700000 0x1000>; 923 924 aes2: aes@0 { 925 compatible = "ti,omap4-aes"; 926 reg = <0 0xa0>; 927 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 928 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 929 dma-names = "tx", "rx"; 930 clocks = <&l3_iclk_div>; 931 clock-names = "fck"; 932 }; 933 }; 934 935 sham_target: target-module@4b101000 { 936 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 937 reg = <0x4b101100 0x4>, 938 <0x4b101110 0x4>, 939 <0x4b101114 0x4>; 940 reg-names = "rev", "sysc", "syss"; 941 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 942 SYSC_OMAP2_AUTOIDLE)>; 943 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 944 <SYSC_IDLE_NO>, 945 <SYSC_IDLE_SMART>; 946 ti,syss-mask = <1>; 947 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 948 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; 949 clock-names = "fck"; 950 #address-cells = <1>; 951 #size-cells = <1>; 952 ranges = <0x0 0x4b101000 0x1000>; 953 954 sham: sham@0 { 955 compatible = "ti,omap5-sham"; 956 reg = <0 0x300>; 957 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 958 dmas = <&edma_xbar 119 0>; 959 dma-names = "rx"; 960 clocks = <&l3_iclk_div>; 961 clock-names = "fck"; 962 }; 963 }; 964 965 opp_supply_mpu: opp-supply@4a003b20 { 966 compatible = "ti,omap5-opp-supply"; 967 reg = <0x4a003b20 0xc>; 968 ti,efuse-settings = < 969 /* uV offset */ 970 1060000 0x0 971 1160000 0x4 972 1210000 0x8 973 >; 974 ti,absolute-max-voltage-uv = <1500000>; 975 }; 976 977 }; 978 979 thermal_zones: thermal-zones { 980 #include "omap4-cpu-thermal.dtsi" 981 #include "omap5-gpu-thermal.dtsi" 982 #include "omap5-core-thermal.dtsi" 983 #include "dra7-dspeve-thermal.dtsi" 984 #include "dra7-iva-thermal.dtsi" 985 }; 986 987}; 988 989&cpu_thermal { 990 polling-delay = <500>; /* milliseconds */ 991 coefficients = <0 2000>; 992}; 993 994&gpu_thermal { 995 coefficients = <0 2000>; 996}; 997 998&core_thermal { 999 coefficients = <0 2000>; 1000}; 1001 1002&dspeve_thermal { 1003 coefficients = <0 2000>; 1004}; 1005 1006&iva_thermal { 1007 coefficients = <0 2000>; 1008}; 1009 1010&cpu_crit { 1011 temperature = <120000>; /* milli Celsius */ 1012}; 1013 1014&core_crit { 1015 temperature = <120000>; /* milli Celsius */ 1016}; 1017 1018&gpu_crit { 1019 temperature = <120000>; /* milli Celsius */ 1020}; 1021 1022&dspeve_crit { 1023 temperature = <120000>; /* milli Celsius */ 1024}; 1025 1026&iva_crit { 1027 temperature = <120000>; /* milli Celsius */ 1028}; 1029 1030#include "dra7-l4.dtsi" 1031#include "dra7xx-clocks.dtsi" 1032 1033&prm { 1034 prm_dsp1: prm@400 { 1035 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1036 reg = <0x400 0x100>; 1037 #reset-cells = <1>; 1038 }; 1039 1040 prm_ipu: prm@500 { 1041 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1042 reg = <0x500 0x100>; 1043 #reset-cells = <1>; 1044 }; 1045 1046 prm_core: prm@700 { 1047 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1048 reg = <0x700 0x100>; 1049 #reset-cells = <1>; 1050 }; 1051 1052 prm_iva: prm@f00 { 1053 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1054 reg = <0xf00 0x100>; 1055 }; 1056 1057 prm_dsp2: prm@1b00 { 1058 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1059 reg = <0x1b00 0x40>; 1060 #reset-cells = <1>; 1061 }; 1062 1063 prm_eve1: prm@1b40 { 1064 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1065 reg = <0x1b40 0x40>; 1066 }; 1067 1068 prm_eve2: prm@1b80 { 1069 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1070 reg = <0x1b80 0x40>; 1071 }; 1072 1073 prm_eve3: prm@1bc0 { 1074 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1075 reg = <0x1bc0 0x40>; 1076 }; 1077 1078 prm_eve4: prm@1c00 { 1079 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1080 reg = <0x1c00 0x60>; 1081 }; 1082}; 1083 1084/* Preferred always-on timer for clockevent */ 1085&timer1_target { 1086 ti,no-reset-on-init; 1087 ti,no-idle; 1088 timer@0 { 1089 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; 1090 assigned-clock-parents = <&sys_32k_ck>; 1091 }; 1092}; 1093