1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2500"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&vic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &vuart; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm1176jzf-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x80000000 0>; 49 }; 50 51 ahb { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 fmc: spi@1e620000 { 58 reg = < 0x1e620000 0xc4 59 0x20000000 0x10000000 >; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 compatible = "aspeed,ast2500-fmc"; 63 clocks = <&syscon ASPEED_CLK_AHB>; 64 status = "disabled"; 65 interrupts = <19>; 66 flash@0 { 67 reg = < 0 >; 68 compatible = "jedec,spi-nor"; 69 spi-max-frequency = <50000000>; 70 status = "disabled"; 71 }; 72 flash@1 { 73 reg = < 1 >; 74 compatible = "jedec,spi-nor"; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-max-frequency = <50000000>; 82 status = "disabled"; 83 }; 84 }; 85 86 spi1: spi@1e630000 { 87 reg = < 0x1e630000 0xc4 88 0x30000000 0x08000000 >; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 compatible = "aspeed,ast2500-spi"; 92 clocks = <&syscon ASPEED_CLK_AHB>; 93 status = "disabled"; 94 flash@0 { 95 reg = < 0 >; 96 compatible = "jedec,spi-nor"; 97 spi-max-frequency = <50000000>; 98 status = "disabled"; 99 }; 100 flash@1 { 101 reg = < 1 >; 102 compatible = "jedec,spi-nor"; 103 spi-max-frequency = <50000000>; 104 status = "disabled"; 105 }; 106 }; 107 108 spi2: spi@1e631000 { 109 reg = < 0x1e631000 0xc4 110 0x38000000 0x08000000 >; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "aspeed,ast2500-spi"; 114 clocks = <&syscon ASPEED_CLK_AHB>; 115 status = "disabled"; 116 flash@0 { 117 reg = < 0 >; 118 compatible = "jedec,spi-nor"; 119 spi-max-frequency = <50000000>; 120 status = "disabled"; 121 }; 122 flash@1 { 123 reg = < 1 >; 124 compatible = "jedec,spi-nor"; 125 spi-max-frequency = <50000000>; 126 status = "disabled"; 127 }; 128 }; 129 130 vic: interrupt-controller@1e6c0080 { 131 compatible = "aspeed,ast2400-vic"; 132 interrupt-controller; 133 #interrupt-cells = <1>; 134 valid-sources = <0xfefff7ff 0x0807ffff>; 135 reg = <0x1e6c0080 0x80>; 136 }; 137 138 cvic: copro-interrupt-controller@1e6c2000 { 139 compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; 140 valid-sources = <0xffffffff>; 141 copro-sw-interrupts = <1>; 142 reg = <0x1e6c2000 0x80>; 143 }; 144 145 mac0: ethernet@1e660000 { 146 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 147 reg = <0x1e660000 0x180>; 148 interrupts = <2>; 149 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 150 status = "disabled"; 151 }; 152 153 mac1: ethernet@1e680000 { 154 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 155 reg = <0x1e680000 0x180>; 156 interrupts = <3>; 157 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 158 status = "disabled"; 159 }; 160 161 ehci0: usb@1e6a1000 { 162 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 163 reg = <0x1e6a1000 0x100>; 164 interrupts = <5>; 165 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_usb2ah_default>; 168 status = "disabled"; 169 }; 170 171 ehci1: usb@1e6a3000 { 172 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 173 reg = <0x1e6a3000 0x100>; 174 interrupts = <13>; 175 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_usb2bh_default>; 178 status = "disabled"; 179 }; 180 181 uhci: usb@1e6b0000 { 182 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 183 reg = <0x1e6b0000 0x100>; 184 interrupts = <14>; 185 #ports = <2>; 186 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 187 status = "disabled"; 188 /* 189 * No default pinmux, it will follow EHCI, use an explicit pinmux 190 * override if you don't enable EHCI 191 */ 192 }; 193 194 vhub: usb-vhub@1e6a0000 { 195 compatible = "aspeed,ast2500-usb-vhub"; 196 reg = <0x1e6a0000 0x300>; 197 interrupts = <5>; 198 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 199 aspeed,vhub-downstream-ports = <5>; 200 aspeed,vhub-generic-endpoints = <15>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_usb2ad_default>; 203 status = "disabled"; 204 }; 205 206 apb { 207 compatible = "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 edac: memory-controller@1e6e0000 { 213 compatible = "aspeed,ast2500-sdram-edac"; 214 reg = <0x1e6e0000 0x174>; 215 interrupts = <0>; 216 status = "disabled"; 217 }; 218 219 syscon: syscon@1e6e2000 { 220 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 221 reg = <0x1e6e2000 0x1a8>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1e6e2000 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 228 scu_ic: interrupt-controller@18 { 229 #interrupt-cells = <1>; 230 compatible = "aspeed,ast2500-scu-ic"; 231 reg = <0x18 0x4>; 232 interrupts = <21>; 233 interrupt-controller; 234 }; 235 236 p2a: p2a-control@2c { 237 compatible = "aspeed,ast2500-p2a-ctrl"; 238 reg = <0x2c 0x4>; 239 status = "disabled"; 240 }; 241 242 pinctrl: pinctrl@80 { 243 compatible = "aspeed,ast2500-pinctrl"; 244 reg = <0x80 0x18>, <0xa0 0x10>; 245 aspeed,external-nodes = <&gfx>, <&lhc>; 246 }; 247 }; 248 249 rng: hwrng@1e6e2078 { 250 compatible = "timeriomem_rng"; 251 reg = <0x1e6e2078 0x4>; 252 period = <1>; 253 quality = <100>; 254 }; 255 256 gfx: display@1e6e6000 { 257 compatible = "aspeed,ast2500-gfx", "syscon"; 258 reg = <0x1e6e6000 0x1000>; 259 reg-io-width = <4>; 260 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 261 resets = <&syscon ASPEED_RESET_CRT1>; 262 status = "disabled"; 263 interrupts = <0x19>; 264 }; 265 266 xdma: xdma@1e6e7000 { 267 compatible = "aspeed,ast2500-xdma"; 268 reg = <0x1e6e7000 0x100>; 269 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 270 resets = <&syscon ASPEED_RESET_XDMA>; 271 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; 272 aspeed,pcie-device = "bmc"; 273 aspeed,scu = <&syscon>; 274 status = "disabled"; 275 }; 276 277 adc: adc@1e6e9000 { 278 compatible = "aspeed,ast2500-adc"; 279 reg = <0x1e6e9000 0xb0>; 280 clocks = <&syscon ASPEED_CLK_APB>; 281 resets = <&syscon ASPEED_RESET_ADC>; 282 #io-channel-cells = <1>; 283 status = "disabled"; 284 }; 285 286 video: video@1e700000 { 287 compatible = "aspeed,ast2500-video-engine"; 288 reg = <0x1e700000 0x1000>; 289 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 290 <&syscon ASPEED_CLK_GATE_ECLK>; 291 clock-names = "vclk", "eclk"; 292 interrupts = <7>; 293 status = "disabled"; 294 }; 295 296 sram: sram@1e720000 { 297 compatible = "mmio-sram"; 298 reg = <0x1e720000 0x9000>; // 36K 299 }; 300 301 sdmmc: sd-controller@1e740000 { 302 compatible = "aspeed,ast2500-sd-controller"; 303 reg = <0x1e740000 0x100>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0x1e740000 0x10000>; 307 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 308 status = "disabled"; 309 310 sdhci0: sdhci@100 { 311 compatible = "aspeed,ast2500-sdhci"; 312 reg = <0x100 0x100>; 313 interrupts = <26>; 314 sdhci,auto-cmd12; 315 clocks = <&syscon ASPEED_CLK_SDIO>; 316 status = "disabled"; 317 }; 318 319 sdhci1: sdhci@200 { 320 compatible = "aspeed,ast2500-sdhci"; 321 reg = <0x200 0x100>; 322 interrupts = <26>; 323 sdhci,auto-cmd12; 324 clocks = <&syscon ASPEED_CLK_SDIO>; 325 status = "disabled"; 326 }; 327 }; 328 329 gpio: gpio@1e780000 { 330 #gpio-cells = <2>; 331 gpio-controller; 332 compatible = "aspeed,ast2500-gpio"; 333 reg = <0x1e780000 0x200>; 334 interrupts = <20>; 335 gpio-ranges = <&pinctrl 0 0 232>; 336 clocks = <&syscon ASPEED_CLK_APB>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 sgpio: sgpio@1e780200 { 342 #gpio-cells = <2>; 343 compatible = "aspeed,ast2500-sgpio"; 344 gpio-controller; 345 interrupts = <40>; 346 reg = <0x1e780200 0x0100>; 347 clocks = <&syscon ASPEED_CLK_APB>; 348 interrupt-controller; 349 ngpios = <8>; 350 bus-frequency = <12000000>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_sgpm_default>; 353 status = "disabled"; 354 }; 355 356 rtc: rtc@1e781000 { 357 compatible = "aspeed,ast2500-rtc"; 358 reg = <0x1e781000 0x18>; 359 status = "disabled"; 360 }; 361 362 timer: timer@1e782000 { 363 /* This timer is a Faraday FTTMR010 derivative */ 364 compatible = "aspeed,ast2400-timer"; 365 reg = <0x1e782000 0x90>; 366 interrupts = <16 17 18 35 36 37 38 39>; 367 clocks = <&syscon ASPEED_CLK_APB>; 368 clock-names = "PCLK"; 369 }; 370 371 uart1: serial@1e783000 { 372 compatible = "ns16550a"; 373 reg = <0x1e783000 0x20>; 374 reg-shift = <2>; 375 interrupts = <9>; 376 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 377 resets = <&lpc_reset 4>; 378 no-loopback-test; 379 status = "disabled"; 380 }; 381 382 uart5: serial@1e784000 { 383 compatible = "ns16550a"; 384 reg = <0x1e784000 0x20>; 385 reg-shift = <2>; 386 interrupts = <10>; 387 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 388 no-loopback-test; 389 status = "disabled"; 390 }; 391 392 wdt1: watchdog@1e785000 { 393 compatible = "aspeed,ast2500-wdt"; 394 reg = <0x1e785000 0x20>; 395 clocks = <&syscon ASPEED_CLK_APB>; 396 }; 397 398 wdt2: watchdog@1e785020 { 399 compatible = "aspeed,ast2500-wdt"; 400 reg = <0x1e785020 0x20>; 401 clocks = <&syscon ASPEED_CLK_APB>; 402 }; 403 404 wdt3: watchdog@1e785040 { 405 compatible = "aspeed,ast2500-wdt"; 406 reg = <0x1e785040 0x20>; 407 clocks = <&syscon ASPEED_CLK_APB>; 408 status = "disabled"; 409 }; 410 411 pwm_tacho: pwm-tacho-controller@1e786000 { 412 compatible = "aspeed,ast2500-pwm-tacho"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0x1e786000 0x1000>; 416 clocks = <&syscon ASPEED_CLK_24M>; 417 resets = <&syscon ASPEED_RESET_PWM>; 418 status = "disabled"; 419 }; 420 421 vuart: serial@1e787000 { 422 compatible = "aspeed,ast2500-vuart"; 423 reg = <0x1e787000 0x40>; 424 reg-shift = <2>; 425 interrupts = <8>; 426 clocks = <&syscon ASPEED_CLK_APB>; 427 no-loopback-test; 428 status = "disabled"; 429 }; 430 431 lpc: lpc@1e789000 { 432 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 433 reg = <0x1e789000 0x1000>; 434 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges = <0x0 0x1e789000 0x1000>; 438 439 lpc_bmc: lpc-bmc@0 { 440 compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; 441 reg = <0x0 0x80>; 442 reg-io-width = <4>; 443 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges = <0x0 0x0 0x80>; 447 448 kcs1: kcs@24 { 449 compatible = "aspeed,ast2500-kcs-bmc-v2"; 450 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 451 interrupts = <8>; 452 status = "disabled"; 453 }; 454 kcs2: kcs@28 { 455 compatible = "aspeed,ast2500-kcs-bmc-v2"; 456 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 457 interrupts = <8>; 458 status = "disabled"; 459 }; 460 kcs3: kcs@2c { 461 compatible = "aspeed,ast2500-kcs-bmc-v2"; 462 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 463 interrupts = <8>; 464 status = "disabled"; 465 }; 466 }; 467 468 lpc_host: lpc-host@80 { 469 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 470 reg = <0x80 0x1e0>; 471 reg-io-width = <4>; 472 473 #address-cells = <1>; 474 #size-cells = <1>; 475 ranges = <0x0 0x80 0x1e0>; 476 477 kcs4: kcs@94 { 478 compatible = "aspeed,ast2500-kcs-bmc-v2"; 479 reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; 480 interrupts = <8>; 481 status = "disabled"; 482 }; 483 484 lpc_ctrl: lpc-ctrl@0 { 485 compatible = "aspeed,ast2500-lpc-ctrl"; 486 reg = <0x0 0x10>; 487 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 488 status = "disabled"; 489 }; 490 491 lpc_snoop: lpc-snoop@10 { 492 compatible = "aspeed,ast2500-lpc-snoop"; 493 reg = <0x10 0x8>; 494 interrupts = <8>; 495 status = "disabled"; 496 }; 497 498 lpc_reset: reset-controller@18 { 499 compatible = "aspeed,ast2500-lpc-reset"; 500 reg = <0x18 0x4>; 501 #reset-cells = <1>; 502 }; 503 504 lhc: lhc@20 { 505 compatible = "aspeed,ast2500-lhc"; 506 reg = <0x20 0x24 0x48 0x8>; 507 }; 508 509 510 ibt: ibt@c0 { 511 compatible = "aspeed,ast2500-ibt-bmc"; 512 reg = <0xc0 0x18>; 513 interrupts = <8>; 514 status = "disabled"; 515 }; 516 }; 517 }; 518 519 uart2: serial@1e78d000 { 520 compatible = "ns16550a"; 521 reg = <0x1e78d000 0x20>; 522 reg-shift = <2>; 523 interrupts = <32>; 524 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 525 resets = <&lpc_reset 5>; 526 no-loopback-test; 527 status = "disabled"; 528 }; 529 530 uart3: serial@1e78e000 { 531 compatible = "ns16550a"; 532 reg = <0x1e78e000 0x20>; 533 reg-shift = <2>; 534 interrupts = <33>; 535 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 536 resets = <&lpc_reset 6>; 537 no-loopback-test; 538 status = "disabled"; 539 }; 540 541 uart4: serial@1e78f000 { 542 compatible = "ns16550a"; 543 reg = <0x1e78f000 0x20>; 544 reg-shift = <2>; 545 interrupts = <34>; 546 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 547 resets = <&lpc_reset 7>; 548 no-loopback-test; 549 status = "disabled"; 550 }; 551 552 i2c: bus@1e78a000 { 553 compatible = "simple-bus"; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges = <0 0x1e78a000 0x1000>; 557 }; 558 }; 559 }; 560}; 561 562&i2c { 563 i2c_ic: interrupt-controller@0 { 564 #interrupt-cells = <1>; 565 compatible = "aspeed,ast2500-i2c-ic"; 566 reg = <0x0 0x40>; 567 interrupts = <12>; 568 interrupt-controller; 569 }; 570 571 i2c0: i2c-bus@40 { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 #interrupt-cells = <1>; 575 576 reg = <0x40 0x40>; 577 compatible = "aspeed,ast2500-i2c-bus"; 578 clocks = <&syscon ASPEED_CLK_APB>; 579 resets = <&syscon ASPEED_RESET_I2C>; 580 bus-frequency = <100000>; 581 interrupts = <0>; 582 interrupt-parent = <&i2c_ic>; 583 status = "disabled"; 584 /* Does not need pinctrl properties */ 585 }; 586 587 i2c1: i2c-bus@80 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 #interrupt-cells = <1>; 591 592 reg = <0x80 0x40>; 593 compatible = "aspeed,ast2500-i2c-bus"; 594 clocks = <&syscon ASPEED_CLK_APB>; 595 resets = <&syscon ASPEED_RESET_I2C>; 596 bus-frequency = <100000>; 597 interrupts = <1>; 598 interrupt-parent = <&i2c_ic>; 599 status = "disabled"; 600 /* Does not need pinctrl properties */ 601 }; 602 603 i2c2: i2c-bus@c0 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 #interrupt-cells = <1>; 607 608 reg = <0xc0 0x40>; 609 compatible = "aspeed,ast2500-i2c-bus"; 610 clocks = <&syscon ASPEED_CLK_APB>; 611 resets = <&syscon ASPEED_RESET_I2C>; 612 bus-frequency = <100000>; 613 interrupts = <2>; 614 interrupt-parent = <&i2c_ic>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pinctrl_i2c3_default>; 617 status = "disabled"; 618 }; 619 620 i2c3: i2c-bus@100 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 #interrupt-cells = <1>; 624 625 reg = <0x100 0x40>; 626 compatible = "aspeed,ast2500-i2c-bus"; 627 clocks = <&syscon ASPEED_CLK_APB>; 628 resets = <&syscon ASPEED_RESET_I2C>; 629 bus-frequency = <100000>; 630 interrupts = <3>; 631 interrupt-parent = <&i2c_ic>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_i2c4_default>; 634 status = "disabled"; 635 }; 636 637 i2c4: i2c-bus@140 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 #interrupt-cells = <1>; 641 642 reg = <0x140 0x40>; 643 compatible = "aspeed,ast2500-i2c-bus"; 644 clocks = <&syscon ASPEED_CLK_APB>; 645 resets = <&syscon ASPEED_RESET_I2C>; 646 bus-frequency = <100000>; 647 interrupts = <4>; 648 interrupt-parent = <&i2c_ic>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_i2c5_default>; 651 status = "disabled"; 652 }; 653 654 i2c5: i2c-bus@180 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 #interrupt-cells = <1>; 658 659 reg = <0x180 0x40>; 660 compatible = "aspeed,ast2500-i2c-bus"; 661 clocks = <&syscon ASPEED_CLK_APB>; 662 resets = <&syscon ASPEED_RESET_I2C>; 663 bus-frequency = <100000>; 664 interrupts = <5>; 665 interrupt-parent = <&i2c_ic>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_i2c6_default>; 668 status = "disabled"; 669 }; 670 671 i2c6: i2c-bus@1c0 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #interrupt-cells = <1>; 675 676 reg = <0x1c0 0x40>; 677 compatible = "aspeed,ast2500-i2c-bus"; 678 clocks = <&syscon ASPEED_CLK_APB>; 679 resets = <&syscon ASPEED_RESET_I2C>; 680 bus-frequency = <100000>; 681 interrupts = <6>; 682 interrupt-parent = <&i2c_ic>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_i2c7_default>; 685 status = "disabled"; 686 }; 687 688 i2c7: i2c-bus@300 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 #interrupt-cells = <1>; 692 693 reg = <0x300 0x40>; 694 compatible = "aspeed,ast2500-i2c-bus"; 695 clocks = <&syscon ASPEED_CLK_APB>; 696 resets = <&syscon ASPEED_RESET_I2C>; 697 bus-frequency = <100000>; 698 interrupts = <7>; 699 interrupt-parent = <&i2c_ic>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_i2c8_default>; 702 status = "disabled"; 703 }; 704 705 i2c8: i2c-bus@340 { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 #interrupt-cells = <1>; 709 710 reg = <0x340 0x40>; 711 compatible = "aspeed,ast2500-i2c-bus"; 712 clocks = <&syscon ASPEED_CLK_APB>; 713 resets = <&syscon ASPEED_RESET_I2C>; 714 bus-frequency = <100000>; 715 interrupts = <8>; 716 interrupt-parent = <&i2c_ic>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pinctrl_i2c9_default>; 719 status = "disabled"; 720 }; 721 722 i2c9: i2c-bus@380 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 #interrupt-cells = <1>; 726 727 reg = <0x380 0x40>; 728 compatible = "aspeed,ast2500-i2c-bus"; 729 clocks = <&syscon ASPEED_CLK_APB>; 730 resets = <&syscon ASPEED_RESET_I2C>; 731 bus-frequency = <100000>; 732 interrupts = <9>; 733 interrupt-parent = <&i2c_ic>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&pinctrl_i2c10_default>; 736 status = "disabled"; 737 }; 738 739 i2c10: i2c-bus@3c0 { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 #interrupt-cells = <1>; 743 744 reg = <0x3c0 0x40>; 745 compatible = "aspeed,ast2500-i2c-bus"; 746 clocks = <&syscon ASPEED_CLK_APB>; 747 resets = <&syscon ASPEED_RESET_I2C>; 748 bus-frequency = <100000>; 749 interrupts = <10>; 750 interrupt-parent = <&i2c_ic>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_i2c11_default>; 753 status = "disabled"; 754 }; 755 756 i2c11: i2c-bus@400 { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 #interrupt-cells = <1>; 760 761 reg = <0x400 0x40>; 762 compatible = "aspeed,ast2500-i2c-bus"; 763 clocks = <&syscon ASPEED_CLK_APB>; 764 resets = <&syscon ASPEED_RESET_I2C>; 765 bus-frequency = <100000>; 766 interrupts = <11>; 767 interrupt-parent = <&i2c_ic>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&pinctrl_i2c12_default>; 770 status = "disabled"; 771 }; 772 773 i2c12: i2c-bus@440 { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 #interrupt-cells = <1>; 777 778 reg = <0x440 0x40>; 779 compatible = "aspeed,ast2500-i2c-bus"; 780 clocks = <&syscon ASPEED_CLK_APB>; 781 resets = <&syscon ASPEED_RESET_I2C>; 782 bus-frequency = <100000>; 783 interrupts = <12>; 784 interrupt-parent = <&i2c_ic>; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&pinctrl_i2c13_default>; 787 status = "disabled"; 788 }; 789 790 i2c13: i2c-bus@480 { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 #interrupt-cells = <1>; 794 795 reg = <0x480 0x40>; 796 compatible = "aspeed,ast2500-i2c-bus"; 797 clocks = <&syscon ASPEED_CLK_APB>; 798 resets = <&syscon ASPEED_RESET_I2C>; 799 bus-frequency = <100000>; 800 interrupts = <13>; 801 interrupt-parent = <&i2c_ic>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&pinctrl_i2c14_default>; 804 status = "disabled"; 805 }; 806}; 807 808&pinctrl { 809 pinctrl_acpi_default: acpi_default { 810 function = "ACPI"; 811 groups = "ACPI"; 812 }; 813 814 pinctrl_adc0_default: adc0_default { 815 function = "ADC0"; 816 groups = "ADC0"; 817 }; 818 819 pinctrl_adc1_default: adc1_default { 820 function = "ADC1"; 821 groups = "ADC1"; 822 }; 823 824 pinctrl_adc10_default: adc10_default { 825 function = "ADC10"; 826 groups = "ADC10"; 827 }; 828 829 pinctrl_adc11_default: adc11_default { 830 function = "ADC11"; 831 groups = "ADC11"; 832 }; 833 834 pinctrl_adc12_default: adc12_default { 835 function = "ADC12"; 836 groups = "ADC12"; 837 }; 838 839 pinctrl_adc13_default: adc13_default { 840 function = "ADC13"; 841 groups = "ADC13"; 842 }; 843 844 pinctrl_adc14_default: adc14_default { 845 function = "ADC14"; 846 groups = "ADC14"; 847 }; 848 849 pinctrl_adc15_default: adc15_default { 850 function = "ADC15"; 851 groups = "ADC15"; 852 }; 853 854 pinctrl_adc2_default: adc2_default { 855 function = "ADC2"; 856 groups = "ADC2"; 857 }; 858 859 pinctrl_adc3_default: adc3_default { 860 function = "ADC3"; 861 groups = "ADC3"; 862 }; 863 864 pinctrl_adc4_default: adc4_default { 865 function = "ADC4"; 866 groups = "ADC4"; 867 }; 868 869 pinctrl_adc5_default: adc5_default { 870 function = "ADC5"; 871 groups = "ADC5"; 872 }; 873 874 pinctrl_adc6_default: adc6_default { 875 function = "ADC6"; 876 groups = "ADC6"; 877 }; 878 879 pinctrl_adc7_default: adc7_default { 880 function = "ADC7"; 881 groups = "ADC7"; 882 }; 883 884 pinctrl_adc8_default: adc8_default { 885 function = "ADC8"; 886 groups = "ADC8"; 887 }; 888 889 pinctrl_adc9_default: adc9_default { 890 function = "ADC9"; 891 groups = "ADC9"; 892 }; 893 894 pinctrl_bmcint_default: bmcint_default { 895 function = "BMCINT"; 896 groups = "BMCINT"; 897 }; 898 899 pinctrl_ddcclk_default: ddcclk_default { 900 function = "DDCCLK"; 901 groups = "DDCCLK"; 902 }; 903 904 pinctrl_ddcdat_default: ddcdat_default { 905 function = "DDCDAT"; 906 groups = "DDCDAT"; 907 }; 908 909 pinctrl_espi_default: espi_default { 910 function = "ESPI"; 911 groups = "ESPI"; 912 }; 913 914 pinctrl_fwspics1_default: fwspics1_default { 915 function = "FWSPICS1"; 916 groups = "FWSPICS1"; 917 }; 918 919 pinctrl_fwspics2_default: fwspics2_default { 920 function = "FWSPICS2"; 921 groups = "FWSPICS2"; 922 }; 923 924 pinctrl_gpid0_default: gpid0_default { 925 function = "GPID0"; 926 groups = "GPID0"; 927 }; 928 929 pinctrl_gpid2_default: gpid2_default { 930 function = "GPID2"; 931 groups = "GPID2"; 932 }; 933 934 pinctrl_gpid4_default: gpid4_default { 935 function = "GPID4"; 936 groups = "GPID4"; 937 }; 938 939 pinctrl_gpid6_default: gpid6_default { 940 function = "GPID6"; 941 groups = "GPID6"; 942 }; 943 944 pinctrl_gpie0_default: gpie0_default { 945 function = "GPIE0"; 946 groups = "GPIE0"; 947 }; 948 949 pinctrl_gpie2_default: gpie2_default { 950 function = "GPIE2"; 951 groups = "GPIE2"; 952 }; 953 954 pinctrl_gpie4_default: gpie4_default { 955 function = "GPIE4"; 956 groups = "GPIE4"; 957 }; 958 959 pinctrl_gpie6_default: gpie6_default { 960 function = "GPIE6"; 961 groups = "GPIE6"; 962 }; 963 964 pinctrl_i2c10_default: i2c10_default { 965 function = "I2C10"; 966 groups = "I2C10"; 967 }; 968 969 pinctrl_i2c11_default: i2c11_default { 970 function = "I2C11"; 971 groups = "I2C11"; 972 }; 973 974 pinctrl_i2c12_default: i2c12_default { 975 function = "I2C12"; 976 groups = "I2C12"; 977 }; 978 979 pinctrl_i2c13_default: i2c13_default { 980 function = "I2C13"; 981 groups = "I2C13"; 982 }; 983 984 pinctrl_i2c14_default: i2c14_default { 985 function = "I2C14"; 986 groups = "I2C14"; 987 }; 988 989 pinctrl_i2c3_default: i2c3_default { 990 function = "I2C3"; 991 groups = "I2C3"; 992 }; 993 994 pinctrl_i2c4_default: i2c4_default { 995 function = "I2C4"; 996 groups = "I2C4"; 997 }; 998 999 pinctrl_i2c5_default: i2c5_default { 1000 function = "I2C5"; 1001 groups = "I2C5"; 1002 }; 1003 1004 pinctrl_i2c6_default: i2c6_default { 1005 function = "I2C6"; 1006 groups = "I2C6"; 1007 }; 1008 1009 pinctrl_i2c7_default: i2c7_default { 1010 function = "I2C7"; 1011 groups = "I2C7"; 1012 }; 1013 1014 pinctrl_i2c8_default: i2c8_default { 1015 function = "I2C8"; 1016 groups = "I2C8"; 1017 }; 1018 1019 pinctrl_i2c9_default: i2c9_default { 1020 function = "I2C9"; 1021 groups = "I2C9"; 1022 }; 1023 1024 pinctrl_lad0_default: lad0_default { 1025 function = "LAD0"; 1026 groups = "LAD0"; 1027 }; 1028 1029 pinctrl_lad1_default: lad1_default { 1030 function = "LAD1"; 1031 groups = "LAD1"; 1032 }; 1033 1034 pinctrl_lad2_default: lad2_default { 1035 function = "LAD2"; 1036 groups = "LAD2"; 1037 }; 1038 1039 pinctrl_lad3_default: lad3_default { 1040 function = "LAD3"; 1041 groups = "LAD3"; 1042 }; 1043 1044 pinctrl_lclk_default: lclk_default { 1045 function = "LCLK"; 1046 groups = "LCLK"; 1047 }; 1048 1049 pinctrl_lframe_default: lframe_default { 1050 function = "LFRAME"; 1051 groups = "LFRAME"; 1052 }; 1053 1054 pinctrl_lpchc_default: lpchc_default { 1055 function = "LPCHC"; 1056 groups = "LPCHC"; 1057 }; 1058 1059 pinctrl_lpcpd_default: lpcpd_default { 1060 function = "LPCPD"; 1061 groups = "LPCPD"; 1062 }; 1063 1064 pinctrl_lpcplus_default: lpcplus_default { 1065 function = "LPCPLUS"; 1066 groups = "LPCPLUS"; 1067 }; 1068 1069 pinctrl_lpcpme_default: lpcpme_default { 1070 function = "LPCPME"; 1071 groups = "LPCPME"; 1072 }; 1073 1074 pinctrl_lpcrst_default: lpcrst_default { 1075 function = "LPCRST"; 1076 groups = "LPCRST"; 1077 }; 1078 1079 pinctrl_lpcsmi_default: lpcsmi_default { 1080 function = "LPCSMI"; 1081 groups = "LPCSMI"; 1082 }; 1083 1084 pinctrl_lsirq_default: lsirq_default { 1085 function = "LSIRQ"; 1086 groups = "LSIRQ"; 1087 }; 1088 1089 pinctrl_mac1link_default: mac1link_default { 1090 function = "MAC1LINK"; 1091 groups = "MAC1LINK"; 1092 }; 1093 1094 pinctrl_mac2link_default: mac2link_default { 1095 function = "MAC2LINK"; 1096 groups = "MAC2LINK"; 1097 }; 1098 1099 pinctrl_mdio1_default: mdio1_default { 1100 function = "MDIO1"; 1101 groups = "MDIO1"; 1102 }; 1103 1104 pinctrl_mdio2_default: mdio2_default { 1105 function = "MDIO2"; 1106 groups = "MDIO2"; 1107 }; 1108 1109 pinctrl_ncts1_default: ncts1_default { 1110 function = "NCTS1"; 1111 groups = "NCTS1"; 1112 }; 1113 1114 pinctrl_ncts2_default: ncts2_default { 1115 function = "NCTS2"; 1116 groups = "NCTS2"; 1117 }; 1118 1119 pinctrl_ncts3_default: ncts3_default { 1120 function = "NCTS3"; 1121 groups = "NCTS3"; 1122 }; 1123 1124 pinctrl_ncts4_default: ncts4_default { 1125 function = "NCTS4"; 1126 groups = "NCTS4"; 1127 }; 1128 1129 pinctrl_ndcd1_default: ndcd1_default { 1130 function = "NDCD1"; 1131 groups = "NDCD1"; 1132 }; 1133 1134 pinctrl_ndcd2_default: ndcd2_default { 1135 function = "NDCD2"; 1136 groups = "NDCD2"; 1137 }; 1138 1139 pinctrl_ndcd3_default: ndcd3_default { 1140 function = "NDCD3"; 1141 groups = "NDCD3"; 1142 }; 1143 1144 pinctrl_ndcd4_default: ndcd4_default { 1145 function = "NDCD4"; 1146 groups = "NDCD4"; 1147 }; 1148 1149 pinctrl_ndsr1_default: ndsr1_default { 1150 function = "NDSR1"; 1151 groups = "NDSR1"; 1152 }; 1153 1154 pinctrl_ndsr2_default: ndsr2_default { 1155 function = "NDSR2"; 1156 groups = "NDSR2"; 1157 }; 1158 1159 pinctrl_ndsr3_default: ndsr3_default { 1160 function = "NDSR3"; 1161 groups = "NDSR3"; 1162 }; 1163 1164 pinctrl_ndsr4_default: ndsr4_default { 1165 function = "NDSR4"; 1166 groups = "NDSR4"; 1167 }; 1168 1169 pinctrl_ndtr1_default: ndtr1_default { 1170 function = "NDTR1"; 1171 groups = "NDTR1"; 1172 }; 1173 1174 pinctrl_ndtr2_default: ndtr2_default { 1175 function = "NDTR2"; 1176 groups = "NDTR2"; 1177 }; 1178 1179 pinctrl_ndtr3_default: ndtr3_default { 1180 function = "NDTR3"; 1181 groups = "NDTR3"; 1182 }; 1183 1184 pinctrl_ndtr4_default: ndtr4_default { 1185 function = "NDTR4"; 1186 groups = "NDTR4"; 1187 }; 1188 1189 pinctrl_nri1_default: nri1_default { 1190 function = "NRI1"; 1191 groups = "NRI1"; 1192 }; 1193 1194 pinctrl_nri2_default: nri2_default { 1195 function = "NRI2"; 1196 groups = "NRI2"; 1197 }; 1198 1199 pinctrl_nri3_default: nri3_default { 1200 function = "NRI3"; 1201 groups = "NRI3"; 1202 }; 1203 1204 pinctrl_nri4_default: nri4_default { 1205 function = "NRI4"; 1206 groups = "NRI4"; 1207 }; 1208 1209 pinctrl_nrts1_default: nrts1_default { 1210 function = "NRTS1"; 1211 groups = "NRTS1"; 1212 }; 1213 1214 pinctrl_nrts2_default: nrts2_default { 1215 function = "NRTS2"; 1216 groups = "NRTS2"; 1217 }; 1218 1219 pinctrl_nrts3_default: nrts3_default { 1220 function = "NRTS3"; 1221 groups = "NRTS3"; 1222 }; 1223 1224 pinctrl_nrts4_default: nrts4_default { 1225 function = "NRTS4"; 1226 groups = "NRTS4"; 1227 }; 1228 1229 pinctrl_oscclk_default: oscclk_default { 1230 function = "OSCCLK"; 1231 groups = "OSCCLK"; 1232 }; 1233 1234 pinctrl_pewake_default: pewake_default { 1235 function = "PEWAKE"; 1236 groups = "PEWAKE"; 1237 }; 1238 1239 pinctrl_pnor_default: pnor_default { 1240 function = "PNOR"; 1241 groups = "PNOR"; 1242 }; 1243 1244 pinctrl_pwm0_default: pwm0_default { 1245 function = "PWM0"; 1246 groups = "PWM0"; 1247 }; 1248 1249 pinctrl_pwm1_default: pwm1_default { 1250 function = "PWM1"; 1251 groups = "PWM1"; 1252 }; 1253 1254 pinctrl_pwm2_default: pwm2_default { 1255 function = "PWM2"; 1256 groups = "PWM2"; 1257 }; 1258 1259 pinctrl_pwm3_default: pwm3_default { 1260 function = "PWM3"; 1261 groups = "PWM3"; 1262 }; 1263 1264 pinctrl_pwm4_default: pwm4_default { 1265 function = "PWM4"; 1266 groups = "PWM4"; 1267 }; 1268 1269 pinctrl_pwm5_default: pwm5_default { 1270 function = "PWM5"; 1271 groups = "PWM5"; 1272 }; 1273 1274 pinctrl_pwm6_default: pwm6_default { 1275 function = "PWM6"; 1276 groups = "PWM6"; 1277 }; 1278 1279 pinctrl_pwm7_default: pwm7_default { 1280 function = "PWM7"; 1281 groups = "PWM7"; 1282 }; 1283 1284 pinctrl_rgmii1_default: rgmii1_default { 1285 function = "RGMII1"; 1286 groups = "RGMII1"; 1287 }; 1288 1289 pinctrl_rgmii2_default: rgmii2_default { 1290 function = "RGMII2"; 1291 groups = "RGMII2"; 1292 }; 1293 1294 pinctrl_rmii1_default: rmii1_default { 1295 function = "RMII1"; 1296 groups = "RMII1"; 1297 }; 1298 1299 pinctrl_rmii2_default: rmii2_default { 1300 function = "RMII2"; 1301 groups = "RMII2"; 1302 }; 1303 1304 pinctrl_rxd1_default: rxd1_default { 1305 function = "RXD1"; 1306 groups = "RXD1"; 1307 }; 1308 1309 pinctrl_rxd2_default: rxd2_default { 1310 function = "RXD2"; 1311 groups = "RXD2"; 1312 }; 1313 1314 pinctrl_rxd3_default: rxd3_default { 1315 function = "RXD3"; 1316 groups = "RXD3"; 1317 }; 1318 1319 pinctrl_rxd4_default: rxd4_default { 1320 function = "RXD4"; 1321 groups = "RXD4"; 1322 }; 1323 1324 pinctrl_salt1_default: salt1_default { 1325 function = "SALT1"; 1326 groups = "SALT1"; 1327 }; 1328 1329 pinctrl_salt10_default: salt10_default { 1330 function = "SALT10"; 1331 groups = "SALT10"; 1332 }; 1333 1334 pinctrl_salt11_default: salt11_default { 1335 function = "SALT11"; 1336 groups = "SALT11"; 1337 }; 1338 1339 pinctrl_salt12_default: salt12_default { 1340 function = "SALT12"; 1341 groups = "SALT12"; 1342 }; 1343 1344 pinctrl_salt13_default: salt13_default { 1345 function = "SALT13"; 1346 groups = "SALT13"; 1347 }; 1348 1349 pinctrl_salt14_default: salt14_default { 1350 function = "SALT14"; 1351 groups = "SALT14"; 1352 }; 1353 1354 pinctrl_salt2_default: salt2_default { 1355 function = "SALT2"; 1356 groups = "SALT2"; 1357 }; 1358 1359 pinctrl_salt3_default: salt3_default { 1360 function = "SALT3"; 1361 groups = "SALT3"; 1362 }; 1363 1364 pinctrl_salt4_default: salt4_default { 1365 function = "SALT4"; 1366 groups = "SALT4"; 1367 }; 1368 1369 pinctrl_salt5_default: salt5_default { 1370 function = "SALT5"; 1371 groups = "SALT5"; 1372 }; 1373 1374 pinctrl_salt6_default: salt6_default { 1375 function = "SALT6"; 1376 groups = "SALT6"; 1377 }; 1378 1379 pinctrl_salt7_default: salt7_default { 1380 function = "SALT7"; 1381 groups = "SALT7"; 1382 }; 1383 1384 pinctrl_salt8_default: salt8_default { 1385 function = "SALT8"; 1386 groups = "SALT8"; 1387 }; 1388 1389 pinctrl_salt9_default: salt9_default { 1390 function = "SALT9"; 1391 groups = "SALT9"; 1392 }; 1393 1394 pinctrl_scl1_default: scl1_default { 1395 function = "SCL1"; 1396 groups = "SCL1"; 1397 }; 1398 1399 pinctrl_scl2_default: scl2_default { 1400 function = "SCL2"; 1401 groups = "SCL2"; 1402 }; 1403 1404 pinctrl_sd1_default: sd1_default { 1405 function = "SD1"; 1406 groups = "SD1"; 1407 }; 1408 1409 pinctrl_sd2_default: sd2_default { 1410 function = "SD2"; 1411 groups = "SD2"; 1412 }; 1413 1414 pinctrl_sda1_default: sda1_default { 1415 function = "SDA1"; 1416 groups = "SDA1"; 1417 }; 1418 1419 pinctrl_sda2_default: sda2_default { 1420 function = "SDA2"; 1421 groups = "SDA2"; 1422 }; 1423 1424 pinctrl_sgpm_default: sgpm_default { 1425 function = "SGPM"; 1426 groups = "SGPM"; 1427 }; 1428 1429 pinctrl_sgps1_default: sgps1_default { 1430 function = "SGPS1"; 1431 groups = "SGPS1"; 1432 }; 1433 1434 pinctrl_sgps2_default: sgps2_default { 1435 function = "SGPS2"; 1436 groups = "SGPS2"; 1437 }; 1438 1439 pinctrl_sioonctrl_default: sioonctrl_default { 1440 function = "SIOONCTRL"; 1441 groups = "SIOONCTRL"; 1442 }; 1443 1444 pinctrl_siopbi_default: siopbi_default { 1445 function = "SIOPBI"; 1446 groups = "SIOPBI"; 1447 }; 1448 1449 pinctrl_siopbo_default: siopbo_default { 1450 function = "SIOPBO"; 1451 groups = "SIOPBO"; 1452 }; 1453 1454 pinctrl_siopwreq_default: siopwreq_default { 1455 function = "SIOPWREQ"; 1456 groups = "SIOPWREQ"; 1457 }; 1458 1459 pinctrl_siopwrgd_default: siopwrgd_default { 1460 function = "SIOPWRGD"; 1461 groups = "SIOPWRGD"; 1462 }; 1463 1464 pinctrl_sios3_default: sios3_default { 1465 function = "SIOS3"; 1466 groups = "SIOS3"; 1467 }; 1468 1469 pinctrl_sios5_default: sios5_default { 1470 function = "SIOS5"; 1471 groups = "SIOS5"; 1472 }; 1473 1474 pinctrl_siosci_default: siosci_default { 1475 function = "SIOSCI"; 1476 groups = "SIOSCI"; 1477 }; 1478 1479 pinctrl_spi1_default: spi1_default { 1480 function = "SPI1"; 1481 groups = "SPI1"; 1482 }; 1483 1484 pinctrl_spi1cs1_default: spi1cs1_default { 1485 function = "SPI1CS1"; 1486 groups = "SPI1CS1"; 1487 }; 1488 1489 pinctrl_spi1debug_default: spi1debug_default { 1490 function = "SPI1DEBUG"; 1491 groups = "SPI1DEBUG"; 1492 }; 1493 1494 pinctrl_spi1passthru_default: spi1passthru_default { 1495 function = "SPI1PASSTHRU"; 1496 groups = "SPI1PASSTHRU"; 1497 }; 1498 1499 pinctrl_spi2ck_default: spi2ck_default { 1500 function = "SPI2CK"; 1501 groups = "SPI2CK"; 1502 }; 1503 1504 pinctrl_spi2cs0_default: spi2cs0_default { 1505 function = "SPI2CS0"; 1506 groups = "SPI2CS0"; 1507 }; 1508 1509 pinctrl_spi2cs1_default: spi2cs1_default { 1510 function = "SPI2CS1"; 1511 groups = "SPI2CS1"; 1512 }; 1513 1514 pinctrl_spi2miso_default: spi2miso_default { 1515 function = "SPI2MISO"; 1516 groups = "SPI2MISO"; 1517 }; 1518 1519 pinctrl_spi2mosi_default: spi2mosi_default { 1520 function = "SPI2MOSI"; 1521 groups = "SPI2MOSI"; 1522 }; 1523 1524 pinctrl_timer3_default: timer3_default { 1525 function = "TIMER3"; 1526 groups = "TIMER3"; 1527 }; 1528 1529 pinctrl_timer4_default: timer4_default { 1530 function = "TIMER4"; 1531 groups = "TIMER4"; 1532 }; 1533 1534 pinctrl_timer5_default: timer5_default { 1535 function = "TIMER5"; 1536 groups = "TIMER5"; 1537 }; 1538 1539 pinctrl_timer6_default: timer6_default { 1540 function = "TIMER6"; 1541 groups = "TIMER6"; 1542 }; 1543 1544 pinctrl_timer7_default: timer7_default { 1545 function = "TIMER7"; 1546 groups = "TIMER7"; 1547 }; 1548 1549 pinctrl_timer8_default: timer8_default { 1550 function = "TIMER8"; 1551 groups = "TIMER8"; 1552 }; 1553 1554 pinctrl_txd1_default: txd1_default { 1555 function = "TXD1"; 1556 groups = "TXD1"; 1557 }; 1558 1559 pinctrl_txd2_default: txd2_default { 1560 function = "TXD2"; 1561 groups = "TXD2"; 1562 }; 1563 1564 pinctrl_txd3_default: txd3_default { 1565 function = "TXD3"; 1566 groups = "TXD3"; 1567 }; 1568 1569 pinctrl_txd4_default: txd4_default { 1570 function = "TXD4"; 1571 groups = "TXD4"; 1572 }; 1573 1574 pinctrl_uart6_default: uart6_default { 1575 function = "UART6"; 1576 groups = "UART6"; 1577 }; 1578 1579 pinctrl_usbcki_default: usbcki_default { 1580 function = "USBCKI"; 1581 groups = "USBCKI"; 1582 }; 1583 1584 pinctrl_usb2ah_default: usb2ah_default { 1585 function = "USB2AH"; 1586 groups = "USB2AH"; 1587 }; 1588 1589 pinctrl_usb2ad_default: usb2ad_default { 1590 function = "USB2AD"; 1591 groups = "USB2AD"; 1592 }; 1593 1594 pinctrl_usb11bhid_default: usb11bhid_default { 1595 function = "USB11BHID"; 1596 groups = "USB11BHID"; 1597 }; 1598 1599 pinctrl_usb2bh_default: usb2bh_default { 1600 function = "USB2BH"; 1601 groups = "USB2BH"; 1602 }; 1603 1604 pinctrl_vgabiosrom_default: vgabiosrom_default { 1605 function = "VGABIOSROM"; 1606 groups = "VGABIOSROM"; 1607 }; 1608 1609 pinctrl_vgahs_default: vgahs_default { 1610 function = "VGAHS"; 1611 groups = "VGAHS"; 1612 }; 1613 1614 pinctrl_vgavs_default: vgavs_default { 1615 function = "VGAVS"; 1616 groups = "VGAVS"; 1617 }; 1618 1619 pinctrl_vpi24_default: vpi24_default { 1620 function = "VPI24"; 1621 groups = "VPI24"; 1622 }; 1623 1624 pinctrl_vpo_default: vpo_default { 1625 function = "VPO"; 1626 groups = "VPO"; 1627 }; 1628 1629 pinctrl_wdtrst1_default: wdtrst1_default { 1630 function = "WDTRST1"; 1631 groups = "WDTRST1"; 1632 }; 1633 1634 pinctrl_wdtrst2_default: wdtrst2_default { 1635 function = "WDTRST2"; 1636 groups = "WDTRST2"; 1637 }; 1638}; 1639