1 /* sound/soc/samsung/ac97.c
2  *
3  * ALSA SoC Audio Layer - S3C AC97 Controller driver
4  * 	Evolved from s3c2443-ac97.c
5  *
6  * Copyright (c) 2010 Samsung Electronics Co. Ltd
7  * 	Author: Jaswinder Singh <jassi.brar@samsung.com>
8  * 	Credits: Graeme Gregory, Sean Choi
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 
20 #include <sound/soc.h>
21 
22 #include <mach/dma.h>
23 #include <plat/regs-ac97.h>
24 #include <plat/audio.h>
25 
26 #include "dma.h"
27 
28 #define AC_CMD_ADDR(x) (x << 16)
29 #define AC_CMD_DATA(x) (x & 0xffff)
30 
31 #define S3C_AC97_DAI_PCM 0
32 #define S3C_AC97_DAI_MIC 1
33 
34 struct s3c_ac97_info {
35 	struct clk         *ac97_clk;
36 	void __iomem	   *regs;
37 	struct mutex       lock;
38 	struct completion  done;
39 };
40 static struct s3c_ac97_info s3c_ac97;
41 
42 static struct s3c2410_dma_client s3c_dma_client_out = {
43 	.name = "AC97 PCMOut"
44 };
45 
46 static struct s3c2410_dma_client s3c_dma_client_in = {
47 	.name = "AC97 PCMIn"
48 };
49 
50 static struct s3c2410_dma_client s3c_dma_client_micin = {
51 	.name = "AC97 MicIn"
52 };
53 
54 static struct s3c_dma_params s3c_ac97_pcm_out = {
55 	.client		= &s3c_dma_client_out,
56 	.dma_size	= 4,
57 };
58 
59 static struct s3c_dma_params s3c_ac97_pcm_in = {
60 	.client		= &s3c_dma_client_in,
61 	.dma_size	= 4,
62 };
63 
64 static struct s3c_dma_params s3c_ac97_mic_in = {
65 	.client		= &s3c_dma_client_micin,
66 	.dma_size	= 4,
67 };
68 
s3c_ac97_activate(struct snd_ac97 * ac97)69 static void s3c_ac97_activate(struct snd_ac97 *ac97)
70 {
71 	u32 ac_glbctrl, stat;
72 
73 	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
74 	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
75 		return; /* Return if already active */
76 
77 	INIT_COMPLETION(s3c_ac97.done);
78 
79 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80 	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
81 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
82 	msleep(1);
83 
84 	ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
85 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
86 	msleep(1);
87 
88 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89 	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
90 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91 
92 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
93 		pr_err("AC97: Unable to activate!");
94 }
95 
s3c_ac97_read(struct snd_ac97 * ac97,unsigned short reg)96 static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
97 	unsigned short reg)
98 {
99 	u32 ac_glbctrl, ac_codec_cmd;
100 	u32 stat, addr, data;
101 
102 	mutex_lock(&s3c_ac97.lock);
103 
104 	s3c_ac97_activate(ac97);
105 
106 	INIT_COMPLETION(s3c_ac97.done);
107 
108 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109 	ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
110 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
111 
112 	udelay(50);
113 
114 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115 	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
116 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117 
118 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
119 		pr_err("AC97: Unable to read!");
120 
121 	stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
122 	addr = (stat >> 16) & 0x7f;
123 	data = (stat & 0xffff);
124 
125 	if (addr != reg)
126 		pr_err("ac97: req addr = %02x, rep addr = %02x\n",
127 			reg, addr);
128 
129 	mutex_unlock(&s3c_ac97.lock);
130 
131 	return (unsigned short)data;
132 }
133 
s3c_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)134 static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
135 	unsigned short val)
136 {
137 	u32 ac_glbctrl, ac_codec_cmd;
138 
139 	mutex_lock(&s3c_ac97.lock);
140 
141 	s3c_ac97_activate(ac97);
142 
143 	INIT_COMPLETION(s3c_ac97.done);
144 
145 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
146 	ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
147 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
148 
149 	udelay(50);
150 
151 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
152 	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
153 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
154 
155 	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
156 		pr_err("AC97: Unable to write!");
157 
158 	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
159 	ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
160 	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
161 
162 	mutex_unlock(&s3c_ac97.lock);
163 }
164 
s3c_ac97_cold_reset(struct snd_ac97 * ac97)165 static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
166 {
167 	pr_debug("AC97: Cold reset\n");
168 	writel(S3C_AC97_GLBCTRL_COLDRESET,
169 			s3c_ac97.regs + S3C_AC97_GLBCTRL);
170 	msleep(1);
171 
172 	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
173 	msleep(1);
174 }
175 
s3c_ac97_warm_reset(struct snd_ac97 * ac97)176 static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
177 {
178 	u32 stat;
179 
180 	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
181 	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
182 		return; /* Return if already active */
183 
184 	pr_debug("AC97: Warm reset\n");
185 
186 	writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
187 	msleep(1);
188 
189 	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
190 	msleep(1);
191 
192 	s3c_ac97_activate(ac97);
193 }
194 
s3c_ac97_irq(int irq,void * dev_id)195 static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
196 {
197 	u32 ac_glbctrl, ac_glbstat;
198 
199 	ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
200 
201 	if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
202 
203 		ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
204 		ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
205 		writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
206 
207 		complete(&s3c_ac97.done);
208 	}
209 
210 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
211 	ac_glbctrl |= (1<<30); /* Clear interrupt */
212 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
213 
214 	return IRQ_HANDLED;
215 }
216 
217 struct snd_ac97_bus_ops soc_ac97_ops = {
218 	.read       = s3c_ac97_read,
219 	.write      = s3c_ac97_write,
220 	.warm_reset = s3c_ac97_warm_reset,
221 	.reset      = s3c_ac97_cold_reset,
222 };
223 EXPORT_SYMBOL_GPL(soc_ac97_ops);
224 
s3c_ac97_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)225 static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
226 				  struct snd_pcm_hw_params *params,
227 				  struct snd_soc_dai *dai)
228 {
229 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
230 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
231 	struct s3c_dma_params *dma_data;
232 
233 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
234 		dma_data = &s3c_ac97_pcm_out;
235 	else
236 		dma_data = &s3c_ac97_pcm_in;
237 
238 	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
239 
240 	return 0;
241 }
242 
s3c_ac97_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)243 static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
244 				struct snd_soc_dai *dai)
245 {
246 	u32 ac_glbctrl;
247 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
248 	struct s3c_dma_params *dma_data =
249 		snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
250 
251 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
252 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
253 		ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
254 	else
255 		ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
256 
257 	switch (cmd) {
258 	case SNDRV_PCM_TRIGGER_START:
259 	case SNDRV_PCM_TRIGGER_RESUME:
260 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
261 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
262 			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
263 		else
264 			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
265 		break;
266 
267 	case SNDRV_PCM_TRIGGER_STOP:
268 	case SNDRV_PCM_TRIGGER_SUSPEND:
269 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
270 		break;
271 	}
272 
273 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
274 
275 	if (!dma_data->ops)
276 		dma_data->ops = samsung_dma_get_ops();
277 
278 	dma_data->ops->started(dma_data->channel);
279 
280 	return 0;
281 }
282 
s3c_ac97_hw_mic_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)283 static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
284 				      struct snd_pcm_hw_params *params,
285 				      struct snd_soc_dai *dai)
286 {
287 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
288 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
289 
290 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
291 		return -ENODEV;
292 	else
293 		snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
294 
295 	return 0;
296 }
297 
s3c_ac97_mic_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)298 static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
299 				    int cmd, struct snd_soc_dai *dai)
300 {
301 	u32 ac_glbctrl;
302 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
303 	struct s3c_dma_params *dma_data =
304 		snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
305 
306 	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
307 	ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
308 
309 	switch (cmd) {
310 	case SNDRV_PCM_TRIGGER_START:
311 	case SNDRV_PCM_TRIGGER_RESUME:
312 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
313 		ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
314 		break;
315 
316 	case SNDRV_PCM_TRIGGER_STOP:
317 	case SNDRV_PCM_TRIGGER_SUSPEND:
318 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
319 		break;
320 	}
321 
322 	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
323 
324 	if (!dma_data->ops)
325 		dma_data->ops = samsung_dma_get_ops();
326 
327 	dma_data->ops->started(dma_data->channel);
328 
329 	return 0;
330 }
331 
332 static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
333 	.hw_params	= s3c_ac97_hw_params,
334 	.trigger	= s3c_ac97_trigger,
335 };
336 
337 static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
338 	.hw_params	= s3c_ac97_hw_mic_params,
339 	.trigger	= s3c_ac97_mic_trigger,
340 };
341 
342 static struct snd_soc_dai_driver s3c_ac97_dai[] = {
343 	[S3C_AC97_DAI_PCM] = {
344 		.name =	"samsung-ac97",
345 		.ac97_control = 1,
346 		.playback = {
347 			.stream_name = "AC97 Playback",
348 			.channels_min = 2,
349 			.channels_max = 2,
350 			.rates = SNDRV_PCM_RATE_8000_48000,
351 			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
352 		.capture = {
353 			.stream_name = "AC97 Capture",
354 			.channels_min = 2,
355 			.channels_max = 2,
356 			.rates = SNDRV_PCM_RATE_8000_48000,
357 			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
358 		.ops = &s3c_ac97_dai_ops,
359 	},
360 	[S3C_AC97_DAI_MIC] = {
361 		.name = "samsung-ac97-mic",
362 		.ac97_control = 1,
363 		.capture = {
364 			.stream_name = "AC97 Mic Capture",
365 			.channels_min = 1,
366 			.channels_max = 1,
367 			.rates = SNDRV_PCM_RATE_8000_48000,
368 			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
369 		.ops = &s3c_ac97_mic_dai_ops,
370 	},
371 };
372 
s3c_ac97_probe(struct platform_device * pdev)373 static __devinit int s3c_ac97_probe(struct platform_device *pdev)
374 {
375 	struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
376 	struct s3c_audio_pdata *ac97_pdata;
377 	int ret;
378 
379 	ac97_pdata = pdev->dev.platform_data;
380 	if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
381 		dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
382 		return -EINVAL;
383 	}
384 
385 	/* Check for availability of necessary resource */
386 	dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
387 	if (!dmatx_res) {
388 		dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
389 		return -ENXIO;
390 	}
391 
392 	dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
393 	if (!dmarx_res) {
394 		dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
395 		return -ENXIO;
396 	}
397 
398 	dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
399 	if (!dmamic_res) {
400 		dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
401 		return -ENXIO;
402 	}
403 
404 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
405 	if (!mem_res) {
406 		dev_err(&pdev->dev, "Unable to get register resource\n");
407 		return -ENXIO;
408 	}
409 
410 	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
411 	if (!irq_res) {
412 		dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
413 		return -ENXIO;
414 	}
415 
416 	if (!request_mem_region(mem_res->start,
417 				resource_size(mem_res), "ac97")) {
418 		dev_err(&pdev->dev, "Unable to request register region\n");
419 		return -EBUSY;
420 	}
421 
422 	s3c_ac97_pcm_out.channel = dmatx_res->start;
423 	s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
424 	s3c_ac97_pcm_in.channel = dmarx_res->start;
425 	s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
426 	s3c_ac97_mic_in.channel = dmamic_res->start;
427 	s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
428 
429 	init_completion(&s3c_ac97.done);
430 	mutex_init(&s3c_ac97.lock);
431 
432 	s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
433 	if (s3c_ac97.regs == NULL) {
434 		dev_err(&pdev->dev, "Unable to ioremap register region\n");
435 		ret = -ENXIO;
436 		goto err1;
437 	}
438 
439 	s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
440 	if (IS_ERR(s3c_ac97.ac97_clk)) {
441 		dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
442 		ret = -ENODEV;
443 		goto err2;
444 	}
445 	clk_enable(s3c_ac97.ac97_clk);
446 
447 	if (ac97_pdata->cfg_gpio(pdev)) {
448 		dev_err(&pdev->dev, "Unable to configure gpio\n");
449 		ret = -EINVAL;
450 		goto err3;
451 	}
452 
453 	ret = request_irq(irq_res->start, s3c_ac97_irq,
454 					0, "AC97", NULL);
455 	if (ret < 0) {
456 		dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
457 		goto err4;
458 	}
459 
460 	ret = snd_soc_register_dais(&pdev->dev, s3c_ac97_dai,
461 			ARRAY_SIZE(s3c_ac97_dai));
462 	if (ret)
463 		goto err5;
464 
465 	return 0;
466 
467 err5:
468 	free_irq(irq_res->start, NULL);
469 err4:
470 err3:
471 	clk_disable(s3c_ac97.ac97_clk);
472 	clk_put(s3c_ac97.ac97_clk);
473 err2:
474 	iounmap(s3c_ac97.regs);
475 err1:
476 	release_mem_region(mem_res->start, resource_size(mem_res));
477 
478 	return ret;
479 }
480 
s3c_ac97_remove(struct platform_device * pdev)481 static __devexit int s3c_ac97_remove(struct platform_device *pdev)
482 {
483 	struct resource *mem_res, *irq_res;
484 
485 	snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(s3c_ac97_dai));
486 
487 	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
488 	if (irq_res)
489 		free_irq(irq_res->start, NULL);
490 
491 	clk_disable(s3c_ac97.ac97_clk);
492 	clk_put(s3c_ac97.ac97_clk);
493 
494 	iounmap(s3c_ac97.regs);
495 
496 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 	if (mem_res)
498 		release_mem_region(mem_res->start, resource_size(mem_res));
499 
500 	return 0;
501 }
502 
503 static struct platform_driver s3c_ac97_driver = {
504 	.probe  = s3c_ac97_probe,
505 	.remove = __devexit_p(s3c_ac97_remove),
506 	.driver = {
507 		.name = "samsung-ac97",
508 		.owner = THIS_MODULE,
509 	},
510 };
511 
512 module_platform_driver(s3c_ac97_driver);
513 
514 MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
515 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
516 MODULE_LICENSE("GPL");
517 MODULE_ALIAS("platform:samsung-ac97");
518