1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/initval.h>
24 #include <sound/soc.h>
25
26 #include <mach/asp.h>
27
28 #include "davinci-pcm.h"
29 #include "davinci-i2s.h"
30
31
32 /*
33 * NOTE: terminology here is confusing.
34 *
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
37 *
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
41 *
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
44 *
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
47 *
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
50 */
51 #define DAVINCI_MCBSP_DRR_REG 0x00
52 #define DAVINCI_MCBSP_DXR_REG 0x04
53 #define DAVINCI_MCBSP_SPCR_REG 0x08
54 #define DAVINCI_MCBSP_RCR_REG 0x0c
55 #define DAVINCI_MCBSP_XCR_REG 0x10
56 #define DAVINCI_MCBSP_SRGR_REG 0x14
57 #define DAVINCI_MCBSP_PCR_REG 0x24
58
59 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
66
67 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
70 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
71 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
72 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
74
75 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
80 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
82
83 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
86 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
87
88 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
92 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
93 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
97
98 enum {
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
105 };
106
107 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
111 };
112
113 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
117 };
118
119 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
122 };
123
124 struct davinci_mcbsp_dev {
125 struct device *dev;
126 struct davinci_pcm_dma_params dma_params[2];
127 void __iomem *base;
128 #define MOD_DSP_A 0
129 #define MOD_DSP_B 1
130 int mode;
131 u32 pcr;
132 struct clk *clk;
133 /*
134 * Combining both channels into 1 element will at least double the
135 * amount of time between servicing the dma channel, increase
136 * effiency, and reduce the chance of overrun/underrun. But,
137 * it will result in the left & right channels being swapped.
138 *
139 * If relabeling the left and right channels is not possible,
140 * you may want to let the codec know to swap them back.
141 *
142 * It may allow x10 the amount of time to service dma requests,
143 * if the codec is master and is using an unnecessarily fast bit clock
144 * (ie. tlvaic23b), independent of the sample rate. So, having an
145 * entire frame at once means it can be serviced at the sample rate
146 * instead of the bit clock rate.
147 *
148 * In the now unlikely case that an underrun still
149 * occurs, both the left and right samples will be repeated
150 * so that no pops are heard, and the left and right channels
151 * won't end up being swapped because of the underrun.
152 */
153 unsigned enable_channel_combine:1;
154
155 unsigned int fmt;
156 int clk_div;
157 int clk_input_pin;
158 bool i2s_accurate_sck;
159 };
160
davinci_mcbsp_write_reg(struct davinci_mcbsp_dev * dev,int reg,u32 val)161 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
162 int reg, u32 val)
163 {
164 __raw_writel(val, dev->base + reg);
165 }
166
davinci_mcbsp_read_reg(struct davinci_mcbsp_dev * dev,int reg)167 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
168 {
169 return __raw_readl(dev->base + reg);
170 }
171
toggle_clock(struct davinci_mcbsp_dev * dev,int playback)172 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
173 {
174 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
175 /* The clock needs to toggle to complete reset.
176 * So, fake it by toggling the clk polarity.
177 */
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
179 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
180 }
181
davinci_mcbsp_start(struct davinci_mcbsp_dev * dev,struct snd_pcm_substream * substream)182 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
183 struct snd_pcm_substream *substream)
184 {
185 struct snd_soc_pcm_runtime *rtd = substream->private_data;
186 struct snd_soc_platform *platform = rtd->platform;
187 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
188 u32 spcr;
189 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
190 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
191 if (spcr & mask) {
192 /* start off disabled */
193 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
194 spcr & ~mask);
195 toggle_clock(dev, playback);
196 }
197 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
198 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
199 /* Start the sample generator */
200 spcr |= DAVINCI_MCBSP_SPCR_GRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
202 }
203
204 if (playback) {
205 /* Stop the DMA to avoid data loss */
206 /* while the transmitter is out of reset to handle XSYNCERR */
207 if (platform->driver->ops->trigger) {
208 int ret = platform->driver->ops->trigger(substream,
209 SNDRV_PCM_TRIGGER_STOP);
210 if (ret < 0)
211 printk(KERN_DEBUG "Playback DMA stop failed\n");
212 }
213
214 /* Enable the transmitter */
215 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
216 spcr |= DAVINCI_MCBSP_SPCR_XRST;
217 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
218
219 /* wait for any unexpected frame sync error to occur */
220 udelay(100);
221
222 /* Disable the transmitter to clear any outstanding XSYNCERR */
223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
226 toggle_clock(dev, playback);
227
228 /* Restart the DMA */
229 if (platform->driver->ops->trigger) {
230 int ret = platform->driver->ops->trigger(substream,
231 SNDRV_PCM_TRIGGER_START);
232 if (ret < 0)
233 printk(KERN_DEBUG "Playback DMA start failed\n");
234 }
235 }
236
237 /* Enable transmitter or receiver */
238 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
239 spcr |= mask;
240
241 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
242 /* Start frame sync */
243 spcr |= DAVINCI_MCBSP_SPCR_FRST;
244 }
245 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
246 }
247
davinci_mcbsp_stop(struct davinci_mcbsp_dev * dev,int playback)248 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
249 {
250 u32 spcr;
251
252 /* Reset transmitter/receiver and sample rate/frame sync generators */
253 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
254 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
255 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
256 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
257 toggle_clock(dev, playback);
258 }
259
260 #define DEFAULT_BITPERSAMPLE 16
261
davinci_i2s_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)262 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 unsigned int fmt)
264 {
265 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
266 unsigned int pcr;
267 unsigned int srgr;
268 bool inv_fs = false;
269 /* Attention srgr is updated by hw_params! */
270 srgr = DAVINCI_MCBSP_SRGR_FSGM |
271 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
272 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
273
274 dev->fmt = fmt;
275 /* set master/slave audio interface */
276 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
277 case SND_SOC_DAIFMT_CBS_CFS:
278 /* cpu is master */
279 pcr = DAVINCI_MCBSP_PCR_FSXM |
280 DAVINCI_MCBSP_PCR_FSRM |
281 DAVINCI_MCBSP_PCR_CLKXM |
282 DAVINCI_MCBSP_PCR_CLKRM;
283 break;
284 case SND_SOC_DAIFMT_CBM_CFS:
285 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
286 /*
287 * Selection of the clock input pin that is the
288 * input for the Sample Rate Generator.
289 * McBSP FSR and FSX are driven by the Sample Rate
290 * Generator.
291 */
292 switch (dev->clk_input_pin) {
293 case MCBSP_CLKS:
294 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
295 DAVINCI_MCBSP_PCR_CLKRM;
296 break;
297 case MCBSP_CLKR:
298 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
299 break;
300 default:
301 dev_err(dev->dev, "bad clk_input_pin\n");
302 return -EINVAL;
303 }
304
305 break;
306 case SND_SOC_DAIFMT_CBM_CFM:
307 /* codec is master */
308 pcr = 0;
309 break;
310 default:
311 printk(KERN_ERR "%s:bad master\n", __func__);
312 return -EINVAL;
313 }
314
315 /* interface format */
316 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
317 case SND_SOC_DAIFMT_I2S:
318 /* Davinci doesn't support TRUE I2S, but some codecs will have
319 * the left and right channels contiguous. This allows
320 * dsp_a mode to be used with an inverted normal frame clk.
321 * If your codec is master and does not have contiguous
322 * channels, then you will have sound on only one channel.
323 * Try using a different mode, or codec as slave.
324 *
325 * The TLV320AIC33 is an example of a codec where this works.
326 * It has a variable bit clock frequency allowing it to have
327 * valid data on every bit clock.
328 *
329 * The TLV320AIC23 is an example of a codec where this does not
330 * work. It has a fixed bit clock frequency with progressively
331 * more empty bit clock slots between channels as the sample
332 * rate is lowered.
333 */
334 inv_fs = true;
335 case SND_SOC_DAIFMT_DSP_A:
336 dev->mode = MOD_DSP_A;
337 break;
338 case SND_SOC_DAIFMT_DSP_B:
339 dev->mode = MOD_DSP_B;
340 break;
341 default:
342 printk(KERN_ERR "%s:bad format\n", __func__);
343 return -EINVAL;
344 }
345
346 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
347 case SND_SOC_DAIFMT_NB_NF:
348 /* CLKRP Receive clock polarity,
349 * 1 - sampled on rising edge of CLKR
350 * valid on rising edge
351 * CLKXP Transmit clock polarity,
352 * 1 - clocked on falling edge of CLKX
353 * valid on rising edge
354 * FSRP Receive frame sync pol, 0 - active high
355 * FSXP Transmit frame sync pol, 0 - active high
356 */
357 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
358 break;
359 case SND_SOC_DAIFMT_IB_IF:
360 /* CLKRP Receive clock polarity,
361 * 0 - sampled on falling edge of CLKR
362 * valid on falling edge
363 * CLKXP Transmit clock polarity,
364 * 0 - clocked on rising edge of CLKX
365 * valid on falling edge
366 * FSRP Receive frame sync pol, 1 - active low
367 * FSXP Transmit frame sync pol, 1 - active low
368 */
369 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
370 break;
371 case SND_SOC_DAIFMT_NB_IF:
372 /* CLKRP Receive clock polarity,
373 * 1 - sampled on rising edge of CLKR
374 * valid on rising edge
375 * CLKXP Transmit clock polarity,
376 * 1 - clocked on falling edge of CLKX
377 * valid on rising edge
378 * FSRP Receive frame sync pol, 1 - active low
379 * FSXP Transmit frame sync pol, 1 - active low
380 */
381 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
382 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
383 break;
384 case SND_SOC_DAIFMT_IB_NF:
385 /* CLKRP Receive clock polarity,
386 * 0 - sampled on falling edge of CLKR
387 * valid on falling edge
388 * CLKXP Transmit clock polarity,
389 * 0 - clocked on rising edge of CLKX
390 * valid on falling edge
391 * FSRP Receive frame sync pol, 0 - active high
392 * FSXP Transmit frame sync pol, 0 - active high
393 */
394 break;
395 default:
396 return -EINVAL;
397 }
398 if (inv_fs == true)
399 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
400 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
401 dev->pcr = pcr;
402 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
403 return 0;
404 }
405
davinci_i2s_dai_set_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)406 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
407 int div_id, int div)
408 {
409 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
410
411 if (div_id != DAVINCI_MCBSP_CLKGDV)
412 return -ENODEV;
413
414 dev->clk_div = div;
415 return 0;
416 }
417
davinci_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)418 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
419 struct snd_pcm_hw_params *params,
420 struct snd_soc_dai *dai)
421 {
422 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
423 struct davinci_pcm_dma_params *dma_params =
424 &dev->dma_params[substream->stream];
425 struct snd_interval *i = NULL;
426 int mcbsp_word_length, master;
427 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
428 u32 spcr;
429 snd_pcm_format_t fmt;
430 unsigned element_cnt = 1;
431
432 /* general line settings */
433 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
434 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
435 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
436 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
437 } else {
438 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
439 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
440 }
441
442 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
443 fmt = params_format(params);
444 mcbsp_word_length = asp_word_length[fmt];
445
446 switch (master) {
447 case SND_SOC_DAIFMT_CBS_CFS:
448 freq = clk_get_rate(dev->clk);
449 srgr = DAVINCI_MCBSP_SRGR_FSGM |
450 DAVINCI_MCBSP_SRGR_CLKSM;
451 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
452 8 - 1);
453 if (dev->i2s_accurate_sck) {
454 clk_div = 256;
455 do {
456 framesize = (freq / (--clk_div)) /
457 params->rate_num *
458 params->rate_den;
459 } while (((framesize < 33) || (framesize > 4095)) &&
460 (clk_div));
461 clk_div--;
462 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
463 } else {
464 /* symmetric waveforms */
465 clk_div = freq / (mcbsp_word_length * 16) /
466 params->rate_num * params->rate_den;
467 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
468 16 - 1);
469 }
470 clk_div &= 0xFF;
471 srgr |= clk_div;
472 break;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 srgr = DAVINCI_MCBSP_SRGR_FSGM;
475 clk_div = dev->clk_div - 1;
476 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
477 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
478 clk_div &= 0xFF;
479 srgr |= clk_div;
480 break;
481 case SND_SOC_DAIFMT_CBM_CFM:
482 /* Clock and frame sync given from external sources */
483 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
484 srgr = DAVINCI_MCBSP_SRGR_FSGM;
485 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
486 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
487 __func__, __LINE__, snd_interval_value(i) - 1);
488
489 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
490 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
491 break;
492 default:
493 return -EINVAL;
494 }
495 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
496
497 rcr = DAVINCI_MCBSP_RCR_RFIG;
498 xcr = DAVINCI_MCBSP_XCR_XFIG;
499 if (dev->mode == MOD_DSP_B) {
500 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
501 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
502 } else {
503 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
504 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
505 }
506 /* Determine xfer data type */
507 fmt = params_format(params);
508 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
509 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
510 return -EINVAL;
511 }
512
513 if (params_channels(params) == 2) {
514 element_cnt = 2;
515 if (double_fmt[fmt] && dev->enable_channel_combine) {
516 element_cnt = 1;
517 fmt = double_fmt[fmt];
518 }
519 switch (master) {
520 case SND_SOC_DAIFMT_CBS_CFS:
521 case SND_SOC_DAIFMT_CBS_CFM:
522 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
523 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
524 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
525 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
526 break;
527 case SND_SOC_DAIFMT_CBM_CFM:
528 case SND_SOC_DAIFMT_CBM_CFS:
529 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
530 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
531 break;
532 default:
533 return -EINVAL;
534 }
535 }
536 dma_params->acnt = dma_params->data_type = data_type[fmt];
537 dma_params->fifo_level = 0;
538 mcbsp_word_length = asp_word_length[fmt];
539
540 switch (master) {
541 case SND_SOC_DAIFMT_CBS_CFS:
542 case SND_SOC_DAIFMT_CBS_CFM:
543 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
544 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
545 break;
546 case SND_SOC_DAIFMT_CBM_CFM:
547 case SND_SOC_DAIFMT_CBM_CFS:
548 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
549 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
550 break;
551 default:
552 return -EINVAL;
553 }
554
555 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
556 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
557 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
558 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
559
560 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
561 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
562 else
563 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
564
565 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
566 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
567 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
568 return 0;
569 }
570
davinci_i2s_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)571 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573 {
574 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
575 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
576 davinci_mcbsp_stop(dev, playback);
577 return 0;
578 }
579
davinci_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)580 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
581 struct snd_soc_dai *dai)
582 {
583 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
584 int ret = 0;
585 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
586
587 switch (cmd) {
588 case SNDRV_PCM_TRIGGER_START:
589 case SNDRV_PCM_TRIGGER_RESUME:
590 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
591 davinci_mcbsp_start(dev, substream);
592 break;
593 case SNDRV_PCM_TRIGGER_STOP:
594 case SNDRV_PCM_TRIGGER_SUSPEND:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
596 davinci_mcbsp_stop(dev, playback);
597 break;
598 default:
599 ret = -EINVAL;
600 }
601 return ret;
602 }
603
davinci_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)604 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
605 struct snd_soc_dai *dai)
606 {
607 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
608
609 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
610 return 0;
611 }
612
davinci_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)613 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
614 struct snd_soc_dai *dai)
615 {
616 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
617 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
618 davinci_mcbsp_stop(dev, playback);
619 }
620
621 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
622
623 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
624 .startup = davinci_i2s_startup,
625 .shutdown = davinci_i2s_shutdown,
626 .prepare = davinci_i2s_prepare,
627 .trigger = davinci_i2s_trigger,
628 .hw_params = davinci_i2s_hw_params,
629 .set_fmt = davinci_i2s_set_dai_fmt,
630 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
631
632 };
633
634 static struct snd_soc_dai_driver davinci_i2s_dai = {
635 .playback = {
636 .channels_min = 2,
637 .channels_max = 2,
638 .rates = DAVINCI_I2S_RATES,
639 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
640 .capture = {
641 .channels_min = 2,
642 .channels_max = 2,
643 .rates = DAVINCI_I2S_RATES,
644 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
645 .ops = &davinci_i2s_dai_ops,
646
647 };
648
davinci_i2s_probe(struct platform_device * pdev)649 static int davinci_i2s_probe(struct platform_device *pdev)
650 {
651 struct snd_platform_data *pdata = pdev->dev.platform_data;
652 struct davinci_mcbsp_dev *dev;
653 struct resource *mem, *ioarea, *res;
654 enum dma_event_q asp_chan_q = EVENTQ_0;
655 enum dma_event_q ram_chan_q = EVENTQ_1;
656 int ret;
657
658 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
659 if (!mem) {
660 dev_err(&pdev->dev, "no mem resource?\n");
661 return -ENODEV;
662 }
663
664 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
665 resource_size(mem),
666 pdev->name);
667 if (!ioarea) {
668 dev_err(&pdev->dev, "McBSP region already claimed\n");
669 return -EBUSY;
670 }
671
672 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
673 GFP_KERNEL);
674 if (!dev)
675 return -ENOMEM;
676 if (pdata) {
677 dev->enable_channel_combine = pdata->enable_channel_combine;
678 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
679 pdata->sram_size_playback;
680 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
681 pdata->sram_size_capture;
682 dev->clk_input_pin = pdata->clk_input_pin;
683 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
684 asp_chan_q = pdata->asp_chan_q;
685 ram_chan_q = pdata->ram_chan_q;
686 }
687
688 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
689 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
690 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
691 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
692
693 dev->clk = clk_get(&pdev->dev, NULL);
694 if (IS_ERR(dev->clk))
695 return -ENODEV;
696 clk_enable(dev->clk);
697
698 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
699 if (!dev->base) {
700 dev_err(&pdev->dev, "ioremap failed\n");
701 ret = -ENOMEM;
702 goto err_release_clk;
703 }
704
705 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
706 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
707
708 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
709 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
710
711 /* first TX, then RX */
712 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
713 if (!res) {
714 dev_err(&pdev->dev, "no DMA resource\n");
715 ret = -ENXIO;
716 goto err_release_clk;
717 }
718 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
719
720 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
721 if (!res) {
722 dev_err(&pdev->dev, "no DMA resource\n");
723 ret = -ENXIO;
724 goto err_release_clk;
725 }
726 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
727 dev->dev = &pdev->dev;
728
729 dev_set_drvdata(&pdev->dev, dev);
730
731 ret = snd_soc_register_dai(&pdev->dev, &davinci_i2s_dai);
732 if (ret != 0)
733 goto err_release_clk;
734
735 return 0;
736
737 err_release_clk:
738 clk_disable(dev->clk);
739 clk_put(dev->clk);
740 return ret;
741 }
742
davinci_i2s_remove(struct platform_device * pdev)743 static int davinci_i2s_remove(struct platform_device *pdev)
744 {
745 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
746
747 snd_soc_unregister_dai(&pdev->dev);
748 clk_disable(dev->clk);
749 clk_put(dev->clk);
750 dev->clk = NULL;
751
752 return 0;
753 }
754
755 static struct platform_driver davinci_mcbsp_driver = {
756 .probe = davinci_i2s_probe,
757 .remove = davinci_i2s_remove,
758 .driver = {
759 .name = "davinci-mcbsp",
760 .owner = THIS_MODULE,
761 },
762 };
763
764 module_platform_driver(davinci_mcbsp_driver);
765
766 MODULE_AUTHOR("Vladimir Barinov");
767 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
768 MODULE_LICENSE("GPL");
769