1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
57
58
59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62 static char *model[SNDRV_CARDS];
63 static int position_fix[SNDRV_CARDS];
64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66 static int probe_only[SNDRV_CARDS];
67 static bool single_cmd;
68 static int enable_msi = -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch[SNDRV_CARDS];
71 #endif
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75 #endif
76
77 module_param_array(index, int, NULL, 0444);
78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79 module_param_array(id, charp, NULL, 0444);
80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81 module_param_array(enable, bool, NULL, 0444);
82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83 module_param_array(model, charp, NULL, 0444);
84 MODULE_PARM_DESC(model, "Use the given board model.");
85 module_param_array(position_fix, int, NULL, 0444);
86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
88 module_param_array(bdl_pos_adj, int, NULL, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90 module_param_array(probe_mask, int, NULL, 0444);
91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94 module_param(single_cmd, bool, 0444);
95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi, int, 0444);
98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch, charp, NULL, 0444);
101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102 #endif
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode, int, NULL, 0444);
105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107 #endif
108
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111 module_param(power_save, int, 0644);
112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
114
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119 static bool power_save_controller = 1;
120 module_param(power_save_controller, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122 #endif
123
124 static bool align_buffer_size = 1;
125 module_param(align_buffer_size, bool, 0644);
126 MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
129 #ifdef CONFIG_X86
130 static bool hda_snoop = true;
131 module_param_named(snoop, hda_snoop, bool, 0444);
132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
134 #else
135 #define hda_snoop true
136 #define azx_snoop(chip) true
137 #endif
138
139
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
143 "{Intel, ICH7},"
144 "{Intel, ESB2},"
145 "{Intel, ICH8},"
146 "{Intel, ICH9},"
147 "{Intel, ICH10},"
148 "{Intel, PCH},"
149 "{Intel, CPT},"
150 "{Intel, PPT},"
151 "{Intel, PBG},"
152 "{Intel, SCH},"
153 "{ATI, SB450},"
154 "{ATI, SB600},"
155 "{ATI, RS600},"
156 "{ATI, RS690},"
157 "{ATI, RS780},"
158 "{ATI, R600},"
159 "{ATI, RV630},"
160 "{ATI, RV610},"
161 "{ATI, RV670},"
162 "{ATI, RV635},"
163 "{ATI, RV620},"
164 "{ATI, RV770},"
165 "{VIA, VT8251},"
166 "{VIA, VT8237A},"
167 "{SiS, SIS966},"
168 "{ULI, M5461}}");
169 MODULE_DESCRIPTION("Intel HDA driver");
170
171 #ifdef CONFIG_SND_VERBOSE_PRINTK
172 #define SFX /* nop */
173 #else
174 #define SFX "hda-intel: "
175 #endif
176
177 /*
178 * registers
179 */
180 #define ICH6_REG_GCAP 0x00
181 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
182 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
183 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
184 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
185 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
186 #define ICH6_REG_VMIN 0x02
187 #define ICH6_REG_VMAJ 0x03
188 #define ICH6_REG_OUTPAY 0x04
189 #define ICH6_REG_INPAY 0x06
190 #define ICH6_REG_GCTL 0x08
191 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
192 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
193 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
194 #define ICH6_REG_WAKEEN 0x0c
195 #define ICH6_REG_STATESTS 0x0e
196 #define ICH6_REG_GSTS 0x10
197 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
198 #define ICH6_REG_INTCTL 0x20
199 #define ICH6_REG_INTSTS 0x24
200 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
201 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
202 #define ICH6_REG_SSYNC 0x38
203 #define ICH6_REG_CORBLBASE 0x40
204 #define ICH6_REG_CORBUBASE 0x44
205 #define ICH6_REG_CORBWP 0x48
206 #define ICH6_REG_CORBRP 0x4a
207 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
208 #define ICH6_REG_CORBCTL 0x4c
209 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
210 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
211 #define ICH6_REG_CORBSTS 0x4d
212 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
213 #define ICH6_REG_CORBSIZE 0x4e
214
215 #define ICH6_REG_RIRBLBASE 0x50
216 #define ICH6_REG_RIRBUBASE 0x54
217 #define ICH6_REG_RIRBWP 0x58
218 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
219 #define ICH6_REG_RINTCNT 0x5a
220 #define ICH6_REG_RIRBCTL 0x5c
221 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
222 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
223 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
224 #define ICH6_REG_RIRBSTS 0x5d
225 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
226 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
227 #define ICH6_REG_RIRBSIZE 0x5e
228
229 #define ICH6_REG_IC 0x60
230 #define ICH6_REG_IR 0x64
231 #define ICH6_REG_IRS 0x68
232 #define ICH6_IRS_VALID (1<<1)
233 #define ICH6_IRS_BUSY (1<<0)
234
235 #define ICH6_REG_DPLBASE 0x70
236 #define ICH6_REG_DPUBASE 0x74
237 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
238
239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
241
242 /* stream register offsets from stream base */
243 #define ICH6_REG_SD_CTL 0x00
244 #define ICH6_REG_SD_STS 0x03
245 #define ICH6_REG_SD_LPIB 0x04
246 #define ICH6_REG_SD_CBL 0x08
247 #define ICH6_REG_SD_LVI 0x0c
248 #define ICH6_REG_SD_FIFOW 0x0e
249 #define ICH6_REG_SD_FIFOSIZE 0x10
250 #define ICH6_REG_SD_FORMAT 0x12
251 #define ICH6_REG_SD_BDLPL 0x18
252 #define ICH6_REG_SD_BDLPU 0x1c
253
254 /* PCI space */
255 #define ICH6_PCIREG_TCSEL 0x44
256
257 /*
258 * other constants
259 */
260
261 /* max number of SDs */
262 /* ICH, ATI and VIA have 4 playback and 4 capture */
263 #define ICH6_NUM_CAPTURE 4
264 #define ICH6_NUM_PLAYBACK 4
265
266 /* ULI has 6 playback and 5 capture */
267 #define ULI_NUM_CAPTURE 5
268 #define ULI_NUM_PLAYBACK 6
269
270 /* ATI HDMI has 1 playback and 0 capture */
271 #define ATIHDMI_NUM_CAPTURE 0
272 #define ATIHDMI_NUM_PLAYBACK 1
273
274 /* TERA has 4 playback and 3 capture */
275 #define TERA_NUM_CAPTURE 3
276 #define TERA_NUM_PLAYBACK 4
277
278 /* this number is statically defined for simplicity */
279 #define MAX_AZX_DEV 16
280
281 /* max number of fragments - we may use more if allocating more pages for BDL */
282 #define BDL_SIZE 4096
283 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284 #define AZX_MAX_FRAG 32
285 /* max buffer size - no h/w limit, you can increase as you like */
286 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
287
288 /* RIRB int mask: overrun[2], response[0] */
289 #define RIRB_INT_RESPONSE 0x01
290 #define RIRB_INT_OVERRUN 0x04
291 #define RIRB_INT_MASK 0x05
292
293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
294 #define AZX_MAX_CODECS 8
295 #define AZX_DEFAULT_CODECS 4
296 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
297
298 /* SD_CTL bits */
299 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
300 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
301 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
302 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
303 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
304 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305 #define SD_CTL_STREAM_TAG_SHIFT 20
306
307 /* SD_CTL and SD_STS */
308 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
309 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
310 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
311 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
312 SD_INT_COMPLETE)
313
314 /* SD_STS */
315 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
316
317 /* INTCTL and INTSTS */
318 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
319 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
320 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
321
322 /* below are so far hardcoded - should read registers in future */
323 #define ICH6_MAX_CORB_ENTRIES 256
324 #define ICH6_MAX_RIRB_ENTRIES 256
325
326 /* position fix mode */
327 enum {
328 POS_FIX_AUTO,
329 POS_FIX_LPIB,
330 POS_FIX_POSBUF,
331 POS_FIX_VIACOMBO,
332 };
333
334 /* Defines for ATI HD Audio support in SB450 south bridge */
335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
337
338 /* Defines for Nvidia HDA support */
339 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
341 #define NVIDIA_HDA_ISTRM_COH 0x4d
342 #define NVIDIA_HDA_OSTRM_COH 0x4c
343 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
344
345 /* Defines for Intel SCH HDA snoop control */
346 #define INTEL_SCH_HDA_DEVC 0x78
347 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
348
349 /* Define IN stream 0 FIFO size offset in VIA controller */
350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351 /* Define VIA HD Audio Device ID*/
352 #define VIA_HDAC_DEVICE_ID 0x3288
353
354 /* HD Audio class code */
355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
356
357 /*
358 */
359
360 struct azx_dev {
361 struct snd_dma_buffer bdl; /* BDL buffer */
362 u32 *posbuf; /* position buffer pointer */
363
364 unsigned int bufsize; /* size of the play buffer in bytes */
365 unsigned int period_bytes; /* size of the period in bytes */
366 unsigned int frags; /* number for period in the play buffer */
367 unsigned int fifo_size; /* FIFO size */
368 unsigned long start_wallclk; /* start + minimum wallclk */
369 unsigned long period_wallclk; /* wallclk for period */
370
371 void __iomem *sd_addr; /* stream descriptor pointer */
372
373 u32 sd_int_sta_mask; /* stream int status mask */
374
375 /* pcm support */
376 struct snd_pcm_substream *substream; /* assigned substream,
377 * set in PCM open
378 */
379 unsigned int format_val; /* format value to be set in the
380 * controller and the codec
381 */
382 unsigned char stream_tag; /* assigned stream */
383 unsigned char index; /* stream index */
384 int assigned_key; /* last device# key assigned to */
385
386 unsigned int opened :1;
387 unsigned int running :1;
388 unsigned int irq_pending :1;
389 /*
390 * For VIA:
391 * A flag to ensure DMA position is 0
392 * when link position is not greater than FIFO size
393 */
394 unsigned int insufficient :1;
395 unsigned int wc_marked:1;
396 };
397
398 /* CORB/RIRB */
399 struct azx_rb {
400 u32 *buf; /* CORB/RIRB buffer
401 * Each CORB entry is 4byte, RIRB is 8byte
402 */
403 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
404 /* for RIRB */
405 unsigned short rp, wp; /* read/write pointers */
406 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
407 u32 res[AZX_MAX_CODECS]; /* last read value */
408 };
409
410 struct azx_pcm {
411 struct azx *chip;
412 struct snd_pcm *pcm;
413 struct hda_codec *codec;
414 struct hda_pcm_stream *hinfo[2];
415 struct list_head list;
416 };
417
418 struct azx {
419 struct snd_card *card;
420 struct pci_dev *pci;
421 int dev_index;
422
423 /* chip type specific */
424 int driver_type;
425 unsigned int driver_caps;
426 int playback_streams;
427 int playback_index_offset;
428 int capture_streams;
429 int capture_index_offset;
430 int num_streams;
431
432 /* pci resources */
433 unsigned long addr;
434 void __iomem *remap_addr;
435 int irq;
436
437 /* locks */
438 spinlock_t reg_lock;
439 struct mutex open_mutex;
440
441 /* streams (x num_streams) */
442 struct azx_dev *azx_dev;
443
444 /* PCM */
445 struct list_head pcm_list; /* azx_pcm list */
446
447 /* HD codec */
448 unsigned short codec_mask;
449 int codec_probe_mask; /* copied from probe_mask option */
450 struct hda_bus *bus;
451 unsigned int beep_mode;
452
453 /* CORB/RIRB */
454 struct azx_rb corb;
455 struct azx_rb rirb;
456
457 /* CORB/RIRB and position buffers */
458 struct snd_dma_buffer rb;
459 struct snd_dma_buffer posbuf;
460
461 /* flags */
462 int position_fix[2]; /* for both playback/capture streams */
463 int poll_count;
464 unsigned int running :1;
465 unsigned int initialized :1;
466 unsigned int single_cmd :1;
467 unsigned int polling_mode :1;
468 unsigned int msi :1;
469 unsigned int irq_pending_warned :1;
470 unsigned int probing :1; /* codec probing phase */
471 unsigned int snoop:1;
472 unsigned int align_buffer_size:1;
473
474 /* for debugging */
475 unsigned int last_cmd[AZX_MAX_CODECS];
476
477 /* for pending irqs */
478 struct work_struct irq_pending_work;
479
480 /* reboot notifier (for mysterious hangup problem at power-down) */
481 struct notifier_block reboot_notifier;
482 };
483
484 /* driver types */
485 enum {
486 AZX_DRIVER_ICH,
487 AZX_DRIVER_PCH,
488 AZX_DRIVER_SCH,
489 AZX_DRIVER_ATI,
490 AZX_DRIVER_ATIHDMI,
491 AZX_DRIVER_ATIHDMI_NS,
492 AZX_DRIVER_VIA,
493 AZX_DRIVER_SIS,
494 AZX_DRIVER_ULI,
495 AZX_DRIVER_NVIDIA,
496 AZX_DRIVER_TERA,
497 AZX_DRIVER_CTX,
498 AZX_DRIVER_GENERIC,
499 AZX_NUM_DRIVERS, /* keep this as last entry */
500 };
501
502 /* driver quirks (capabilities) */
503 /* bits 0-7 are used for indicating driver type */
504 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
505 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
506 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
507 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
508 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
509 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
510 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
511 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
512 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
513 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
514 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
515 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
516 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
517 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
518
519 /* quirks for ATI SB / AMD Hudson */
520 #define AZX_DCAPS_PRESET_ATI_SB \
521 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
522 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
523
524 /* quirks for ATI/AMD HDMI */
525 #define AZX_DCAPS_PRESET_ATI_HDMI \
526 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
527
528 /* quirks for Nvidia */
529 #define AZX_DCAPS_PRESET_NVIDIA \
530 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
531
532 static char *driver_short_names[] __devinitdata = {
533 [AZX_DRIVER_ICH] = "HDA Intel",
534 [AZX_DRIVER_PCH] = "HDA Intel PCH",
535 [AZX_DRIVER_SCH] = "HDA Intel MID",
536 [AZX_DRIVER_ATI] = "HDA ATI SB",
537 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
538 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
539 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
540 [AZX_DRIVER_SIS] = "HDA SIS966",
541 [AZX_DRIVER_ULI] = "HDA ULI M5461",
542 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
543 [AZX_DRIVER_TERA] = "HDA Teradici",
544 [AZX_DRIVER_CTX] = "HDA Creative",
545 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
546 };
547
548 /*
549 * macros for easy use
550 */
551 #define azx_writel(chip,reg,value) \
552 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
553 #define azx_readl(chip,reg) \
554 readl((chip)->remap_addr + ICH6_REG_##reg)
555 #define azx_writew(chip,reg,value) \
556 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
557 #define azx_readw(chip,reg) \
558 readw((chip)->remap_addr + ICH6_REG_##reg)
559 #define azx_writeb(chip,reg,value) \
560 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
561 #define azx_readb(chip,reg) \
562 readb((chip)->remap_addr + ICH6_REG_##reg)
563
564 #define azx_sd_writel(dev,reg,value) \
565 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
566 #define azx_sd_readl(dev,reg) \
567 readl((dev)->sd_addr + ICH6_REG_##reg)
568 #define azx_sd_writew(dev,reg,value) \
569 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
570 #define azx_sd_readw(dev,reg) \
571 readw((dev)->sd_addr + ICH6_REG_##reg)
572 #define azx_sd_writeb(dev,reg,value) \
573 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
574 #define azx_sd_readb(dev,reg) \
575 readb((dev)->sd_addr + ICH6_REG_##reg)
576
577 /* for pcm support */
578 #define get_azx_dev(substream) (substream->runtime->private_data)
579
580 #ifdef CONFIG_X86
__mark_pages_wc(struct azx * chip,void * addr,size_t size,bool on)581 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
582 {
583 if (azx_snoop(chip))
584 return;
585 if (addr && size) {
586 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
587 if (on)
588 set_memory_wc((unsigned long)addr, pages);
589 else
590 set_memory_wb((unsigned long)addr, pages);
591 }
592 }
593
mark_pages_wc(struct azx * chip,struct snd_dma_buffer * buf,bool on)594 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
595 bool on)
596 {
597 __mark_pages_wc(chip, buf->area, buf->bytes, on);
598 }
mark_runtime_wc(struct azx * chip,struct azx_dev * azx_dev,struct snd_pcm_runtime * runtime,bool on)599 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
600 struct snd_pcm_runtime *runtime, bool on)
601 {
602 if (azx_dev->wc_marked != on) {
603 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
604 azx_dev->wc_marked = on;
605 }
606 }
607 #else
608 /* NOP for other archs */
mark_pages_wc(struct azx * chip,struct snd_dma_buffer * buf,bool on)609 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
610 bool on)
611 {
612 }
mark_runtime_wc(struct azx * chip,struct azx_dev * azx_dev,struct snd_pcm_runtime * runtime,bool on)613 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
614 struct snd_pcm_runtime *runtime, bool on)
615 {
616 }
617 #endif
618
619 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
620 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
621 /*
622 * Interface for HD codec
623 */
624
625 /*
626 * CORB / RIRB interface
627 */
azx_alloc_cmd_io(struct azx * chip)628 static int azx_alloc_cmd_io(struct azx *chip)
629 {
630 int err;
631
632 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
633 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
634 snd_dma_pci_data(chip->pci),
635 PAGE_SIZE, &chip->rb);
636 if (err < 0) {
637 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
638 return err;
639 }
640 mark_pages_wc(chip, &chip->rb, true);
641 return 0;
642 }
643
azx_init_cmd_io(struct azx * chip)644 static void azx_init_cmd_io(struct azx *chip)
645 {
646 spin_lock_irq(&chip->reg_lock);
647 /* CORB set up */
648 chip->corb.addr = chip->rb.addr;
649 chip->corb.buf = (u32 *)chip->rb.area;
650 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
651 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
652
653 /* set the corb size to 256 entries (ULI requires explicitly) */
654 azx_writeb(chip, CORBSIZE, 0x02);
655 /* set the corb write pointer to 0 */
656 azx_writew(chip, CORBWP, 0);
657 /* reset the corb hw read pointer */
658 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
659 /* enable corb dma */
660 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
661
662 /* RIRB set up */
663 chip->rirb.addr = chip->rb.addr + 2048;
664 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
665 chip->rirb.wp = chip->rirb.rp = 0;
666 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
667 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
668 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
669
670 /* set the rirb size to 256 entries (ULI requires explicitly) */
671 azx_writeb(chip, RIRBSIZE, 0x02);
672 /* reset the rirb hw write pointer */
673 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
674 /* set N=1, get RIRB response interrupt for new entry */
675 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
676 azx_writew(chip, RINTCNT, 0xc0);
677 else
678 azx_writew(chip, RINTCNT, 1);
679 /* enable rirb dma and response irq */
680 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
681 spin_unlock_irq(&chip->reg_lock);
682 }
683
azx_free_cmd_io(struct azx * chip)684 static void azx_free_cmd_io(struct azx *chip)
685 {
686 spin_lock_irq(&chip->reg_lock);
687 /* disable ringbuffer DMAs */
688 azx_writeb(chip, RIRBCTL, 0);
689 azx_writeb(chip, CORBCTL, 0);
690 spin_unlock_irq(&chip->reg_lock);
691 }
692
azx_command_addr(u32 cmd)693 static unsigned int azx_command_addr(u32 cmd)
694 {
695 unsigned int addr = cmd >> 28;
696
697 if (addr >= AZX_MAX_CODECS) {
698 snd_BUG();
699 addr = 0;
700 }
701
702 return addr;
703 }
704
azx_response_addr(u32 res)705 static unsigned int azx_response_addr(u32 res)
706 {
707 unsigned int addr = res & 0xf;
708
709 if (addr >= AZX_MAX_CODECS) {
710 snd_BUG();
711 addr = 0;
712 }
713
714 return addr;
715 }
716
717 /* send a command */
azx_corb_send_cmd(struct hda_bus * bus,u32 val)718 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
719 {
720 struct azx *chip = bus->private_data;
721 unsigned int addr = azx_command_addr(val);
722 unsigned int wp;
723
724 spin_lock_irq(&chip->reg_lock);
725
726 /* add command to corb */
727 wp = azx_readb(chip, CORBWP);
728 wp++;
729 wp %= ICH6_MAX_CORB_ENTRIES;
730
731 chip->rirb.cmds[addr]++;
732 chip->corb.buf[wp] = cpu_to_le32(val);
733 azx_writel(chip, CORBWP, wp);
734
735 spin_unlock_irq(&chip->reg_lock);
736
737 return 0;
738 }
739
740 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
741
742 /* retrieve RIRB entry - called from interrupt handler */
azx_update_rirb(struct azx * chip)743 static void azx_update_rirb(struct azx *chip)
744 {
745 unsigned int rp, wp;
746 unsigned int addr;
747 u32 res, res_ex;
748
749 wp = azx_readb(chip, RIRBWP);
750 if (wp == chip->rirb.wp)
751 return;
752 chip->rirb.wp = wp;
753
754 while (chip->rirb.rp != wp) {
755 chip->rirb.rp++;
756 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
757
758 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
759 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
760 res = le32_to_cpu(chip->rirb.buf[rp]);
761 addr = azx_response_addr(res_ex);
762 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
763 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
764 else if (chip->rirb.cmds[addr]) {
765 chip->rirb.res[addr] = res;
766 smp_wmb();
767 chip->rirb.cmds[addr]--;
768 } else
769 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
770 "last cmd=%#08x\n",
771 res, res_ex,
772 chip->last_cmd[addr]);
773 }
774 }
775
776 /* receive a response */
azx_rirb_get_response(struct hda_bus * bus,unsigned int addr)777 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
778 unsigned int addr)
779 {
780 struct azx *chip = bus->private_data;
781 unsigned long timeout;
782 int do_poll = 0;
783
784 again:
785 timeout = jiffies + msecs_to_jiffies(1000);
786 for (;;) {
787 if (chip->polling_mode || do_poll) {
788 spin_lock_irq(&chip->reg_lock);
789 azx_update_rirb(chip);
790 spin_unlock_irq(&chip->reg_lock);
791 }
792 if (!chip->rirb.cmds[addr]) {
793 smp_rmb();
794 bus->rirb_error = 0;
795
796 if (!do_poll)
797 chip->poll_count = 0;
798 return chip->rirb.res[addr]; /* the last value */
799 }
800 if (time_after(jiffies, timeout))
801 break;
802 if (bus->needs_damn_long_delay)
803 msleep(2); /* temporary workaround */
804 else {
805 udelay(10);
806 cond_resched();
807 }
808 }
809
810 if (!chip->polling_mode && chip->poll_count < 2) {
811 snd_printdd(SFX "azx_get_response timeout, "
812 "polling the codec once: last cmd=0x%08x\n",
813 chip->last_cmd[addr]);
814 do_poll = 1;
815 chip->poll_count++;
816 goto again;
817 }
818
819
820 if (!chip->polling_mode) {
821 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
822 "switching to polling mode: last cmd=0x%08x\n",
823 chip->last_cmd[addr]);
824 chip->polling_mode = 1;
825 goto again;
826 }
827
828 if (chip->msi) {
829 snd_printk(KERN_WARNING SFX "No response from codec, "
830 "disabling MSI: last cmd=0x%08x\n",
831 chip->last_cmd[addr]);
832 free_irq(chip->irq, chip);
833 chip->irq = -1;
834 pci_disable_msi(chip->pci);
835 chip->msi = 0;
836 if (azx_acquire_irq(chip, 1) < 0) {
837 bus->rirb_error = 1;
838 return -1;
839 }
840 goto again;
841 }
842
843 if (chip->probing) {
844 /* If this critical timeout happens during the codec probing
845 * phase, this is likely an access to a non-existing codec
846 * slot. Better to return an error and reset the system.
847 */
848 return -1;
849 }
850
851 /* a fatal communication error; need either to reset or to fallback
852 * to the single_cmd mode
853 */
854 bus->rirb_error = 1;
855 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
856 bus->response_reset = 1;
857 return -1; /* give a chance to retry */
858 }
859
860 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
861 "switching to single_cmd mode: last cmd=0x%08x\n",
862 chip->last_cmd[addr]);
863 chip->single_cmd = 1;
864 bus->response_reset = 0;
865 /* release CORB/RIRB */
866 azx_free_cmd_io(chip);
867 /* disable unsolicited responses */
868 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
869 return -1;
870 }
871
872 /*
873 * Use the single immediate command instead of CORB/RIRB for simplicity
874 *
875 * Note: according to Intel, this is not preferred use. The command was
876 * intended for the BIOS only, and may get confused with unsolicited
877 * responses. So, we shouldn't use it for normal operation from the
878 * driver.
879 * I left the codes, however, for debugging/testing purposes.
880 */
881
882 /* receive a response */
azx_single_wait_for_response(struct azx * chip,unsigned int addr)883 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
884 {
885 int timeout = 50;
886
887 while (timeout--) {
888 /* check IRV busy bit */
889 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
890 /* reuse rirb.res as the response return value */
891 chip->rirb.res[addr] = azx_readl(chip, IR);
892 return 0;
893 }
894 udelay(1);
895 }
896 if (printk_ratelimit())
897 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
898 azx_readw(chip, IRS));
899 chip->rirb.res[addr] = -1;
900 return -EIO;
901 }
902
903 /* send a command */
azx_single_send_cmd(struct hda_bus * bus,u32 val)904 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
905 {
906 struct azx *chip = bus->private_data;
907 unsigned int addr = azx_command_addr(val);
908 int timeout = 50;
909
910 bus->rirb_error = 0;
911 while (timeout--) {
912 /* check ICB busy bit */
913 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
914 /* Clear IRV valid bit */
915 azx_writew(chip, IRS, azx_readw(chip, IRS) |
916 ICH6_IRS_VALID);
917 azx_writel(chip, IC, val);
918 azx_writew(chip, IRS, azx_readw(chip, IRS) |
919 ICH6_IRS_BUSY);
920 return azx_single_wait_for_response(chip, addr);
921 }
922 udelay(1);
923 }
924 if (printk_ratelimit())
925 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
926 azx_readw(chip, IRS), val);
927 return -EIO;
928 }
929
930 /* receive a response */
azx_single_get_response(struct hda_bus * bus,unsigned int addr)931 static unsigned int azx_single_get_response(struct hda_bus *bus,
932 unsigned int addr)
933 {
934 struct azx *chip = bus->private_data;
935 return chip->rirb.res[addr];
936 }
937
938 /*
939 * The below are the main callbacks from hda_codec.
940 *
941 * They are just the skeleton to call sub-callbacks according to the
942 * current setting of chip->single_cmd.
943 */
944
945 /* send a command */
azx_send_cmd(struct hda_bus * bus,unsigned int val)946 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
947 {
948 struct azx *chip = bus->private_data;
949
950 chip->last_cmd[azx_command_addr(val)] = val;
951 if (chip->single_cmd)
952 return azx_single_send_cmd(bus, val);
953 else
954 return azx_corb_send_cmd(bus, val);
955 }
956
957 /* get a response */
azx_get_response(struct hda_bus * bus,unsigned int addr)958 static unsigned int azx_get_response(struct hda_bus *bus,
959 unsigned int addr)
960 {
961 struct azx *chip = bus->private_data;
962 if (chip->single_cmd)
963 return azx_single_get_response(bus, addr);
964 else
965 return azx_rirb_get_response(bus, addr);
966 }
967
968 #ifdef CONFIG_SND_HDA_POWER_SAVE
969 static void azx_power_notify(struct hda_bus *bus);
970 #endif
971
972 /* reset codec link */
azx_reset(struct azx * chip,int full_reset)973 static int azx_reset(struct azx *chip, int full_reset)
974 {
975 int count;
976
977 if (!full_reset)
978 goto __skip;
979
980 /* clear STATESTS */
981 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
982
983 /* reset controller */
984 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
985
986 count = 50;
987 while (azx_readb(chip, GCTL) && --count)
988 msleep(1);
989
990 /* delay for >= 100us for codec PLL to settle per spec
991 * Rev 0.9 section 5.5.1
992 */
993 msleep(1);
994
995 /* Bring controller out of reset */
996 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
997
998 count = 50;
999 while (!azx_readb(chip, GCTL) && --count)
1000 msleep(1);
1001
1002 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1003 msleep(1);
1004
1005 __skip:
1006 /* check to see if controller is ready */
1007 if (!azx_readb(chip, GCTL)) {
1008 snd_printd(SFX "azx_reset: controller not ready!\n");
1009 return -EBUSY;
1010 }
1011
1012 /* Accept unsolicited responses */
1013 if (!chip->single_cmd)
1014 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1015 ICH6_GCTL_UNSOL);
1016
1017 /* detect codecs */
1018 if (!chip->codec_mask) {
1019 chip->codec_mask = azx_readw(chip, STATESTS);
1020 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1021 }
1022
1023 return 0;
1024 }
1025
1026
1027 /*
1028 * Lowlevel interface
1029 */
1030
1031 /* enable interrupts */
azx_int_enable(struct azx * chip)1032 static void azx_int_enable(struct azx *chip)
1033 {
1034 /* enable controller CIE and GIE */
1035 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1036 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1037 }
1038
1039 /* disable interrupts */
azx_int_disable(struct azx * chip)1040 static void azx_int_disable(struct azx *chip)
1041 {
1042 int i;
1043
1044 /* disable interrupts in stream descriptor */
1045 for (i = 0; i < chip->num_streams; i++) {
1046 struct azx_dev *azx_dev = &chip->azx_dev[i];
1047 azx_sd_writeb(azx_dev, SD_CTL,
1048 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1049 }
1050
1051 /* disable SIE for all streams */
1052 azx_writeb(chip, INTCTL, 0);
1053
1054 /* disable controller CIE and GIE */
1055 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1056 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1057 }
1058
1059 /* clear interrupts */
azx_int_clear(struct azx * chip)1060 static void azx_int_clear(struct azx *chip)
1061 {
1062 int i;
1063
1064 /* clear stream status */
1065 for (i = 0; i < chip->num_streams; i++) {
1066 struct azx_dev *azx_dev = &chip->azx_dev[i];
1067 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1068 }
1069
1070 /* clear STATESTS */
1071 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1072
1073 /* clear rirb status */
1074 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1075
1076 /* clear int status */
1077 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1078 }
1079
1080 /* start a stream */
azx_stream_start(struct azx * chip,struct azx_dev * azx_dev)1081 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1082 {
1083 /*
1084 * Before stream start, initialize parameter
1085 */
1086 azx_dev->insufficient = 1;
1087
1088 /* enable SIE */
1089 azx_writel(chip, INTCTL,
1090 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1091 /* set DMA start and interrupt mask */
1092 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1093 SD_CTL_DMA_START | SD_INT_MASK);
1094 }
1095
1096 /* stop DMA */
azx_stream_clear(struct azx * chip,struct azx_dev * azx_dev)1097 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1098 {
1099 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1100 ~(SD_CTL_DMA_START | SD_INT_MASK));
1101 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1102 }
1103
1104 /* stop a stream */
azx_stream_stop(struct azx * chip,struct azx_dev * azx_dev)1105 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1106 {
1107 azx_stream_clear(chip, azx_dev);
1108 /* disable SIE */
1109 azx_writel(chip, INTCTL,
1110 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1111 }
1112
1113
1114 /*
1115 * reset and start the controller registers
1116 */
azx_init_chip(struct azx * chip,int full_reset)1117 static void azx_init_chip(struct azx *chip, int full_reset)
1118 {
1119 if (chip->initialized)
1120 return;
1121
1122 /* reset controller */
1123 azx_reset(chip, full_reset);
1124
1125 /* initialize interrupts */
1126 azx_int_clear(chip);
1127 azx_int_enable(chip);
1128
1129 /* initialize the codec command I/O */
1130 if (!chip->single_cmd)
1131 azx_init_cmd_io(chip);
1132
1133 /* program the position buffer */
1134 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1135 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1136
1137 chip->initialized = 1;
1138 }
1139
1140 /*
1141 * initialize the PCI registers
1142 */
1143 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)1144 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1145 unsigned char mask, unsigned char val)
1146 {
1147 unsigned char data;
1148
1149 pci_read_config_byte(pci, reg, &data);
1150 data &= ~mask;
1151 data |= (val & mask);
1152 pci_write_config_byte(pci, reg, data);
1153 }
1154
azx_init_pci(struct azx * chip)1155 static void azx_init_pci(struct azx *chip)
1156 {
1157 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1158 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1159 * Ensuring these bits are 0 clears playback static on some HD Audio
1160 * codecs.
1161 * The PCI register TCSEL is defined in the Intel manuals.
1162 */
1163 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1164 snd_printdd(SFX "Clearing TCSEL\n");
1165 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1166 }
1167
1168 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1169 * we need to enable snoop.
1170 */
1171 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1172 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1173 update_pci_byte(chip->pci,
1174 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1175 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1176 }
1177
1178 /* For NVIDIA HDA, enable snoop */
1179 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1180 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1181 update_pci_byte(chip->pci,
1182 NVIDIA_HDA_TRANSREG_ADDR,
1183 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1184 update_pci_byte(chip->pci,
1185 NVIDIA_HDA_ISTRM_COH,
1186 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1187 update_pci_byte(chip->pci,
1188 NVIDIA_HDA_OSTRM_COH,
1189 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1190 }
1191
1192 /* Enable SCH/PCH snoop if needed */
1193 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1194 unsigned short snoop;
1195 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1196 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1197 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1198 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1199 if (!azx_snoop(chip))
1200 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1201 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1202 pci_read_config_word(chip->pci,
1203 INTEL_SCH_HDA_DEVC, &snoop);
1204 }
1205 snd_printdd(SFX "SCH snoop: %s\n",
1206 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1207 ? "Disabled" : "Enabled");
1208 }
1209 }
1210
1211
1212 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1213
1214 /*
1215 * interrupt handler
1216 */
azx_interrupt(int irq,void * dev_id)1217 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1218 {
1219 struct azx *chip = dev_id;
1220 struct azx_dev *azx_dev;
1221 u32 status;
1222 u8 sd_status;
1223 int i, ok;
1224
1225 spin_lock(&chip->reg_lock);
1226
1227 status = azx_readl(chip, INTSTS);
1228 if (status == 0) {
1229 spin_unlock(&chip->reg_lock);
1230 return IRQ_NONE;
1231 }
1232
1233 for (i = 0; i < chip->num_streams; i++) {
1234 azx_dev = &chip->azx_dev[i];
1235 if (status & azx_dev->sd_int_sta_mask) {
1236 sd_status = azx_sd_readb(azx_dev, SD_STS);
1237 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1238 if (!azx_dev->substream || !azx_dev->running ||
1239 !(sd_status & SD_INT_COMPLETE))
1240 continue;
1241 /* check whether this IRQ is really acceptable */
1242 ok = azx_position_ok(chip, azx_dev);
1243 if (ok == 1) {
1244 azx_dev->irq_pending = 0;
1245 spin_unlock(&chip->reg_lock);
1246 snd_pcm_period_elapsed(azx_dev->substream);
1247 spin_lock(&chip->reg_lock);
1248 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1249 /* bogus IRQ, process it later */
1250 azx_dev->irq_pending = 1;
1251 queue_work(chip->bus->workq,
1252 &chip->irq_pending_work);
1253 }
1254 }
1255 }
1256
1257 /* clear rirb int */
1258 status = azx_readb(chip, RIRBSTS);
1259 if (status & RIRB_INT_MASK) {
1260 if (status & RIRB_INT_RESPONSE) {
1261 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1262 udelay(80);
1263 azx_update_rirb(chip);
1264 }
1265 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1266 }
1267
1268 #if 0
1269 /* clear state status int */
1270 if (azx_readb(chip, STATESTS) & 0x04)
1271 azx_writeb(chip, STATESTS, 0x04);
1272 #endif
1273 spin_unlock(&chip->reg_lock);
1274
1275 return IRQ_HANDLED;
1276 }
1277
1278
1279 /*
1280 * set up a BDL entry
1281 */
setup_bdle(struct snd_pcm_substream * substream,struct azx_dev * azx_dev,u32 ** bdlp,int ofs,int size,int with_ioc)1282 static int setup_bdle(struct snd_pcm_substream *substream,
1283 struct azx_dev *azx_dev, u32 **bdlp,
1284 int ofs, int size, int with_ioc)
1285 {
1286 u32 *bdl = *bdlp;
1287
1288 while (size > 0) {
1289 dma_addr_t addr;
1290 int chunk;
1291
1292 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1293 return -EINVAL;
1294
1295 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1296 /* program the address field of the BDL entry */
1297 bdl[0] = cpu_to_le32((u32)addr);
1298 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1299 /* program the size field of the BDL entry */
1300 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1301 bdl[2] = cpu_to_le32(chunk);
1302 /* program the IOC to enable interrupt
1303 * only when the whole fragment is processed
1304 */
1305 size -= chunk;
1306 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1307 bdl += 4;
1308 azx_dev->frags++;
1309 ofs += chunk;
1310 }
1311 *bdlp = bdl;
1312 return ofs;
1313 }
1314
1315 /*
1316 * set up BDL entries
1317 */
azx_setup_periods(struct azx * chip,struct snd_pcm_substream * substream,struct azx_dev * azx_dev)1318 static int azx_setup_periods(struct azx *chip,
1319 struct snd_pcm_substream *substream,
1320 struct azx_dev *azx_dev)
1321 {
1322 u32 *bdl;
1323 int i, ofs, periods, period_bytes;
1324 int pos_adj;
1325
1326 /* reset BDL address */
1327 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1328 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1329
1330 period_bytes = azx_dev->period_bytes;
1331 periods = azx_dev->bufsize / period_bytes;
1332
1333 /* program the initial BDL entries */
1334 bdl = (u32 *)azx_dev->bdl.area;
1335 ofs = 0;
1336 azx_dev->frags = 0;
1337 pos_adj = bdl_pos_adj[chip->dev_index];
1338 if (pos_adj > 0) {
1339 struct snd_pcm_runtime *runtime = substream->runtime;
1340 int pos_align = pos_adj;
1341 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1342 if (!pos_adj)
1343 pos_adj = pos_align;
1344 else
1345 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1346 pos_align;
1347 pos_adj = frames_to_bytes(runtime, pos_adj);
1348 if (pos_adj >= period_bytes) {
1349 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1350 bdl_pos_adj[chip->dev_index]);
1351 pos_adj = 0;
1352 } else {
1353 ofs = setup_bdle(substream, azx_dev,
1354 &bdl, ofs, pos_adj,
1355 !substream->runtime->no_period_wakeup);
1356 if (ofs < 0)
1357 goto error;
1358 }
1359 } else
1360 pos_adj = 0;
1361 for (i = 0; i < periods; i++) {
1362 if (i == periods - 1 && pos_adj)
1363 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1364 period_bytes - pos_adj, 0);
1365 else
1366 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1367 period_bytes,
1368 !substream->runtime->no_period_wakeup);
1369 if (ofs < 0)
1370 goto error;
1371 }
1372 return 0;
1373
1374 error:
1375 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1376 azx_dev->bufsize, period_bytes);
1377 return -EINVAL;
1378 }
1379
1380 /* reset stream */
azx_stream_reset(struct azx * chip,struct azx_dev * azx_dev)1381 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1382 {
1383 unsigned char val;
1384 int timeout;
1385
1386 azx_stream_clear(chip, azx_dev);
1387
1388 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1389 SD_CTL_STREAM_RESET);
1390 udelay(3);
1391 timeout = 300;
1392 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1393 --timeout)
1394 ;
1395 val &= ~SD_CTL_STREAM_RESET;
1396 azx_sd_writeb(azx_dev, SD_CTL, val);
1397 udelay(3);
1398
1399 timeout = 300;
1400 /* waiting for hardware to report that the stream is out of reset */
1401 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1402 --timeout)
1403 ;
1404
1405 /* reset first position - may not be synced with hw at this time */
1406 *azx_dev->posbuf = 0;
1407 }
1408
1409 /*
1410 * set up the SD for streaming
1411 */
azx_setup_controller(struct azx * chip,struct azx_dev * azx_dev)1412 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1413 {
1414 unsigned int val;
1415 /* make sure the run bit is zero for SD */
1416 azx_stream_clear(chip, azx_dev);
1417 /* program the stream_tag */
1418 val = azx_sd_readl(azx_dev, SD_CTL);
1419 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1420 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1421 if (!azx_snoop(chip))
1422 val |= SD_CTL_TRAFFIC_PRIO;
1423 azx_sd_writel(azx_dev, SD_CTL, val);
1424
1425 /* program the length of samples in cyclic buffer */
1426 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1427
1428 /* program the stream format */
1429 /* this value needs to be the same as the one programmed */
1430 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1431
1432 /* program the stream LVI (last valid index) of the BDL */
1433 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1434
1435 /* program the BDL address */
1436 /* lower BDL address */
1437 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1438 /* upper BDL address */
1439 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1440
1441 /* enable the position buffer */
1442 if (chip->position_fix[0] != POS_FIX_LPIB ||
1443 chip->position_fix[1] != POS_FIX_LPIB) {
1444 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1445 azx_writel(chip, DPLBASE,
1446 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1447 }
1448
1449 /* set the interrupt enable bits in the descriptor control register */
1450 azx_sd_writel(azx_dev, SD_CTL,
1451 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1452
1453 return 0;
1454 }
1455
1456 /*
1457 * Probe the given codec address
1458 */
probe_codec(struct azx * chip,int addr)1459 static int probe_codec(struct azx *chip, int addr)
1460 {
1461 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1462 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1463 unsigned int res;
1464
1465 mutex_lock(&chip->bus->cmd_mutex);
1466 chip->probing = 1;
1467 azx_send_cmd(chip->bus, cmd);
1468 res = azx_get_response(chip->bus, addr);
1469 chip->probing = 0;
1470 mutex_unlock(&chip->bus->cmd_mutex);
1471 if (res == -1)
1472 return -EIO;
1473 snd_printdd(SFX "codec #%d probed OK\n", addr);
1474 return 0;
1475 }
1476
1477 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1478 struct hda_pcm *cpcm);
1479 static void azx_stop_chip(struct azx *chip);
1480
azx_bus_reset(struct hda_bus * bus)1481 static void azx_bus_reset(struct hda_bus *bus)
1482 {
1483 struct azx *chip = bus->private_data;
1484
1485 bus->in_reset = 1;
1486 azx_stop_chip(chip);
1487 azx_init_chip(chip, 1);
1488 #ifdef CONFIG_PM
1489 if (chip->initialized) {
1490 struct azx_pcm *p;
1491 list_for_each_entry(p, &chip->pcm_list, list)
1492 snd_pcm_suspend_all(p->pcm);
1493 snd_hda_suspend(chip->bus);
1494 snd_hda_resume(chip->bus);
1495 }
1496 #endif
1497 bus->in_reset = 0;
1498 }
1499
1500 /*
1501 * Codec initialization
1502 */
1503
1504 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1505 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1506 [AZX_DRIVER_NVIDIA] = 8,
1507 [AZX_DRIVER_TERA] = 1,
1508 };
1509
azx_codec_create(struct azx * chip,const char * model)1510 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1511 {
1512 struct hda_bus_template bus_temp;
1513 int c, codecs, err;
1514 int max_slots;
1515
1516 memset(&bus_temp, 0, sizeof(bus_temp));
1517 bus_temp.private_data = chip;
1518 bus_temp.modelname = model;
1519 bus_temp.pci = chip->pci;
1520 bus_temp.ops.command = azx_send_cmd;
1521 bus_temp.ops.get_response = azx_get_response;
1522 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1523 bus_temp.ops.bus_reset = azx_bus_reset;
1524 #ifdef CONFIG_SND_HDA_POWER_SAVE
1525 bus_temp.power_save = &power_save;
1526 bus_temp.ops.pm_notify = azx_power_notify;
1527 #endif
1528
1529 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1530 if (err < 0)
1531 return err;
1532
1533 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1534 snd_printd(SFX "Enable delay in RIRB handling\n");
1535 chip->bus->needs_damn_long_delay = 1;
1536 }
1537
1538 codecs = 0;
1539 max_slots = azx_max_codecs[chip->driver_type];
1540 if (!max_slots)
1541 max_slots = AZX_DEFAULT_CODECS;
1542
1543 /* First try to probe all given codec slots */
1544 for (c = 0; c < max_slots; c++) {
1545 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1546 if (probe_codec(chip, c) < 0) {
1547 /* Some BIOSen give you wrong codec addresses
1548 * that don't exist
1549 */
1550 snd_printk(KERN_WARNING SFX
1551 "Codec #%d probe error; "
1552 "disabling it...\n", c);
1553 chip->codec_mask &= ~(1 << c);
1554 /* More badly, accessing to a non-existing
1555 * codec often screws up the controller chip,
1556 * and disturbs the further communications.
1557 * Thus if an error occurs during probing,
1558 * better to reset the controller chip to
1559 * get back to the sanity state.
1560 */
1561 azx_stop_chip(chip);
1562 azx_init_chip(chip, 1);
1563 }
1564 }
1565 }
1566
1567 /* AMD chipsets often cause the communication stalls upon certain
1568 * sequence like the pin-detection. It seems that forcing the synced
1569 * access works around the stall. Grrr...
1570 */
1571 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1572 snd_printd(SFX "Enable sync_write for stable communication\n");
1573 chip->bus->sync_write = 1;
1574 chip->bus->allow_bus_reset = 1;
1575 }
1576
1577 /* Then create codec instances */
1578 for (c = 0; c < max_slots; c++) {
1579 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1580 struct hda_codec *codec;
1581 err = snd_hda_codec_new(chip->bus, c, &codec);
1582 if (err < 0)
1583 continue;
1584 codec->beep_mode = chip->beep_mode;
1585 codecs++;
1586 }
1587 }
1588 if (!codecs) {
1589 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1590 return -ENXIO;
1591 }
1592 return 0;
1593 }
1594
1595 /* configure each codec instance */
azx_codec_configure(struct azx * chip)1596 static int __devinit azx_codec_configure(struct azx *chip)
1597 {
1598 struct hda_codec *codec;
1599 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1600 snd_hda_codec_configure(codec);
1601 }
1602 return 0;
1603 }
1604
1605
1606 /*
1607 * PCM support
1608 */
1609
1610 /* assign a stream for the PCM */
1611 static inline struct azx_dev *
azx_assign_device(struct azx * chip,struct snd_pcm_substream * substream)1612 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1613 {
1614 int dev, i, nums;
1615 struct azx_dev *res = NULL;
1616 /* make a non-zero unique key for the substream */
1617 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1618 (substream->stream + 1);
1619
1620 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1621 dev = chip->playback_index_offset;
1622 nums = chip->playback_streams;
1623 } else {
1624 dev = chip->capture_index_offset;
1625 nums = chip->capture_streams;
1626 }
1627 for (i = 0; i < nums; i++, dev++)
1628 if (!chip->azx_dev[dev].opened) {
1629 res = &chip->azx_dev[dev];
1630 if (res->assigned_key == key)
1631 break;
1632 }
1633 if (res) {
1634 res->opened = 1;
1635 res->assigned_key = key;
1636 }
1637 return res;
1638 }
1639
1640 /* release the assigned stream */
azx_release_device(struct azx_dev * azx_dev)1641 static inline void azx_release_device(struct azx_dev *azx_dev)
1642 {
1643 azx_dev->opened = 0;
1644 }
1645
1646 static struct snd_pcm_hardware azx_pcm_hw = {
1647 .info = (SNDRV_PCM_INFO_MMAP |
1648 SNDRV_PCM_INFO_INTERLEAVED |
1649 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1650 SNDRV_PCM_INFO_MMAP_VALID |
1651 /* No full-resume yet implemented */
1652 /* SNDRV_PCM_INFO_RESUME |*/
1653 SNDRV_PCM_INFO_PAUSE |
1654 SNDRV_PCM_INFO_SYNC_START |
1655 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1656 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1657 .rates = SNDRV_PCM_RATE_48000,
1658 .rate_min = 48000,
1659 .rate_max = 48000,
1660 .channels_min = 2,
1661 .channels_max = 2,
1662 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1663 .period_bytes_min = 128,
1664 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1665 .periods_min = 2,
1666 .periods_max = AZX_MAX_FRAG,
1667 .fifo_size = 0,
1668 };
1669
azx_pcm_open(struct snd_pcm_substream * substream)1670 static int azx_pcm_open(struct snd_pcm_substream *substream)
1671 {
1672 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1673 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1674 struct azx *chip = apcm->chip;
1675 struct azx_dev *azx_dev;
1676 struct snd_pcm_runtime *runtime = substream->runtime;
1677 unsigned long flags;
1678 int err;
1679 int buff_step;
1680
1681 mutex_lock(&chip->open_mutex);
1682 azx_dev = azx_assign_device(chip, substream);
1683 if (azx_dev == NULL) {
1684 mutex_unlock(&chip->open_mutex);
1685 return -EBUSY;
1686 }
1687 runtime->hw = azx_pcm_hw;
1688 runtime->hw.channels_min = hinfo->channels_min;
1689 runtime->hw.channels_max = hinfo->channels_max;
1690 runtime->hw.formats = hinfo->formats;
1691 runtime->hw.rates = hinfo->rates;
1692 snd_pcm_limit_hw_rates(runtime);
1693 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1694 if (chip->align_buffer_size)
1695 /* constrain buffer sizes to be multiple of 128
1696 bytes. This is more efficient in terms of memory
1697 access but isn't required by the HDA spec and
1698 prevents users from specifying exact period/buffer
1699 sizes. For example for 44.1kHz, a period size set
1700 to 20ms will be rounded to 19.59ms. */
1701 buff_step = 128;
1702 else
1703 /* Don't enforce steps on buffer sizes, still need to
1704 be multiple of 4 bytes (HDA spec). Tested on Intel
1705 HDA controllers, may not work on all devices where
1706 option needs to be disabled */
1707 buff_step = 4;
1708
1709 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1710 buff_step);
1711 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1712 buff_step);
1713 snd_hda_power_up(apcm->codec);
1714 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1715 if (err < 0) {
1716 azx_release_device(azx_dev);
1717 snd_hda_power_down(apcm->codec);
1718 mutex_unlock(&chip->open_mutex);
1719 return err;
1720 }
1721 snd_pcm_limit_hw_rates(runtime);
1722 /* sanity check */
1723 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1724 snd_BUG_ON(!runtime->hw.channels_max) ||
1725 snd_BUG_ON(!runtime->hw.formats) ||
1726 snd_BUG_ON(!runtime->hw.rates)) {
1727 azx_release_device(azx_dev);
1728 hinfo->ops.close(hinfo, apcm->codec, substream);
1729 snd_hda_power_down(apcm->codec);
1730 mutex_unlock(&chip->open_mutex);
1731 return -EINVAL;
1732 }
1733 spin_lock_irqsave(&chip->reg_lock, flags);
1734 azx_dev->substream = substream;
1735 azx_dev->running = 0;
1736 spin_unlock_irqrestore(&chip->reg_lock, flags);
1737
1738 runtime->private_data = azx_dev;
1739 snd_pcm_set_sync(substream);
1740 mutex_unlock(&chip->open_mutex);
1741 return 0;
1742 }
1743
azx_pcm_close(struct snd_pcm_substream * substream)1744 static int azx_pcm_close(struct snd_pcm_substream *substream)
1745 {
1746 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1747 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1748 struct azx *chip = apcm->chip;
1749 struct azx_dev *azx_dev = get_azx_dev(substream);
1750 unsigned long flags;
1751
1752 mutex_lock(&chip->open_mutex);
1753 spin_lock_irqsave(&chip->reg_lock, flags);
1754 azx_dev->substream = NULL;
1755 azx_dev->running = 0;
1756 spin_unlock_irqrestore(&chip->reg_lock, flags);
1757 azx_release_device(azx_dev);
1758 hinfo->ops.close(hinfo, apcm->codec, substream);
1759 snd_hda_power_down(apcm->codec);
1760 mutex_unlock(&chip->open_mutex);
1761 return 0;
1762 }
1763
azx_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1764 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1765 struct snd_pcm_hw_params *hw_params)
1766 {
1767 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1768 struct azx *chip = apcm->chip;
1769 struct snd_pcm_runtime *runtime = substream->runtime;
1770 struct azx_dev *azx_dev = get_azx_dev(substream);
1771 int ret;
1772
1773 mark_runtime_wc(chip, azx_dev, runtime, false);
1774 azx_dev->bufsize = 0;
1775 azx_dev->period_bytes = 0;
1776 azx_dev->format_val = 0;
1777 ret = snd_pcm_lib_malloc_pages(substream,
1778 params_buffer_bytes(hw_params));
1779 if (ret < 0)
1780 return ret;
1781 mark_runtime_wc(chip, azx_dev, runtime, true);
1782 return ret;
1783 }
1784
azx_pcm_hw_free(struct snd_pcm_substream * substream)1785 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1786 {
1787 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1788 struct azx_dev *azx_dev = get_azx_dev(substream);
1789 struct azx *chip = apcm->chip;
1790 struct snd_pcm_runtime *runtime = substream->runtime;
1791 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1792
1793 /* reset BDL address */
1794 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1795 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1796 azx_sd_writel(azx_dev, SD_CTL, 0);
1797 azx_dev->bufsize = 0;
1798 azx_dev->period_bytes = 0;
1799 azx_dev->format_val = 0;
1800
1801 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1802
1803 mark_runtime_wc(chip, azx_dev, runtime, false);
1804 return snd_pcm_lib_free_pages(substream);
1805 }
1806
azx_pcm_prepare(struct snd_pcm_substream * substream)1807 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1808 {
1809 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1810 struct azx *chip = apcm->chip;
1811 struct azx_dev *azx_dev = get_azx_dev(substream);
1812 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1813 struct snd_pcm_runtime *runtime = substream->runtime;
1814 unsigned int bufsize, period_bytes, format_val, stream_tag;
1815 int err;
1816 struct hda_spdif_out *spdif =
1817 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1818 unsigned short ctls = spdif ? spdif->ctls : 0;
1819
1820 azx_stream_reset(chip, azx_dev);
1821 format_val = snd_hda_calc_stream_format(runtime->rate,
1822 runtime->channels,
1823 runtime->format,
1824 hinfo->maxbps,
1825 ctls);
1826 if (!format_val) {
1827 snd_printk(KERN_ERR SFX
1828 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1829 runtime->rate, runtime->channels, runtime->format);
1830 return -EINVAL;
1831 }
1832
1833 bufsize = snd_pcm_lib_buffer_bytes(substream);
1834 period_bytes = snd_pcm_lib_period_bytes(substream);
1835
1836 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1837 bufsize, format_val);
1838
1839 if (bufsize != azx_dev->bufsize ||
1840 period_bytes != azx_dev->period_bytes ||
1841 format_val != azx_dev->format_val) {
1842 azx_dev->bufsize = bufsize;
1843 azx_dev->period_bytes = period_bytes;
1844 azx_dev->format_val = format_val;
1845 err = azx_setup_periods(chip, substream, azx_dev);
1846 if (err < 0)
1847 return err;
1848 }
1849
1850 /* wallclk has 24Mhz clock source */
1851 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1852 runtime->rate) * 1000);
1853 azx_setup_controller(chip, azx_dev);
1854 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1855 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1856 else
1857 azx_dev->fifo_size = 0;
1858
1859 stream_tag = azx_dev->stream_tag;
1860 /* CA-IBG chips need the playback stream starting from 1 */
1861 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1862 stream_tag > chip->capture_streams)
1863 stream_tag -= chip->capture_streams;
1864 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1865 azx_dev->format_val, substream);
1866 }
1867
azx_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1868 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1869 {
1870 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871 struct azx *chip = apcm->chip;
1872 struct azx_dev *azx_dev;
1873 struct snd_pcm_substream *s;
1874 int rstart = 0, start, nsync = 0, sbits = 0;
1875 int nwait, timeout;
1876
1877 switch (cmd) {
1878 case SNDRV_PCM_TRIGGER_START:
1879 rstart = 1;
1880 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1881 case SNDRV_PCM_TRIGGER_RESUME:
1882 start = 1;
1883 break;
1884 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1885 case SNDRV_PCM_TRIGGER_SUSPEND:
1886 case SNDRV_PCM_TRIGGER_STOP:
1887 start = 0;
1888 break;
1889 default:
1890 return -EINVAL;
1891 }
1892
1893 snd_pcm_group_for_each_entry(s, substream) {
1894 if (s->pcm->card != substream->pcm->card)
1895 continue;
1896 azx_dev = get_azx_dev(s);
1897 sbits |= 1 << azx_dev->index;
1898 nsync++;
1899 snd_pcm_trigger_done(s, substream);
1900 }
1901
1902 spin_lock(&chip->reg_lock);
1903 if (nsync > 1) {
1904 /* first, set SYNC bits of corresponding streams */
1905 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1906 azx_writel(chip, OLD_SSYNC,
1907 azx_readl(chip, OLD_SSYNC) | sbits);
1908 else
1909 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1910 }
1911 snd_pcm_group_for_each_entry(s, substream) {
1912 if (s->pcm->card != substream->pcm->card)
1913 continue;
1914 azx_dev = get_azx_dev(s);
1915 if (start) {
1916 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1917 if (!rstart)
1918 azx_dev->start_wallclk -=
1919 azx_dev->period_wallclk;
1920 azx_stream_start(chip, azx_dev);
1921 } else {
1922 azx_stream_stop(chip, azx_dev);
1923 }
1924 azx_dev->running = start;
1925 }
1926 spin_unlock(&chip->reg_lock);
1927 if (start) {
1928 if (nsync == 1)
1929 return 0;
1930 /* wait until all FIFOs get ready */
1931 for (timeout = 5000; timeout; timeout--) {
1932 nwait = 0;
1933 snd_pcm_group_for_each_entry(s, substream) {
1934 if (s->pcm->card != substream->pcm->card)
1935 continue;
1936 azx_dev = get_azx_dev(s);
1937 if (!(azx_sd_readb(azx_dev, SD_STS) &
1938 SD_STS_FIFO_READY))
1939 nwait++;
1940 }
1941 if (!nwait)
1942 break;
1943 cpu_relax();
1944 }
1945 } else {
1946 /* wait until all RUN bits are cleared */
1947 for (timeout = 5000; timeout; timeout--) {
1948 nwait = 0;
1949 snd_pcm_group_for_each_entry(s, substream) {
1950 if (s->pcm->card != substream->pcm->card)
1951 continue;
1952 azx_dev = get_azx_dev(s);
1953 if (azx_sd_readb(azx_dev, SD_CTL) &
1954 SD_CTL_DMA_START)
1955 nwait++;
1956 }
1957 if (!nwait)
1958 break;
1959 cpu_relax();
1960 }
1961 }
1962 if (nsync > 1) {
1963 spin_lock(&chip->reg_lock);
1964 /* reset SYNC bits */
1965 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1966 azx_writel(chip, OLD_SSYNC,
1967 azx_readl(chip, OLD_SSYNC) & ~sbits);
1968 else
1969 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1970 spin_unlock(&chip->reg_lock);
1971 }
1972 return 0;
1973 }
1974
1975 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)1976 static unsigned int azx_via_get_position(struct azx *chip,
1977 struct azx_dev *azx_dev)
1978 {
1979 unsigned int link_pos, mini_pos, bound_pos;
1980 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1981 unsigned int fifo_size;
1982
1983 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1984 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1985 /* Playback, no problem using link position */
1986 return link_pos;
1987 }
1988
1989 /* Capture */
1990 /* For new chipset,
1991 * use mod to get the DMA position just like old chipset
1992 */
1993 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1994 mod_dma_pos %= azx_dev->period_bytes;
1995
1996 /* azx_dev->fifo_size can't get FIFO size of in stream.
1997 * Get from base address + offset.
1998 */
1999 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2000
2001 if (azx_dev->insufficient) {
2002 /* Link position never gather than FIFO size */
2003 if (link_pos <= fifo_size)
2004 return 0;
2005
2006 azx_dev->insufficient = 0;
2007 }
2008
2009 if (link_pos <= fifo_size)
2010 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2011 else
2012 mini_pos = link_pos - fifo_size;
2013
2014 /* Find nearest previous boudary */
2015 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2016 mod_link_pos = link_pos % azx_dev->period_bytes;
2017 if (mod_link_pos >= fifo_size)
2018 bound_pos = link_pos - mod_link_pos;
2019 else if (mod_dma_pos >= mod_mini_pos)
2020 bound_pos = mini_pos - mod_mini_pos;
2021 else {
2022 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2023 if (bound_pos >= azx_dev->bufsize)
2024 bound_pos = 0;
2025 }
2026
2027 /* Calculate real DMA position we want */
2028 return bound_pos + mod_dma_pos;
2029 }
2030
azx_get_position(struct azx * chip,struct azx_dev * azx_dev,bool with_check)2031 static unsigned int azx_get_position(struct azx *chip,
2032 struct azx_dev *azx_dev,
2033 bool with_check)
2034 {
2035 unsigned int pos;
2036 int stream = azx_dev->substream->stream;
2037
2038 switch (chip->position_fix[stream]) {
2039 case POS_FIX_LPIB:
2040 /* read LPIB */
2041 pos = azx_sd_readl(azx_dev, SD_LPIB);
2042 break;
2043 case POS_FIX_VIACOMBO:
2044 pos = azx_via_get_position(chip, azx_dev);
2045 break;
2046 default:
2047 /* use the position buffer */
2048 pos = le32_to_cpu(*azx_dev->posbuf);
2049 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2050 if (!pos || pos == (u32)-1) {
2051 printk(KERN_WARNING
2052 "hda-intel: Invalid position buffer, "
2053 "using LPIB read method instead.\n");
2054 chip->position_fix[stream] = POS_FIX_LPIB;
2055 pos = azx_sd_readl(azx_dev, SD_LPIB);
2056 } else
2057 chip->position_fix[stream] = POS_FIX_POSBUF;
2058 }
2059 break;
2060 }
2061
2062 if (pos >= azx_dev->bufsize)
2063 pos = 0;
2064 return pos;
2065 }
2066
azx_pcm_pointer(struct snd_pcm_substream * substream)2067 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2068 {
2069 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2070 struct azx *chip = apcm->chip;
2071 struct azx_dev *azx_dev = get_azx_dev(substream);
2072 return bytes_to_frames(substream->runtime,
2073 azx_get_position(chip, azx_dev, false));
2074 }
2075
2076 /*
2077 * Check whether the current DMA position is acceptable for updating
2078 * periods. Returns non-zero if it's OK.
2079 *
2080 * Many HD-audio controllers appear pretty inaccurate about
2081 * the update-IRQ timing. The IRQ is issued before actually the
2082 * data is processed. So, we need to process it afterwords in a
2083 * workqueue.
2084 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)2085 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2086 {
2087 u32 wallclk;
2088 unsigned int pos;
2089 int stream;
2090
2091 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2092 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2093 return -1; /* bogus (too early) interrupt */
2094
2095 stream = azx_dev->substream->stream;
2096 pos = azx_get_position(chip, azx_dev, true);
2097
2098 if (WARN_ONCE(!azx_dev->period_bytes,
2099 "hda-intel: zero azx_dev->period_bytes"))
2100 return -1; /* this shouldn't happen! */
2101 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2102 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2103 /* NG - it's below the first next period boundary */
2104 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2105 azx_dev->start_wallclk += wallclk;
2106 return 1; /* OK, it's fine */
2107 }
2108
2109 /*
2110 * The work for pending PCM period updates.
2111 */
azx_irq_pending_work(struct work_struct * work)2112 static void azx_irq_pending_work(struct work_struct *work)
2113 {
2114 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2115 int i, pending, ok;
2116
2117 if (!chip->irq_pending_warned) {
2118 printk(KERN_WARNING
2119 "hda-intel: IRQ timing workaround is activated "
2120 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2121 chip->card->number);
2122 chip->irq_pending_warned = 1;
2123 }
2124
2125 for (;;) {
2126 pending = 0;
2127 spin_lock_irq(&chip->reg_lock);
2128 for (i = 0; i < chip->num_streams; i++) {
2129 struct azx_dev *azx_dev = &chip->azx_dev[i];
2130 if (!azx_dev->irq_pending ||
2131 !azx_dev->substream ||
2132 !azx_dev->running)
2133 continue;
2134 ok = azx_position_ok(chip, azx_dev);
2135 if (ok > 0) {
2136 azx_dev->irq_pending = 0;
2137 spin_unlock(&chip->reg_lock);
2138 snd_pcm_period_elapsed(azx_dev->substream);
2139 spin_lock(&chip->reg_lock);
2140 } else if (ok < 0) {
2141 pending = 0; /* too early */
2142 } else
2143 pending++;
2144 }
2145 spin_unlock_irq(&chip->reg_lock);
2146 if (!pending)
2147 return;
2148 msleep(1);
2149 }
2150 }
2151
2152 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)2153 static void azx_clear_irq_pending(struct azx *chip)
2154 {
2155 int i;
2156
2157 spin_lock_irq(&chip->reg_lock);
2158 for (i = 0; i < chip->num_streams; i++)
2159 chip->azx_dev[i].irq_pending = 0;
2160 spin_unlock_irq(&chip->reg_lock);
2161 }
2162
2163 #ifdef CONFIG_X86
azx_pcm_mmap(struct snd_pcm_substream * substream,struct vm_area_struct * area)2164 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2165 struct vm_area_struct *area)
2166 {
2167 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2168 struct azx *chip = apcm->chip;
2169 if (!azx_snoop(chip))
2170 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2171 return snd_pcm_lib_default_mmap(substream, area);
2172 }
2173 #else
2174 #define azx_pcm_mmap NULL
2175 #endif
2176
2177 static struct snd_pcm_ops azx_pcm_ops = {
2178 .open = azx_pcm_open,
2179 .close = azx_pcm_close,
2180 .ioctl = snd_pcm_lib_ioctl,
2181 .hw_params = azx_pcm_hw_params,
2182 .hw_free = azx_pcm_hw_free,
2183 .prepare = azx_pcm_prepare,
2184 .trigger = azx_pcm_trigger,
2185 .pointer = azx_pcm_pointer,
2186 .mmap = azx_pcm_mmap,
2187 .page = snd_pcm_sgbuf_ops_page,
2188 };
2189
azx_pcm_free(struct snd_pcm * pcm)2190 static void azx_pcm_free(struct snd_pcm *pcm)
2191 {
2192 struct azx_pcm *apcm = pcm->private_data;
2193 if (apcm) {
2194 list_del(&apcm->list);
2195 kfree(apcm);
2196 }
2197 }
2198
2199 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2200
2201 static int
azx_attach_pcm_stream(struct hda_bus * bus,struct hda_codec * codec,struct hda_pcm * cpcm)2202 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2203 struct hda_pcm *cpcm)
2204 {
2205 struct azx *chip = bus->private_data;
2206 struct snd_pcm *pcm;
2207 struct azx_pcm *apcm;
2208 int pcm_dev = cpcm->device;
2209 unsigned int size;
2210 int s, err;
2211
2212 list_for_each_entry(apcm, &chip->pcm_list, list) {
2213 if (apcm->pcm->device == pcm_dev) {
2214 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2215 return -EBUSY;
2216 }
2217 }
2218 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2219 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2220 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2221 &pcm);
2222 if (err < 0)
2223 return err;
2224 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2225 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2226 if (apcm == NULL)
2227 return -ENOMEM;
2228 apcm->chip = chip;
2229 apcm->pcm = pcm;
2230 apcm->codec = codec;
2231 pcm->private_data = apcm;
2232 pcm->private_free = azx_pcm_free;
2233 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2234 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2235 list_add_tail(&apcm->list, &chip->pcm_list);
2236 cpcm->pcm = pcm;
2237 for (s = 0; s < 2; s++) {
2238 apcm->hinfo[s] = &cpcm->stream[s];
2239 if (cpcm->stream[s].substreams)
2240 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2241 }
2242 /* buffer pre-allocation */
2243 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2244 if (size > MAX_PREALLOC_SIZE)
2245 size = MAX_PREALLOC_SIZE;
2246 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2247 snd_dma_pci_data(chip->pci),
2248 size, MAX_PREALLOC_SIZE);
2249 return 0;
2250 }
2251
2252 /*
2253 * mixer creation - all stuff is implemented in hda module
2254 */
azx_mixer_create(struct azx * chip)2255 static int __devinit azx_mixer_create(struct azx *chip)
2256 {
2257 return snd_hda_build_controls(chip->bus);
2258 }
2259
2260
2261 /*
2262 * initialize SD streams
2263 */
azx_init_stream(struct azx * chip)2264 static int __devinit azx_init_stream(struct azx *chip)
2265 {
2266 int i;
2267
2268 /* initialize each stream (aka device)
2269 * assign the starting bdl address to each stream (device)
2270 * and initialize
2271 */
2272 for (i = 0; i < chip->num_streams; i++) {
2273 struct azx_dev *azx_dev = &chip->azx_dev[i];
2274 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2275 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2276 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2277 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2278 azx_dev->sd_int_sta_mask = 1 << i;
2279 /* stream tag: must be non-zero and unique */
2280 azx_dev->index = i;
2281 azx_dev->stream_tag = i + 1;
2282 }
2283
2284 return 0;
2285 }
2286
azx_acquire_irq(struct azx * chip,int do_disconnect)2287 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2288 {
2289 if (request_irq(chip->pci->irq, azx_interrupt,
2290 chip->msi ? 0 : IRQF_SHARED,
2291 KBUILD_MODNAME, chip)) {
2292 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2293 "disabling device\n", chip->pci->irq);
2294 if (do_disconnect)
2295 snd_card_disconnect(chip->card);
2296 return -1;
2297 }
2298 chip->irq = chip->pci->irq;
2299 pci_intx(chip->pci, !chip->msi);
2300 return 0;
2301 }
2302
2303
azx_stop_chip(struct azx * chip)2304 static void azx_stop_chip(struct azx *chip)
2305 {
2306 if (!chip->initialized)
2307 return;
2308
2309 /* disable interrupts */
2310 azx_int_disable(chip);
2311 azx_int_clear(chip);
2312
2313 /* disable CORB/RIRB */
2314 azx_free_cmd_io(chip);
2315
2316 /* disable position buffer */
2317 azx_writel(chip, DPLBASE, 0);
2318 azx_writel(chip, DPUBASE, 0);
2319
2320 chip->initialized = 0;
2321 }
2322
2323 #ifdef CONFIG_SND_HDA_POWER_SAVE
2324 /* power-up/down the controller */
azx_power_notify(struct hda_bus * bus)2325 static void azx_power_notify(struct hda_bus *bus)
2326 {
2327 struct azx *chip = bus->private_data;
2328 struct hda_codec *c;
2329 int power_on = 0;
2330
2331 list_for_each_entry(c, &bus->codec_list, list) {
2332 if (c->power_on) {
2333 power_on = 1;
2334 break;
2335 }
2336 }
2337 if (power_on)
2338 azx_init_chip(chip, 1);
2339 else if (chip->running && power_save_controller &&
2340 !bus->power_keep_link_on)
2341 azx_stop_chip(chip);
2342 }
2343 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2344
2345 #ifdef CONFIG_PM
2346 /*
2347 * power management
2348 */
2349
snd_hda_codecs_inuse(struct hda_bus * bus)2350 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2351 {
2352 struct hda_codec *codec;
2353
2354 list_for_each_entry(codec, &bus->codec_list, list) {
2355 if (snd_hda_codec_needs_resume(codec))
2356 return 1;
2357 }
2358 return 0;
2359 }
2360
azx_suspend(struct pci_dev * pci,pm_message_t state)2361 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2362 {
2363 struct snd_card *card = pci_get_drvdata(pci);
2364 struct azx *chip = card->private_data;
2365 struct azx_pcm *p;
2366
2367 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2368 azx_clear_irq_pending(chip);
2369 list_for_each_entry(p, &chip->pcm_list, list)
2370 snd_pcm_suspend_all(p->pcm);
2371 if (chip->initialized)
2372 snd_hda_suspend(chip->bus);
2373 azx_stop_chip(chip);
2374 if (chip->irq >= 0) {
2375 free_irq(chip->irq, chip);
2376 chip->irq = -1;
2377 }
2378 if (chip->msi)
2379 pci_disable_msi(chip->pci);
2380 pci_disable_device(pci);
2381 pci_save_state(pci);
2382 pci_set_power_state(pci, pci_choose_state(pci, state));
2383 return 0;
2384 }
2385
azx_resume(struct pci_dev * pci)2386 static int azx_resume(struct pci_dev *pci)
2387 {
2388 struct snd_card *card = pci_get_drvdata(pci);
2389 struct azx *chip = card->private_data;
2390
2391 pci_set_power_state(pci, PCI_D0);
2392 pci_restore_state(pci);
2393 if (pci_enable_device(pci) < 0) {
2394 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2395 "disabling device\n");
2396 snd_card_disconnect(card);
2397 return -EIO;
2398 }
2399 pci_set_master(pci);
2400 if (chip->msi)
2401 if (pci_enable_msi(pci) < 0)
2402 chip->msi = 0;
2403 if (azx_acquire_irq(chip, 1) < 0)
2404 return -EIO;
2405 azx_init_pci(chip);
2406
2407 if (snd_hda_codecs_inuse(chip->bus))
2408 azx_init_chip(chip, 1);
2409
2410 snd_hda_resume(chip->bus);
2411 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2412 return 0;
2413 }
2414 #endif /* CONFIG_PM */
2415
2416
2417 /*
2418 * reboot notifier for hang-up problem at power-down
2419 */
azx_halt(struct notifier_block * nb,unsigned long event,void * buf)2420 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2421 {
2422 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2423 snd_hda_bus_reboot_notify(chip->bus);
2424 azx_stop_chip(chip);
2425 return NOTIFY_OK;
2426 }
2427
azx_notifier_register(struct azx * chip)2428 static void azx_notifier_register(struct azx *chip)
2429 {
2430 chip->reboot_notifier.notifier_call = azx_halt;
2431 register_reboot_notifier(&chip->reboot_notifier);
2432 }
2433
azx_notifier_unregister(struct azx * chip)2434 static void azx_notifier_unregister(struct azx *chip)
2435 {
2436 if (chip->reboot_notifier.notifier_call)
2437 unregister_reboot_notifier(&chip->reboot_notifier);
2438 }
2439
2440 /*
2441 * destructor
2442 */
azx_free(struct azx * chip)2443 static int azx_free(struct azx *chip)
2444 {
2445 int i;
2446
2447 azx_notifier_unregister(chip);
2448
2449 if (chip->initialized) {
2450 azx_clear_irq_pending(chip);
2451 for (i = 0; i < chip->num_streams; i++)
2452 azx_stream_stop(chip, &chip->azx_dev[i]);
2453 azx_stop_chip(chip);
2454 }
2455
2456 if (chip->irq >= 0)
2457 free_irq(chip->irq, (void*)chip);
2458 if (chip->msi)
2459 pci_disable_msi(chip->pci);
2460 if (chip->remap_addr)
2461 iounmap(chip->remap_addr);
2462
2463 if (chip->azx_dev) {
2464 for (i = 0; i < chip->num_streams; i++)
2465 if (chip->azx_dev[i].bdl.area) {
2466 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2467 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2468 }
2469 }
2470 if (chip->rb.area) {
2471 mark_pages_wc(chip, &chip->rb, false);
2472 snd_dma_free_pages(&chip->rb);
2473 }
2474 if (chip->posbuf.area) {
2475 mark_pages_wc(chip, &chip->posbuf, false);
2476 snd_dma_free_pages(&chip->posbuf);
2477 }
2478 pci_release_regions(chip->pci);
2479 pci_disable_device(chip->pci);
2480 kfree(chip->azx_dev);
2481 kfree(chip);
2482
2483 return 0;
2484 }
2485
azx_dev_free(struct snd_device * device)2486 static int azx_dev_free(struct snd_device *device)
2487 {
2488 return azx_free(device->device_data);
2489 }
2490
2491 /*
2492 * white/black-listing for position_fix
2493 */
2494 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2495 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2496 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2497 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2498 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2499 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2500 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2501 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2502 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2503 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2504 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2505 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2506 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2507 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2508 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2509 {}
2510 };
2511
check_position_fix(struct azx * chip,int fix)2512 static int __devinit check_position_fix(struct azx *chip, int fix)
2513 {
2514 const struct snd_pci_quirk *q;
2515
2516 switch (fix) {
2517 case POS_FIX_LPIB:
2518 case POS_FIX_POSBUF:
2519 case POS_FIX_VIACOMBO:
2520 return fix;
2521 }
2522
2523 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2524 if (q) {
2525 printk(KERN_INFO
2526 "hda_intel: position_fix set to %d "
2527 "for device %04x:%04x\n",
2528 q->value, q->subvendor, q->subdevice);
2529 return q->value;
2530 }
2531
2532 /* Check VIA/ATI HD Audio Controller exist */
2533 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2534 snd_printd(SFX "Using VIACOMBO position fix\n");
2535 return POS_FIX_VIACOMBO;
2536 }
2537 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2538 snd_printd(SFX "Using LPIB position fix\n");
2539 return POS_FIX_LPIB;
2540 }
2541 return POS_FIX_AUTO;
2542 }
2543
2544 /*
2545 * black-lists for probe_mask
2546 */
2547 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2548 /* Thinkpad often breaks the controller communication when accessing
2549 * to the non-working (or non-existing) modem codec slot.
2550 */
2551 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2552 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2553 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2554 /* broken BIOS */
2555 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2556 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2557 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2558 /* forced codec slots */
2559 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2560 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2561 {}
2562 };
2563
2564 #define AZX_FORCE_CODEC_MASK 0x100
2565
check_probe_mask(struct azx * chip,int dev)2566 static void __devinit check_probe_mask(struct azx *chip, int dev)
2567 {
2568 const struct snd_pci_quirk *q;
2569
2570 chip->codec_probe_mask = probe_mask[dev];
2571 if (chip->codec_probe_mask == -1) {
2572 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2573 if (q) {
2574 printk(KERN_INFO
2575 "hda_intel: probe_mask set to 0x%x "
2576 "for device %04x:%04x\n",
2577 q->value, q->subvendor, q->subdevice);
2578 chip->codec_probe_mask = q->value;
2579 }
2580 }
2581
2582 /* check forced option */
2583 if (chip->codec_probe_mask != -1 &&
2584 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2585 chip->codec_mask = chip->codec_probe_mask & 0xff;
2586 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2587 chip->codec_mask);
2588 }
2589 }
2590
2591 /*
2592 * white/black-list for enable_msi
2593 */
2594 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2595 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2596 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2597 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2598 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2599 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2600 {}
2601 };
2602
check_msi(struct azx * chip)2603 static void __devinit check_msi(struct azx *chip)
2604 {
2605 const struct snd_pci_quirk *q;
2606
2607 if (enable_msi >= 0) {
2608 chip->msi = !!enable_msi;
2609 return;
2610 }
2611 chip->msi = 1; /* enable MSI as default */
2612 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2613 if (q) {
2614 printk(KERN_INFO
2615 "hda_intel: msi for device %04x:%04x set to %d\n",
2616 q->subvendor, q->subdevice, q->value);
2617 chip->msi = q->value;
2618 return;
2619 }
2620
2621 /* NVidia chipsets seem to cause troubles with MSI */
2622 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2623 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2624 chip->msi = 0;
2625 }
2626 }
2627
2628 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)2629 static void __devinit azx_check_snoop_available(struct azx *chip)
2630 {
2631 bool snoop = chip->snoop;
2632
2633 switch (chip->driver_type) {
2634 case AZX_DRIVER_VIA:
2635 /* force to non-snoop mode for a new VIA controller
2636 * when BIOS is set
2637 */
2638 if (snoop) {
2639 u8 val;
2640 pci_read_config_byte(chip->pci, 0x42, &val);
2641 if (!(val & 0x80) && chip->pci->revision == 0x30)
2642 snoop = false;
2643 }
2644 break;
2645 case AZX_DRIVER_ATIHDMI_NS:
2646 /* new ATI HDMI requires non-snoop */
2647 snoop = false;
2648 break;
2649 }
2650
2651 if (snoop != chip->snoop) {
2652 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2653 snoop ? "snoop" : "non-snoop");
2654 chip->snoop = snoop;
2655 }
2656 }
2657
2658 /*
2659 * constructor
2660 */
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)2661 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2662 int dev, unsigned int driver_caps,
2663 struct azx **rchip)
2664 {
2665 struct azx *chip;
2666 int i, err;
2667 unsigned short gcap;
2668 static struct snd_device_ops ops = {
2669 .dev_free = azx_dev_free,
2670 };
2671
2672 *rchip = NULL;
2673
2674 err = pci_enable_device(pci);
2675 if (err < 0)
2676 return err;
2677
2678 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2679 if (!chip) {
2680 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2681 pci_disable_device(pci);
2682 return -ENOMEM;
2683 }
2684
2685 spin_lock_init(&chip->reg_lock);
2686 mutex_init(&chip->open_mutex);
2687 chip->card = card;
2688 chip->pci = pci;
2689 chip->irq = -1;
2690 chip->driver_caps = driver_caps;
2691 chip->driver_type = driver_caps & 0xff;
2692 check_msi(chip);
2693 chip->dev_index = dev;
2694 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2695 INIT_LIST_HEAD(&chip->pcm_list);
2696
2697 chip->position_fix[0] = chip->position_fix[1] =
2698 check_position_fix(chip, position_fix[dev]);
2699 check_probe_mask(chip, dev);
2700
2701 chip->single_cmd = single_cmd;
2702 chip->snoop = hda_snoop;
2703 azx_check_snoop_available(chip);
2704
2705 if (bdl_pos_adj[dev] < 0) {
2706 switch (chip->driver_type) {
2707 case AZX_DRIVER_ICH:
2708 case AZX_DRIVER_PCH:
2709 bdl_pos_adj[dev] = 1;
2710 break;
2711 default:
2712 bdl_pos_adj[dev] = 32;
2713 break;
2714 }
2715 }
2716
2717 #if BITS_PER_LONG != 64
2718 /* Fix up base address on ULI M5461 */
2719 if (chip->driver_type == AZX_DRIVER_ULI) {
2720 u16 tmp3;
2721 pci_read_config_word(pci, 0x40, &tmp3);
2722 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2723 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2724 }
2725 #endif
2726
2727 err = pci_request_regions(pci, "ICH HD audio");
2728 if (err < 0) {
2729 kfree(chip);
2730 pci_disable_device(pci);
2731 return err;
2732 }
2733
2734 chip->addr = pci_resource_start(pci, 0);
2735 chip->remap_addr = pci_ioremap_bar(pci, 0);
2736 if (chip->remap_addr == NULL) {
2737 snd_printk(KERN_ERR SFX "ioremap error\n");
2738 err = -ENXIO;
2739 goto errout;
2740 }
2741
2742 if (chip->msi)
2743 if (pci_enable_msi(pci) < 0)
2744 chip->msi = 0;
2745
2746 if (azx_acquire_irq(chip, 0) < 0) {
2747 err = -EBUSY;
2748 goto errout;
2749 }
2750
2751 pci_set_master(pci);
2752 synchronize_irq(chip->irq);
2753
2754 gcap = azx_readw(chip, GCAP);
2755 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2756
2757 /* disable SB600 64bit support for safety */
2758 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2759 struct pci_dev *p_smbus;
2760 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2761 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2762 NULL);
2763 if (p_smbus) {
2764 if (p_smbus->revision < 0x30)
2765 gcap &= ~ICH6_GCAP_64OK;
2766 pci_dev_put(p_smbus);
2767 }
2768 }
2769
2770 /* disable 64bit DMA address on some devices */
2771 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2772 snd_printd(SFX "Disabling 64bit DMA\n");
2773 gcap &= ~ICH6_GCAP_64OK;
2774 }
2775
2776 /* disable buffer size rounding to 128-byte multiples if supported */
2777 chip->align_buffer_size = align_buffer_size;
2778 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2779 chip->align_buffer_size = 0;
2780
2781 /* allow 64bit DMA address if supported by H/W */
2782 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2783 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2784 else {
2785 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2786 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2787 }
2788
2789 /* read number of streams from GCAP register instead of using
2790 * hardcoded value
2791 */
2792 chip->capture_streams = (gcap >> 8) & 0x0f;
2793 chip->playback_streams = (gcap >> 12) & 0x0f;
2794 if (!chip->playback_streams && !chip->capture_streams) {
2795 /* gcap didn't give any info, switching to old method */
2796
2797 switch (chip->driver_type) {
2798 case AZX_DRIVER_ULI:
2799 chip->playback_streams = ULI_NUM_PLAYBACK;
2800 chip->capture_streams = ULI_NUM_CAPTURE;
2801 break;
2802 case AZX_DRIVER_ATIHDMI:
2803 case AZX_DRIVER_ATIHDMI_NS:
2804 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2805 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2806 break;
2807 case AZX_DRIVER_GENERIC:
2808 default:
2809 chip->playback_streams = ICH6_NUM_PLAYBACK;
2810 chip->capture_streams = ICH6_NUM_CAPTURE;
2811 break;
2812 }
2813 }
2814 chip->capture_index_offset = 0;
2815 chip->playback_index_offset = chip->capture_streams;
2816 chip->num_streams = chip->playback_streams + chip->capture_streams;
2817 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2818 GFP_KERNEL);
2819 if (!chip->azx_dev) {
2820 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2821 goto errout;
2822 }
2823
2824 for (i = 0; i < chip->num_streams; i++) {
2825 /* allocate memory for the BDL for each stream */
2826 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2827 snd_dma_pci_data(chip->pci),
2828 BDL_SIZE, &chip->azx_dev[i].bdl);
2829 if (err < 0) {
2830 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2831 goto errout;
2832 }
2833 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2834 }
2835 /* allocate memory for the position buffer */
2836 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2837 snd_dma_pci_data(chip->pci),
2838 chip->num_streams * 8, &chip->posbuf);
2839 if (err < 0) {
2840 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2841 goto errout;
2842 }
2843 mark_pages_wc(chip, &chip->posbuf, true);
2844 /* allocate CORB/RIRB */
2845 err = azx_alloc_cmd_io(chip);
2846 if (err < 0)
2847 goto errout;
2848
2849 /* initialize streams */
2850 azx_init_stream(chip);
2851
2852 /* initialize chip */
2853 azx_init_pci(chip);
2854 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2855
2856 /* codec detection */
2857 if (!chip->codec_mask) {
2858 snd_printk(KERN_ERR SFX "no codecs found!\n");
2859 err = -ENODEV;
2860 goto errout;
2861 }
2862
2863 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2864 if (err <0) {
2865 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2866 goto errout;
2867 }
2868
2869 strcpy(card->driver, "HDA-Intel");
2870 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2871 sizeof(card->shortname));
2872 snprintf(card->longname, sizeof(card->longname),
2873 "%s at 0x%lx irq %i",
2874 card->shortname, chip->addr, chip->irq);
2875
2876 *rchip = chip;
2877 return 0;
2878
2879 errout:
2880 azx_free(chip);
2881 return err;
2882 }
2883
power_down_all_codecs(struct azx * chip)2884 static void power_down_all_codecs(struct azx *chip)
2885 {
2886 #ifdef CONFIG_SND_HDA_POWER_SAVE
2887 /* The codecs were powered up in snd_hda_codec_new().
2888 * Now all initialization done, so turn them down if possible
2889 */
2890 struct hda_codec *codec;
2891 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2892 snd_hda_power_down(codec);
2893 }
2894 #endif
2895 }
2896
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2897 static int __devinit azx_probe(struct pci_dev *pci,
2898 const struct pci_device_id *pci_id)
2899 {
2900 static int dev;
2901 struct snd_card *card;
2902 struct azx *chip;
2903 int err;
2904
2905 if (dev >= SNDRV_CARDS)
2906 return -ENODEV;
2907 if (!enable[dev]) {
2908 dev++;
2909 return -ENOENT;
2910 }
2911
2912 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2913 if (err < 0) {
2914 snd_printk(KERN_ERR SFX "Error creating card!\n");
2915 return err;
2916 }
2917
2918 /* set this here since it's referred in snd_hda_load_patch() */
2919 snd_card_set_dev(card, &pci->dev);
2920
2921 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2922 if (err < 0)
2923 goto out_free;
2924 card->private_data = chip;
2925
2926 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2927 chip->beep_mode = beep_mode[dev];
2928 #endif
2929
2930 /* create codec instances */
2931 err = azx_codec_create(chip, model[dev]);
2932 if (err < 0)
2933 goto out_free;
2934 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2935 if (patch[dev] && *patch[dev]) {
2936 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2937 patch[dev]);
2938 err = snd_hda_load_patch(chip->bus, patch[dev]);
2939 if (err < 0)
2940 goto out_free;
2941 }
2942 #endif
2943 if ((probe_only[dev] & 1) == 0) {
2944 err = azx_codec_configure(chip);
2945 if (err < 0)
2946 goto out_free;
2947 }
2948
2949 /* create PCM streams */
2950 err = snd_hda_build_pcms(chip->bus);
2951 if (err < 0)
2952 goto out_free;
2953
2954 /* create mixer controls */
2955 err = azx_mixer_create(chip);
2956 if (err < 0)
2957 goto out_free;
2958
2959 err = snd_card_register(card);
2960 if (err < 0)
2961 goto out_free;
2962
2963 pci_set_drvdata(pci, card);
2964 chip->running = 1;
2965 power_down_all_codecs(chip);
2966 azx_notifier_register(chip);
2967
2968 dev++;
2969 return err;
2970 out_free:
2971 snd_card_free(card);
2972 return err;
2973 }
2974
azx_remove(struct pci_dev * pci)2975 static void __devexit azx_remove(struct pci_dev *pci)
2976 {
2977 snd_card_free(pci_get_drvdata(pci));
2978 pci_set_drvdata(pci, NULL);
2979 }
2980
2981 /* PCI IDs */
2982 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2983 /* CPT */
2984 { PCI_DEVICE(0x8086, 0x1c20),
2985 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2986 AZX_DCAPS_BUFSIZE },
2987 /* PBG */
2988 { PCI_DEVICE(0x8086, 0x1d20),
2989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2990 AZX_DCAPS_BUFSIZE},
2991 /* Panther Point */
2992 { PCI_DEVICE(0x8086, 0x1e20),
2993 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2994 AZX_DCAPS_BUFSIZE},
2995 /* SCH */
2996 { PCI_DEVICE(0x8086, 0x811b),
2997 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2998 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
2999 { PCI_DEVICE(0x8086, 0x080a),
3000 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3001 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3002 /* ICH */
3003 { PCI_DEVICE(0x8086, 0x2668),
3004 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3005 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3006 { PCI_DEVICE(0x8086, 0x27d8),
3007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3008 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3009 { PCI_DEVICE(0x8086, 0x269a),
3010 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3011 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3012 { PCI_DEVICE(0x8086, 0x284b),
3013 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3014 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3015 { PCI_DEVICE(0x8086, 0x293e),
3016 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3017 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3018 { PCI_DEVICE(0x8086, 0x293f),
3019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3020 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3021 { PCI_DEVICE(0x8086, 0x3a3e),
3022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3023 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3024 { PCI_DEVICE(0x8086, 0x3a6e),
3025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3026 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3027 /* Generic Intel */
3028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3029 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3030 .class_mask = 0xffffff,
3031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3032 /* ATI SB 450/600/700/800/900 */
3033 { PCI_DEVICE(0x1002, 0x437b),
3034 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3035 { PCI_DEVICE(0x1002, 0x4383),
3036 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3037 /* AMD Hudson */
3038 { PCI_DEVICE(0x1022, 0x780d),
3039 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3040 /* ATI HDMI */
3041 { PCI_DEVICE(0x1002, 0x793b),
3042 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3043 { PCI_DEVICE(0x1002, 0x7919),
3044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3045 { PCI_DEVICE(0x1002, 0x960f),
3046 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3047 { PCI_DEVICE(0x1002, 0x970f),
3048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3049 { PCI_DEVICE(0x1002, 0xaa00),
3050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3051 { PCI_DEVICE(0x1002, 0xaa08),
3052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3053 { PCI_DEVICE(0x1002, 0xaa10),
3054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3055 { PCI_DEVICE(0x1002, 0xaa18),
3056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3057 { PCI_DEVICE(0x1002, 0xaa20),
3058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3059 { PCI_DEVICE(0x1002, 0xaa28),
3060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3061 { PCI_DEVICE(0x1002, 0xaa30),
3062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3063 { PCI_DEVICE(0x1002, 0xaa38),
3064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3065 { PCI_DEVICE(0x1002, 0xaa40),
3066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3067 { PCI_DEVICE(0x1002, 0xaa48),
3068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3069 { PCI_DEVICE(0x1002, 0x9902),
3070 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3071 { PCI_DEVICE(0x1002, 0xaaa0),
3072 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3073 { PCI_DEVICE(0x1002, 0xaaa8),
3074 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3075 { PCI_DEVICE(0x1002, 0xaab0),
3076 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3077 /* VIA VT8251/VT8237A */
3078 { PCI_DEVICE(0x1106, 0x3288),
3079 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3080 /* SIS966 */
3081 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3082 /* ULI M5461 */
3083 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3084 /* NVIDIA MCP */
3085 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3086 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3087 .class_mask = 0xffffff,
3088 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3089 /* Teradici */
3090 { PCI_DEVICE(0x6549, 0x1200),
3091 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3092 /* Creative X-Fi (CA0110-IBG) */
3093 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3094 /* the following entry conflicts with snd-ctxfi driver,
3095 * as ctxfi driver mutates from HD-audio to native mode with
3096 * a special command sequence.
3097 */
3098 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3099 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3100 .class_mask = 0xffffff,
3101 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3102 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3103 #else
3104 /* this entry seems still valid -- i.e. without emu20kx chip */
3105 { PCI_DEVICE(0x1102, 0x0009),
3106 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3107 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3108 #endif
3109 /* Vortex86MX */
3110 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3111 /* VMware HDAudio */
3112 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3113 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3114 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3115 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3116 .class_mask = 0xffffff,
3117 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3118 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3119 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3120 .class_mask = 0xffffff,
3121 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3122 { 0, }
3123 };
3124 MODULE_DEVICE_TABLE(pci, azx_ids);
3125
3126 /* pci_driver definition */
3127 static struct pci_driver driver = {
3128 .name = KBUILD_MODNAME,
3129 .id_table = azx_ids,
3130 .probe = azx_probe,
3131 .remove = __devexit_p(azx_remove),
3132 #ifdef CONFIG_PM
3133 .suspend = azx_suspend,
3134 .resume = azx_resume,
3135 #endif
3136 };
3137
alsa_card_azx_init(void)3138 static int __init alsa_card_azx_init(void)
3139 {
3140 return pci_register_driver(&driver);
3141 }
3142
alsa_card_azx_exit(void)3143 static void __exit alsa_card_azx_exit(void)
3144 {
3145 pci_unregister_driver(&driver);
3146 }
3147
3148 module_init(alsa_card_azx_init)
3149 module_exit(alsa_card_azx_exit)
3150