1 /*
2 * include/linux/mmc/sh_mmcif.h
3 *
4 * platform data for eMMC driver
5 *
6 * Copyright (C) 2010 Renesas Solutions Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 */
13
14 #ifndef LINUX_MMC_SH_MMCIF_H
15 #define LINUX_MMC_SH_MMCIF_H
16
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/sh_dma.h>
20
21 /*
22 * MMCIF : CE_CLK_CTRL [19:16]
23 * 1000 : Peripheral clock / 512
24 * 0111 : Peripheral clock / 256
25 * 0110 : Peripheral clock / 128
26 * 0101 : Peripheral clock / 64
27 * 0100 : Peripheral clock / 32
28 * 0011 : Peripheral clock / 16
29 * 0010 : Peripheral clock / 8
30 * 0001 : Peripheral clock / 4
31 * 0000 : Peripheral clock / 2
32 * 1111 : Peripheral clock (sup_pclk set '1')
33 */
34
35 struct sh_mmcif_dma {
36 struct sh_dmae_slave chan_priv_tx;
37 struct sh_dmae_slave chan_priv_rx;
38 };
39
40 struct sh_mmcif_plat_data {
41 void (*set_pwr)(struct platform_device *pdev, int state);
42 void (*down_pwr)(struct platform_device *pdev);
43 int (*get_cd)(struct platform_device *pdef);
44 struct sh_mmcif_dma *dma; /* Deprecated. Instead */
45 unsigned int slave_id_tx; /* use embedded slave_id_[tr]x */
46 unsigned int slave_id_rx;
47 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
48 unsigned long caps;
49 u32 ocr;
50 };
51
52 #define MMCIF_CE_CMD_SET 0x00000000
53 #define MMCIF_CE_ARG 0x00000008
54 #define MMCIF_CE_ARG_CMD12 0x0000000C
55 #define MMCIF_CE_CMD_CTRL 0x00000010
56 #define MMCIF_CE_BLOCK_SET 0x00000014
57 #define MMCIF_CE_CLK_CTRL 0x00000018
58 #define MMCIF_CE_BUF_ACC 0x0000001C
59 #define MMCIF_CE_RESP3 0x00000020
60 #define MMCIF_CE_RESP2 0x00000024
61 #define MMCIF_CE_RESP1 0x00000028
62 #define MMCIF_CE_RESP0 0x0000002C
63 #define MMCIF_CE_RESP_CMD12 0x00000030
64 #define MMCIF_CE_DATA 0x00000034
65 #define MMCIF_CE_INT 0x00000040
66 #define MMCIF_CE_INT_MASK 0x00000044
67 #define MMCIF_CE_HOST_STS1 0x00000048
68 #define MMCIF_CE_HOST_STS2 0x0000004C
69 #define MMCIF_CE_VERSION 0x0000007C
70
71 /* CE_BUF_ACC */
72 #define BUF_ACC_DMAWEN (1 << 25)
73 #define BUF_ACC_DMAREN (1 << 24)
74 #define BUF_ACC_BUSW_32 (0 << 17)
75 #define BUF_ACC_BUSW_16 (1 << 17)
76 #define BUF_ACC_ATYP (1 << 16)
77
78 /* CE_CLK_CTRL */
79 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
80 #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
81 #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
82 #define CLKDIV_4 (1<<16) /* mmc clock frequency.
83 * n: bus clock/(2^(n+1)) */
84 #define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
85 #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
86 #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
87 (1 << 9) | (1 << 8)) /* resp busy timeout */
88 #define SRWDTO_29 ((1 << 7) | (1 << 6) | \
89 (1 << 5) | (1 << 4)) /* read/write timeout */
90 #define SCCSTO_29 ((1 << 3) | (1 << 2) | \
91 (1 << 1) | (1 << 0)) /* ccs timeout */
92
93 /* CE_VERSION */
94 #define SOFT_RST_ON (1 << 31)
95 #define SOFT_RST_OFF 0
96
sh_mmcif_readl(void __iomem * addr,int reg)97 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
98 {
99 return __raw_readl(addr + reg);
100 }
101
sh_mmcif_writel(void __iomem * addr,int reg,u32 val)102 static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
103 {
104 __raw_writel(val, addr + reg);
105 }
106
107 #define SH_MMCIF_BBS 512 /* boot block size */
108
sh_mmcif_boot_cmd_send(void __iomem * base,unsigned long cmd,unsigned long arg)109 static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
110 unsigned long cmd, unsigned long arg)
111 {
112 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
113 sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
114 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
115 }
116
sh_mmcif_boot_cmd_poll(void __iomem * base,unsigned long mask)117 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
118 {
119 unsigned long tmp;
120 int cnt;
121
122 for (cnt = 0; cnt < 1000000; cnt++) {
123 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
124 if (tmp & mask) {
125 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
126 return 0;
127 }
128 }
129
130 return -1;
131 }
132
sh_mmcif_boot_cmd(void __iomem * base,unsigned long cmd,unsigned long arg)133 static inline int sh_mmcif_boot_cmd(void __iomem *base,
134 unsigned long cmd, unsigned long arg)
135 {
136 sh_mmcif_boot_cmd_send(base, cmd, arg);
137 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
138 }
139
sh_mmcif_boot_do_read_single(void __iomem * base,unsigned int block_nr,unsigned long * buf)140 static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
141 unsigned int block_nr,
142 unsigned long *buf)
143 {
144 int k;
145
146 /* CMD13 - Status */
147 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
148
149 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
150 return -1;
151
152 /* CMD17 - Read */
153 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
154 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
155 return -1;
156
157 for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
158 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
159
160 return 0;
161 }
162
sh_mmcif_boot_do_read(void __iomem * base,unsigned long first_block,unsigned long nr_blocks,void * buf)163 static inline int sh_mmcif_boot_do_read(void __iomem *base,
164 unsigned long first_block,
165 unsigned long nr_blocks,
166 void *buf)
167 {
168 unsigned long k;
169 int ret = 0;
170
171 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
172 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
173 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
174 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
175
176 /* CMD9 - Get CSD */
177 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
178
179 /* CMD7 - Select the card */
180 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
181
182 /* CMD16 - Set the block size */
183 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
184
185 for (k = 0; !ret && k < nr_blocks; k++)
186 ret = sh_mmcif_boot_do_read_single(base, first_block + k,
187 buf + (k * SH_MMCIF_BBS));
188
189 return ret;
190 }
191
sh_mmcif_boot_init(void __iomem * base)192 static inline void sh_mmcif_boot_init(void __iomem *base)
193 {
194 /* reset */
195 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
196 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
197
198 /* byte swap */
199 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
200
201 /* Set block size in MMCIF hardware */
202 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
203
204 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
205 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
206 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
207 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
208
209 /* CMD0 */
210 sh_mmcif_boot_cmd(base, 0x00000040, 0);
211
212 /* CMD1 - Get OCR */
213 do {
214 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
215 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
216 != 0x80000000);
217
218 /* CMD2 - Get CID */
219 sh_mmcif_boot_cmd(base, 0x02806040, 0);
220
221 /* CMD3 - Set card relative address */
222 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
223 }
224
225 #endif /* LINUX_MMC_SH_MMCIF_H */
226