1 /*
2 * Copyright (C) ST Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * STE Ux500 PRCMU API
7 */
8 #ifndef __MACH_PRCMU_H
9 #define __MACH_PRCMU_H
10
11 #include <linux/interrupt.h>
12 #include <linux/notifier.h>
13 #include <asm/mach-types.h>
14
15 /* PRCMU Wakeup defines */
16 enum prcmu_wakeup_index {
17 PRCMU_WAKEUP_INDEX_RTC,
18 PRCMU_WAKEUP_INDEX_RTT0,
19 PRCMU_WAKEUP_INDEX_RTT1,
20 PRCMU_WAKEUP_INDEX_HSI0,
21 PRCMU_WAKEUP_INDEX_HSI1,
22 PRCMU_WAKEUP_INDEX_USB,
23 PRCMU_WAKEUP_INDEX_ABB,
24 PRCMU_WAKEUP_INDEX_ABB_FIFO,
25 PRCMU_WAKEUP_INDEX_ARM,
26 PRCMU_WAKEUP_INDEX_CD_IRQ,
27 NUM_PRCMU_WAKEUP_INDICES
28 };
29 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
30
31 /* EPOD (power domain) IDs */
32
33 /*
34 * DB8500 EPODs
35 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39 * - EPOD_ID_SGA: power domain for SGA
40 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43 * - NUM_EPOD_ID: number of power domains
44 *
45 * TODO: These should be prefixed.
46 */
47 #define EPOD_ID_SVAMMDSP 0
48 #define EPOD_ID_SVAPIPE 1
49 #define EPOD_ID_SIAMMDSP 2
50 #define EPOD_ID_SIAPIPE 3
51 #define EPOD_ID_SGA 4
52 #define EPOD_ID_B2R2_MCDE 5
53 #define EPOD_ID_ESRAM12 6
54 #define EPOD_ID_ESRAM34 7
55 #define NUM_EPOD_ID 8
56
57 /*
58 * DB5500 EPODs
59 */
60 #define DB5500_EPOD_ID_BASE 0x0100
61 #define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62 #define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63 #define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64 #define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65 #define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66 #define DB5500_NUM_EPOD_ID 7
67
68 /*
69 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off
72 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
73 * retention
74 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
75 * - EPOD_STATE_ON: Same as above, but with clock enabled
76 */
77 #define EPOD_STATE_NO_CHANGE 0x00
78 #define EPOD_STATE_OFF 0x01
79 #define EPOD_STATE_RAMRET 0x02
80 #define EPOD_STATE_ON_CLK_OFF 0x03
81 #define EPOD_STATE_ON 0x04
82
83 /*
84 * CLKOUT sources
85 */
86 #define PRCMU_CLKSRC_CLK38M 0x00
87 #define PRCMU_CLKSRC_ACLK 0x01
88 #define PRCMU_CLKSRC_SYSCLK 0x02
89 #define PRCMU_CLKSRC_LCDCLK 0x03
90 #define PRCMU_CLKSRC_SDMMCCLK 0x04
91 #define PRCMU_CLKSRC_TVCLK 0x05
92 #define PRCMU_CLKSRC_TIMCLK 0x06
93 #define PRCMU_CLKSRC_CLK009 0x07
94 /* These are only valid for CLKOUT1: */
95 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
96 #define PRCMU_CLKSRC_I2CCLK 0x41
97 #define PRCMU_CLKSRC_MSP02CLK 0x42
98 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
99 #define PRCMU_CLKSRC_HSIRXCLK 0x44
100 #define PRCMU_CLKSRC_HSITXCLK 0x45
101 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
102 #define PRCMU_CLKSRC_HDMICLK 0x47
103
104 /*
105 * Clock identifiers.
106 */
107 enum prcmu_clock {
108 PRCMU_SGACLK,
109 PRCMU_UARTCLK,
110 PRCMU_MSP02CLK,
111 PRCMU_MSP1CLK,
112 PRCMU_I2CCLK,
113 PRCMU_SDMMCCLK,
114 PRCMU_SLIMCLK,
115 PRCMU_PER1CLK,
116 PRCMU_PER2CLK,
117 PRCMU_PER3CLK,
118 PRCMU_PER5CLK,
119 PRCMU_PER6CLK,
120 PRCMU_PER7CLK,
121 PRCMU_LCDCLK,
122 PRCMU_BMLCLK,
123 PRCMU_HSITXCLK,
124 PRCMU_HSIRXCLK,
125 PRCMU_HDMICLK,
126 PRCMU_APEATCLK,
127 PRCMU_APETRACECLK,
128 PRCMU_MCDECLK,
129 PRCMU_IPI2CCLK,
130 PRCMU_DSIALTCLK,
131 PRCMU_DMACLK,
132 PRCMU_B2R2CLK,
133 PRCMU_TVCLK,
134 PRCMU_SSPCLK,
135 PRCMU_RNGCLK,
136 PRCMU_UICCCLK,
137 PRCMU_PWMCLK,
138 PRCMU_IRDACLK,
139 PRCMU_IRRCCLK,
140 PRCMU_SIACLK,
141 PRCMU_SVACLK,
142 PRCMU_NUM_REG_CLOCKS,
143 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
144 PRCMU_TIMCLK,
145 PRCMU_PLLSOC0,
146 PRCMU_PLLSOC1,
147 PRCMU_PLLDDR,
148 };
149
150 /**
151 * enum ape_opp - APE OPP states definition
152 * @APE_OPP_INIT:
153 * @APE_NO_CHANGE: The APE operating point is unchanged
154 * @APE_100_OPP: The new APE operating point is ape100opp
155 * @APE_50_OPP: 50%
156 */
157 enum ape_opp {
158 APE_OPP_INIT = 0x00,
159 APE_NO_CHANGE = 0x01,
160 APE_100_OPP = 0x02,
161 APE_50_OPP = 0x03
162 };
163
164 /**
165 * enum arm_opp - ARM OPP states definition
166 * @ARM_OPP_INIT:
167 * @ARM_NO_CHANGE: The ARM operating point is unchanged
168 * @ARM_100_OPP: The new ARM operating point is arm100opp
169 * @ARM_50_OPP: The new ARM operating point is arm50opp
170 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
171 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
172 * @ARM_EXTCLK: The new ARM operating point is armExtClk
173 */
174 enum arm_opp {
175 ARM_OPP_INIT = 0x00,
176 ARM_NO_CHANGE = 0x01,
177 ARM_100_OPP = 0x02,
178 ARM_50_OPP = 0x03,
179 ARM_MAX_OPP = 0x04,
180 ARM_MAX_FREQ100OPP = 0x05,
181 ARM_EXTCLK = 0x07
182 };
183
184 /**
185 * enum ddr_opp - DDR OPP states definition
186 * @DDR_100_OPP: The new DDR operating point is ddr100opp
187 * @DDR_50_OPP: The new DDR operating point is ddr50opp
188 * @DDR_25_OPP: The new DDR operating point is ddr25opp
189 */
190 enum ddr_opp {
191 DDR_100_OPP = 0x00,
192 DDR_50_OPP = 0x01,
193 DDR_25_OPP = 0x02,
194 };
195
196 /*
197 * Definitions for controlling ESRAM0 in deep sleep.
198 */
199 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
200 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
201
202 /**
203 * enum ddr_pwrst - DDR power states definition
204 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
205 * @DDR_PWR_STATE_ON:
206 * @DDR_PWR_STATE_OFFLOWLAT:
207 * @DDR_PWR_STATE_OFFHIGHLAT:
208 */
209 enum ddr_pwrst {
210 DDR_PWR_STATE_UNCHANGED = 0x00,
211 DDR_PWR_STATE_ON = 0x01,
212 DDR_PWR_STATE_OFFLOWLAT = 0x02,
213 DDR_PWR_STATE_OFFHIGHLAT = 0x03
214 };
215
216 #include <linux/mfd/db8500-prcmu.h>
217 #include <linux/mfd/db5500-prcmu.h>
218
219 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
220
prcmu_early_init(void)221 static inline void __init prcmu_early_init(void)
222 {
223 if (machine_is_u5500())
224 return db5500_prcmu_early_init();
225 else
226 return db8500_prcmu_early_init();
227 }
228
prcmu_set_power_state(u8 state,bool keep_ulp_clk,bool keep_ap_pll)229 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
230 bool keep_ap_pll)
231 {
232 if (machine_is_u5500())
233 return db5500_prcmu_set_power_state(state, keep_ulp_clk,
234 keep_ap_pll);
235 else
236 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
237 keep_ap_pll);
238 }
239
prcmu_set_epod(u16 epod_id,u8 epod_state)240 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
241 {
242 if (machine_is_u5500())
243 return -EINVAL;
244 else
245 return db8500_prcmu_set_epod(epod_id, epod_state);
246 }
247
prcmu_enable_wakeups(u32 wakeups)248 static inline void prcmu_enable_wakeups(u32 wakeups)
249 {
250 if (machine_is_u5500())
251 db5500_prcmu_enable_wakeups(wakeups);
252 else
253 db8500_prcmu_enable_wakeups(wakeups);
254 }
255
prcmu_disable_wakeups(void)256 static inline void prcmu_disable_wakeups(void)
257 {
258 prcmu_enable_wakeups(0);
259 }
260
prcmu_config_abb_event_readout(u32 abb_events)261 static inline void prcmu_config_abb_event_readout(u32 abb_events)
262 {
263 if (machine_is_u5500())
264 db5500_prcmu_config_abb_event_readout(abb_events);
265 else
266 db8500_prcmu_config_abb_event_readout(abb_events);
267 }
268
prcmu_get_abb_event_buffer(void __iomem ** buf)269 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
270 {
271 if (machine_is_u5500())
272 db5500_prcmu_get_abb_event_buffer(buf);
273 else
274 db8500_prcmu_get_abb_event_buffer(buf);
275 }
276
277 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
278 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
279
280 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
281
prcmu_request_clock(u8 clock,bool enable)282 static inline int prcmu_request_clock(u8 clock, bool enable)
283 {
284 if (machine_is_u5500())
285 return db5500_prcmu_request_clock(clock, enable);
286 else
287 return db8500_prcmu_request_clock(clock, enable);
288 }
289
290 int prcmu_set_ape_opp(u8 opp);
291 int prcmu_get_ape_opp(void);
292 int prcmu_set_ddr_opp(u8 opp);
293 int prcmu_get_ddr_opp(void);
294
prcmu_set_arm_opp(u8 opp)295 static inline int prcmu_set_arm_opp(u8 opp)
296 {
297 if (machine_is_u5500())
298 return -EINVAL;
299 else
300 return db8500_prcmu_set_arm_opp(opp);
301 }
302
prcmu_get_arm_opp(void)303 static inline int prcmu_get_arm_opp(void)
304 {
305 if (machine_is_u5500())
306 return -EINVAL;
307 else
308 return db8500_prcmu_get_arm_opp();
309 }
310
prcmu_system_reset(u16 reset_code)311 static inline void prcmu_system_reset(u16 reset_code)
312 {
313 if (machine_is_u5500())
314 return db5500_prcmu_system_reset(reset_code);
315 else
316 return db8500_prcmu_system_reset(reset_code);
317 }
318
prcmu_get_reset_code(void)319 static inline u16 prcmu_get_reset_code(void)
320 {
321 if (machine_is_u5500())
322 return db5500_prcmu_get_reset_code();
323 else
324 return db8500_prcmu_get_reset_code();
325 }
326
327 void prcmu_ac_wake_req(void);
328 void prcmu_ac_sleep_req(void);
329 void prcmu_modem_reset(void);
prcmu_is_ac_wake_requested(void)330 static inline bool prcmu_is_ac_wake_requested(void)
331 {
332 if (machine_is_u5500())
333 return db5500_prcmu_is_ac_wake_requested();
334 else
335 return db8500_prcmu_is_ac_wake_requested();
336 }
337
prcmu_set_display_clocks(void)338 static inline int prcmu_set_display_clocks(void)
339 {
340 if (machine_is_u5500())
341 return db5500_prcmu_set_display_clocks();
342 else
343 return db8500_prcmu_set_display_clocks();
344 }
345
prcmu_disable_dsipll(void)346 static inline int prcmu_disable_dsipll(void)
347 {
348 if (machine_is_u5500())
349 return db5500_prcmu_disable_dsipll();
350 else
351 return db8500_prcmu_disable_dsipll();
352 }
353
prcmu_enable_dsipll(void)354 static inline int prcmu_enable_dsipll(void)
355 {
356 if (machine_is_u5500())
357 return db5500_prcmu_enable_dsipll();
358 else
359 return db8500_prcmu_enable_dsipll();
360 }
361
prcmu_config_esram0_deep_sleep(u8 state)362 static inline int prcmu_config_esram0_deep_sleep(u8 state)
363 {
364 if (machine_is_u5500())
365 return -EINVAL;
366 else
367 return db8500_prcmu_config_esram0_deep_sleep(state);
368 }
369 #else
370
prcmu_early_init(void)371 static inline void __init prcmu_early_init(void) {}
372
prcmu_set_power_state(u8 state,bool keep_ulp_clk,bool keep_ap_pll)373 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
374 bool keep_ap_pll)
375 {
376 return 0;
377 }
378
prcmu_set_epod(u16 epod_id,u8 epod_state)379 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
380 {
381 return 0;
382 }
383
prcmu_enable_wakeups(u32 wakeups)384 static inline void prcmu_enable_wakeups(u32 wakeups) {}
385
prcmu_disable_wakeups(void)386 static inline void prcmu_disable_wakeups(void) {}
387
prcmu_abb_read(u8 slave,u8 reg,u8 * value,u8 size)388 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
389 {
390 return -ENOSYS;
391 }
392
prcmu_abb_write(u8 slave,u8 reg,u8 * value,u8 size)393 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
394 {
395 return -ENOSYS;
396 }
397
prcmu_config_clkout(u8 clkout,u8 source,u8 div)398 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
399 {
400 return 0;
401 }
402
prcmu_request_clock(u8 clock,bool enable)403 static inline int prcmu_request_clock(u8 clock, bool enable)
404 {
405 return 0;
406 }
407
prcmu_set_ape_opp(u8 opp)408 static inline int prcmu_set_ape_opp(u8 opp)
409 {
410 return 0;
411 }
412
prcmu_get_ape_opp(void)413 static inline int prcmu_get_ape_opp(void)
414 {
415 return APE_100_OPP;
416 }
417
prcmu_set_arm_opp(u8 opp)418 static inline int prcmu_set_arm_opp(u8 opp)
419 {
420 return 0;
421 }
422
prcmu_get_arm_opp(void)423 static inline int prcmu_get_arm_opp(void)
424 {
425 return ARM_100_OPP;
426 }
427
prcmu_set_ddr_opp(u8 opp)428 static inline int prcmu_set_ddr_opp(u8 opp)
429 {
430 return 0;
431 }
432
prcmu_get_ddr_opp(void)433 static inline int prcmu_get_ddr_opp(void)
434 {
435 return DDR_100_OPP;
436 }
437
prcmu_system_reset(u16 reset_code)438 static inline void prcmu_system_reset(u16 reset_code) {}
439
prcmu_get_reset_code(void)440 static inline u16 prcmu_get_reset_code(void)
441 {
442 return 0;
443 }
444
prcmu_ac_wake_req(void)445 static inline void prcmu_ac_wake_req(void) {}
446
prcmu_ac_sleep_req(void)447 static inline void prcmu_ac_sleep_req(void) {}
448
prcmu_modem_reset(void)449 static inline void prcmu_modem_reset(void) {}
450
prcmu_is_ac_wake_requested(void)451 static inline bool prcmu_is_ac_wake_requested(void)
452 {
453 return false;
454 }
455
prcmu_set_display_clocks(void)456 static inline int prcmu_set_display_clocks(void)
457 {
458 return 0;
459 }
460
prcmu_disable_dsipll(void)461 static inline int prcmu_disable_dsipll(void)
462 {
463 return 0;
464 }
465
prcmu_enable_dsipll(void)466 static inline int prcmu_enable_dsipll(void)
467 {
468 return 0;
469 }
470
prcmu_config_esram0_deep_sleep(u8 state)471 static inline int prcmu_config_esram0_deep_sleep(u8 state)
472 {
473 return 0;
474 }
475
prcmu_config_abb_event_readout(u32 abb_events)476 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
477
prcmu_get_abb_event_buffer(void __iomem ** buf)478 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
479 {
480 *buf = NULL;
481 }
482
483 #endif
484
485 /* PRCMU QoS APE OPP class */
486 #define PRCMU_QOS_APE_OPP 1
487 #define PRCMU_QOS_DDR_OPP 2
488 #define PRCMU_QOS_DEFAULT_VALUE -1
489
490 #ifdef CONFIG_UX500_PRCMU_QOS_POWER
491
492 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
493 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
494 void prcmu_qos_force_opp(int, s32);
495 int prcmu_qos_requirement(int pm_qos_class);
496 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
497 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
498 void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
499 int prcmu_qos_add_notifier(int prcmu_qos_class,
500 struct notifier_block *notifier);
501 int prcmu_qos_remove_notifier(int prcmu_qos_class,
502 struct notifier_block *notifier);
503
504 #else
505
prcmu_qos_get_cpufreq_opp_delay(void)506 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
507 {
508 return 0;
509 }
510
prcmu_qos_set_cpufreq_opp_delay(unsigned long n)511 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
512
prcmu_qos_force_opp(int prcmu_qos_class,s32 i)513 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
514
prcmu_qos_requirement(int prcmu_qos_class)515 static inline int prcmu_qos_requirement(int prcmu_qos_class)
516 {
517 return 0;
518 }
519
prcmu_qos_add_requirement(int prcmu_qos_class,char * name,s32 value)520 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
521 char *name, s32 value)
522 {
523 return 0;
524 }
525
prcmu_qos_update_requirement(int prcmu_qos_class,char * name,s32 new_value)526 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
527 char *name, s32 new_value)
528 {
529 return 0;
530 }
531
prcmu_qos_remove_requirement(int prcmu_qos_class,char * name)532 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
533 {
534 }
535
prcmu_qos_add_notifier(int prcmu_qos_class,struct notifier_block * notifier)536 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
537 struct notifier_block *notifier)
538 {
539 return 0;
540 }
prcmu_qos_remove_notifier(int prcmu_qos_class,struct notifier_block * notifier)541 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
542 struct notifier_block *notifier)
543 {
544 return 0;
545 }
546
547 #endif
548
549 #endif /* __MACH_PRCMU_H */
550