1 /*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/err.h>
23 #include <linux/slab.h>
24
25 #include <video/omapdss.h>
26 #include <plat/cpu.h>
27
28 #include "dss.h"
29 #include "dss_features.h"
30
31 /* Defines a generic omap register field */
32 struct dss_reg_field {
33 u8 start, end;
34 };
35
36 struct dss_param_range {
37 int min, max;
38 };
39
40 struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const u32 has_feature;
45
46 const int num_mgrs;
47 const int num_ovls;
48 const enum omap_display_type *supported_displays;
49 const enum omap_color_mode *supported_color_modes;
50 const enum omap_overlay_caps *overlay_caps;
51 const char * const *clksrc_names;
52 const struct dss_param_range *dss_params;
53
54 const u32 buffer_size_unit;
55 const u32 burst_size_unit;
56 };
57
58 /* This struct is assigned to one of the below during initialization */
59 static const struct omap_dss_features *omap_current_dss_features;
60
61 static const struct dss_reg_field omap2_dss_reg_fields[] = {
62 [FEAT_REG_FIRHINC] = { 11, 0 },
63 [FEAT_REG_FIRVINC] = { 27, 16 },
64 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
65 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
66 [FEAT_REG_FIFOSIZE] = { 8, 0 },
67 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
68 [FEAT_REG_VERTICALACCU] = { 25, 16 },
69 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
70 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
71 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
72 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
73 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
74 };
75
76 static const struct dss_reg_field omap3_dss_reg_fields[] = {
77 [FEAT_REG_FIRHINC] = { 12, 0 },
78 [FEAT_REG_FIRVINC] = { 28, 16 },
79 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
80 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
81 [FEAT_REG_FIFOSIZE] = { 10, 0 },
82 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
83 [FEAT_REG_VERTICALACCU] = { 25, 16 },
84 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
85 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
86 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
87 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
88 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
89 };
90
91 static const struct dss_reg_field omap4_dss_reg_fields[] = {
92 [FEAT_REG_FIRHINC] = { 12, 0 },
93 [FEAT_REG_FIRVINC] = { 28, 16 },
94 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
95 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
96 [FEAT_REG_FIFOSIZE] = { 15, 0 },
97 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
98 [FEAT_REG_VERTICALACCU] = { 26, 16 },
99 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
100 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
101 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
102 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
103 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
104 };
105
106 static const enum omap_display_type omap2_dss_supported_displays[] = {
107 /* OMAP_DSS_CHANNEL_LCD */
108 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
109
110 /* OMAP_DSS_CHANNEL_DIGIT */
111 OMAP_DISPLAY_TYPE_VENC,
112 };
113
114 static const enum omap_display_type omap3430_dss_supported_displays[] = {
115 /* OMAP_DSS_CHANNEL_LCD */
116 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
117 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
118
119 /* OMAP_DSS_CHANNEL_DIGIT */
120 OMAP_DISPLAY_TYPE_VENC,
121 };
122
123 static const enum omap_display_type omap3630_dss_supported_displays[] = {
124 /* OMAP_DSS_CHANNEL_LCD */
125 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
126 OMAP_DISPLAY_TYPE_DSI,
127
128 /* OMAP_DSS_CHANNEL_DIGIT */
129 OMAP_DISPLAY_TYPE_VENC,
130 };
131
132 static const enum omap_display_type omap4_dss_supported_displays[] = {
133 /* OMAP_DSS_CHANNEL_LCD */
134 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
135
136 /* OMAP_DSS_CHANNEL_DIGIT */
137 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
138
139 /* OMAP_DSS_CHANNEL_LCD2 */
140 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
141 OMAP_DISPLAY_TYPE_DSI,
142 };
143
144 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
145 /* OMAP_DSS_GFX */
146 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
147 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
148 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
149 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
150
151 /* OMAP_DSS_VIDEO1 */
152 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
153 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
154 OMAP_DSS_COLOR_UYVY,
155
156 /* OMAP_DSS_VIDEO2 */
157 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
158 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
159 OMAP_DSS_COLOR_UYVY,
160 };
161
162 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
163 /* OMAP_DSS_GFX */
164 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
165 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
166 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
167 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
168 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
169 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
170
171 /* OMAP_DSS_VIDEO1 */
172 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
173 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
174 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
175
176 /* OMAP_DSS_VIDEO2 */
177 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
178 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
179 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
180 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
181 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
182 };
183
184 static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
185 /* OMAP_DSS_GFX */
186 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
187 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
188 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
189 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
190 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
191 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
192 OMAP_DSS_COLOR_ARGB16_1555,
193
194 /* OMAP_DSS_VIDEO1 */
195 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
196 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
197 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
198 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
199 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
200 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
201 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
202 OMAP_DSS_COLOR_RGBX32,
203
204 /* OMAP_DSS_VIDEO2 */
205 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
206 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
207 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
208 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
209 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
210 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
211 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
212 OMAP_DSS_COLOR_RGBX32,
213
214 /* OMAP_DSS_VIDEO3 */
215 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
216 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
217 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
218 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
219 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
220 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
221 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
222 OMAP_DSS_COLOR_RGBX32,
223 };
224
225 static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
226 /* OMAP_DSS_GFX */
227 0,
228
229 /* OMAP_DSS_VIDEO1 */
230 OMAP_DSS_OVL_CAP_SCALE,
231
232 /* OMAP_DSS_VIDEO2 */
233 OMAP_DSS_OVL_CAP_SCALE,
234 };
235
236 static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
237 /* OMAP_DSS_GFX */
238 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
239
240 /* OMAP_DSS_VIDEO1 */
241 OMAP_DSS_OVL_CAP_SCALE,
242
243 /* OMAP_DSS_VIDEO2 */
244 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
245 };
246
247 static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
248 /* OMAP_DSS_GFX */
249 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
250
251 /* OMAP_DSS_VIDEO1 */
252 OMAP_DSS_OVL_CAP_SCALE,
253
254 /* OMAP_DSS_VIDEO2 */
255 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
256 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
257 };
258
259 static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
260 /* OMAP_DSS_GFX */
261 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
262 OMAP_DSS_OVL_CAP_ZORDER,
263
264 /* OMAP_DSS_VIDEO1 */
265 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
266 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
267
268 /* OMAP_DSS_VIDEO2 */
269 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
270 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
271
272 /* OMAP_DSS_VIDEO3 */
273 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
274 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
275 };
276
277 static const char * const omap2_dss_clk_source_names[] = {
278 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
279 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
280 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
281 };
282
283 static const char * const omap3_dss_clk_source_names[] = {
284 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
285 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
286 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
287 };
288
289 static const char * const omap4_dss_clk_source_names[] = {
290 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
291 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
292 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
293 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
294 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
295 };
296
297 static const struct dss_param_range omap2_dss_param_range[] = {
298 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
299 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
300 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
301 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
302 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
303 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
304 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
305 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
306 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
307 /*
308 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
309 * scaler cannot scale a image with width more than 768.
310 */
311 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
312 };
313
314 static const struct dss_param_range omap3_dss_param_range[] = {
315 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
316 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
317 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
318 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
319 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
320 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
321 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
322 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
323 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
324 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
325 };
326
327 static const struct dss_param_range omap4_dss_param_range[] = {
328 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
329 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
330 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
331 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
332 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
333 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
334 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
335 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
336 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
337 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
338 };
339
340 /* OMAP2 DSS Features */
341 static const struct omap_dss_features omap2_dss_features = {
342 .reg_fields = omap2_dss_reg_fields,
343 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
344
345 .has_feature =
346 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
347 FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
348 FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
349
350 .num_mgrs = 2,
351 .num_ovls = 3,
352 .supported_displays = omap2_dss_supported_displays,
353 .supported_color_modes = omap2_dss_supported_color_modes,
354 .overlay_caps = omap2_dss_overlay_caps,
355 .clksrc_names = omap2_dss_clk_source_names,
356 .dss_params = omap2_dss_param_range,
357 .buffer_size_unit = 1,
358 .burst_size_unit = 8,
359 };
360
361 /* OMAP3 DSS Features */
362 static const struct omap_dss_features omap3430_dss_features = {
363 .reg_fields = omap3_dss_reg_fields,
364 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
365
366 .has_feature =
367 FEAT_LCDENABLEPOL |
368 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
369 FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
370 FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
371 FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
372 FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
373 FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
374
375 .num_mgrs = 2,
376 .num_ovls = 3,
377 .supported_displays = omap3430_dss_supported_displays,
378 .supported_color_modes = omap3_dss_supported_color_modes,
379 .overlay_caps = omap3430_dss_overlay_caps,
380 .clksrc_names = omap3_dss_clk_source_names,
381 .dss_params = omap3_dss_param_range,
382 .buffer_size_unit = 1,
383 .burst_size_unit = 8,
384 };
385
386 static const struct omap_dss_features omap3630_dss_features = {
387 .reg_fields = omap3_dss_reg_fields,
388 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
389
390 .has_feature =
391 FEAT_LCDENABLEPOL |
392 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
393 FEAT_FUNCGATED |
394 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
395 FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
396 FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
397 FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
398
399 .num_mgrs = 2,
400 .num_ovls = 3,
401 .supported_displays = omap3630_dss_supported_displays,
402 .supported_color_modes = omap3_dss_supported_color_modes,
403 .overlay_caps = omap3630_dss_overlay_caps,
404 .clksrc_names = omap3_dss_clk_source_names,
405 .dss_params = omap3_dss_param_range,
406 .buffer_size_unit = 1,
407 .burst_size_unit = 8,
408 };
409
410 /* OMAP4 DSS Features */
411 /* For OMAP4430 ES 1.0 revision */
412 static const struct omap_dss_features omap4430_es1_0_dss_features = {
413 .reg_fields = omap4_dss_reg_fields,
414 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
415
416 .has_feature =
417 FEAT_MGR_LCD2 |
418 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
419 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
420 FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 |
421 FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V |
422 FEAT_ALPHA_FREE_ZORDER,
423
424 .num_mgrs = 3,
425 .num_ovls = 4,
426 .supported_displays = omap4_dss_supported_displays,
427 .supported_color_modes = omap4_dss_supported_color_modes,
428 .overlay_caps = omap4_dss_overlay_caps,
429 .clksrc_names = omap4_dss_clk_source_names,
430 .dss_params = omap4_dss_param_range,
431 .buffer_size_unit = 16,
432 .burst_size_unit = 16,
433 };
434
435 /* For all the other OMAP4 versions */
436 static const struct omap_dss_features omap4_dss_features = {
437 .reg_fields = omap4_dss_reg_fields,
438 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
439
440 .has_feature =
441 FEAT_MGR_LCD2 |
442 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
443 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
444 FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
445 FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
446 FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER,
447
448 .num_mgrs = 3,
449 .num_ovls = 4,
450 .supported_displays = omap4_dss_supported_displays,
451 .supported_color_modes = omap4_dss_supported_color_modes,
452 .overlay_caps = omap4_dss_overlay_caps,
453 .clksrc_names = omap4_dss_clk_source_names,
454 .dss_params = omap4_dss_param_range,
455 .buffer_size_unit = 16,
456 .burst_size_unit = 16,
457 };
458
459 #if defined(CONFIG_OMAP4_DSS_HDMI)
460 /* HDMI OMAP4 Functions*/
461 static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
462
463 .video_configure = ti_hdmi_4xxx_basic_configure,
464 .phy_enable = ti_hdmi_4xxx_phy_enable,
465 .phy_disable = ti_hdmi_4xxx_phy_disable,
466 .read_edid = ti_hdmi_4xxx_read_edid,
467 .detect = ti_hdmi_4xxx_detect,
468 .pll_enable = ti_hdmi_4xxx_pll_enable,
469 .pll_disable = ti_hdmi_4xxx_pll_disable,
470 .video_enable = ti_hdmi_4xxx_wp_video_start,
471 .dump_wrapper = ti_hdmi_4xxx_wp_dump,
472 .dump_core = ti_hdmi_4xxx_core_dump,
473 .dump_pll = ti_hdmi_4xxx_pll_dump,
474 .dump_phy = ti_hdmi_4xxx_phy_dump,
475 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
476 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
477 .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
478 #endif
479
480 };
481
dss_init_hdmi_ip_ops(struct hdmi_ip_data * ip_data)482 void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
483 {
484 if (cpu_is_omap44xx())
485 ip_data->ops = &omap4_hdmi_functions;
486 }
487 #endif
488
489 /* Functions returning values related to a DSS feature */
dss_feat_get_num_mgrs(void)490 int dss_feat_get_num_mgrs(void)
491 {
492 return omap_current_dss_features->num_mgrs;
493 }
494
dss_feat_get_num_ovls(void)495 int dss_feat_get_num_ovls(void)
496 {
497 return omap_current_dss_features->num_ovls;
498 }
499
dss_feat_get_param_min(enum dss_range_param param)500 unsigned long dss_feat_get_param_min(enum dss_range_param param)
501 {
502 return omap_current_dss_features->dss_params[param].min;
503 }
504
dss_feat_get_param_max(enum dss_range_param param)505 unsigned long dss_feat_get_param_max(enum dss_range_param param)
506 {
507 return omap_current_dss_features->dss_params[param].max;
508 }
509
dss_feat_get_supported_displays(enum omap_channel channel)510 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
511 {
512 return omap_current_dss_features->supported_displays[channel];
513 }
514
dss_feat_get_supported_color_modes(enum omap_plane plane)515 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
516 {
517 return omap_current_dss_features->supported_color_modes[plane];
518 }
519
dss_feat_get_overlay_caps(enum omap_plane plane)520 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
521 {
522 return omap_current_dss_features->overlay_caps[plane];
523 }
524
dss_feat_color_mode_supported(enum omap_plane plane,enum omap_color_mode color_mode)525 bool dss_feat_color_mode_supported(enum omap_plane plane,
526 enum omap_color_mode color_mode)
527 {
528 return omap_current_dss_features->supported_color_modes[plane] &
529 color_mode;
530 }
531
dss_feat_get_clk_source_name(enum omap_dss_clk_source id)532 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
533 {
534 return omap_current_dss_features->clksrc_names[id];
535 }
536
dss_feat_get_buffer_size_unit(void)537 u32 dss_feat_get_buffer_size_unit(void)
538 {
539 return omap_current_dss_features->buffer_size_unit;
540 }
541
dss_feat_get_burst_size_unit(void)542 u32 dss_feat_get_burst_size_unit(void)
543 {
544 return omap_current_dss_features->burst_size_unit;
545 }
546
547 /* DSS has_feature check */
dss_has_feature(enum dss_feat_id id)548 bool dss_has_feature(enum dss_feat_id id)
549 {
550 return omap_current_dss_features->has_feature & id;
551 }
552
dss_feat_get_reg_field(enum dss_feat_reg_field id,u8 * start,u8 * end)553 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
554 {
555 if (id >= omap_current_dss_features->num_reg_fields)
556 BUG();
557
558 *start = omap_current_dss_features->reg_fields[id].start;
559 *end = omap_current_dss_features->reg_fields[id].end;
560 }
561
dss_features_init(void)562 void dss_features_init(void)
563 {
564 if (cpu_is_omap24xx())
565 omap_current_dss_features = &omap2_dss_features;
566 else if (cpu_is_omap3630())
567 omap_current_dss_features = &omap3630_dss_features;
568 else if (cpu_is_omap34xx())
569 omap_current_dss_features = &omap3430_dss_features;
570 else if (omap_rev() == OMAP4430_REV_ES1_0)
571 omap_current_dss_features = &omap4430_es1_0_dss_features;
572 else if (cpu_is_omap44xx())
573 omap_current_dss_features = &omap4_dss_features;
574 else
575 DSSWARN("Unsupported OMAP version");
576 }
577