1 /*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef __OMAP2_DSS_H
24 #define __OMAP2_DSS_H
25
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
27 #define DEBUG
28 #endif
29
30 #ifdef DEBUG
31 extern bool dss_debug;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
34 if (dss_debug) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
36 ## __VA_ARGS__)
37 #else
38 #define DSSDBG(format, ...) \
39 if (dss_debug) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
41 #endif
42
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
45 if (dss_debug) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
48 __func__, \
49 ## __VA_ARGS__)
50 #else
51 #define DSSDBGF(format, ...) \
52 if (dss_debug) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
55 __func__, \
56 ## __VA_ARGS__)
57 #endif
58
59 #else /* DEBUG */
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
62 #endif
63
64
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
68 ## __VA_ARGS__)
69 #else
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
72 #endif
73
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
77 ## __VA_ARGS__)
78 #else
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
81 #endif
82
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
86 ## __VA_ARGS__)
87 #else
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
90 #endif
91
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
99
100 enum dss_io_pad_mode {
101 DSS_IO_PAD_MODE_RESET,
102 DSS_IO_PAD_MODE_RFBI,
103 DSS_IO_PAD_MODE_BYPASS,
104 };
105
106 enum dss_hdmi_venc_clk_source_select {
107 DSS_VENC_TV_CLK = 0,
108 DSS_HDMI_M_PCLK = 1,
109 };
110
111 enum dss_dsi_content_type {
112 DSS_DSI_CONTENT_DCS,
113 DSS_DSI_CONTENT_GENERIC,
114 };
115
116 struct dss_clock_info {
117 /* rates that we get with dividers below */
118 unsigned long fck;
119
120 /* dividers */
121 u16 fck_div;
122 };
123
124 struct dispc_clock_info {
125 /* rates that we get with dividers below */
126 unsigned long lck;
127 unsigned long pck;
128
129 /* dividers */
130 u16 lck_div;
131 u16 pck_div;
132 };
133
134 struct dsi_clock_info {
135 /* rates that we get with dividers below */
136 unsigned long fint;
137 unsigned long clkin4ddr;
138 unsigned long clkin;
139 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
140 * OMAP4: PLLx_CLK1 */
141 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
142 * OMAP4: PLLx_CLK2 */
143 unsigned long lp_clk;
144
145 /* dividers */
146 u16 regn;
147 u16 regm;
148 u16 regm_dispc; /* OMAP3: REGM3
149 * OMAP4: REGM4 */
150 u16 regm_dsi; /* OMAP3: REGM4
151 * OMAP4: REGM5 */
152 u16 lp_clk_div;
153
154 u8 highfreq;
155 bool use_sys_clk;
156 };
157
158 struct seq_file;
159 struct platform_device;
160
161 /* core */
162 struct bus_type *dss_get_bus(void);
163 struct regulator *dss_get_vdds_dsi(void);
164 struct regulator *dss_get_vdds_sdi(void);
165
166 /* apply */
167 void dss_apply_init(void);
168 int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr);
169 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
170 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
171 int omap_dss_mgr_apply(struct omap_overlay_manager *mgr);
172
173 int dss_mgr_enable(struct omap_overlay_manager *mgr);
174 void dss_mgr_disable(struct omap_overlay_manager *mgr);
175 int dss_mgr_set_info(struct omap_overlay_manager *mgr,
176 struct omap_overlay_manager_info *info);
177 void dss_mgr_get_info(struct omap_overlay_manager *mgr,
178 struct omap_overlay_manager_info *info);
179 int dss_mgr_set_device(struct omap_overlay_manager *mgr,
180 struct omap_dss_device *dssdev);
181 int dss_mgr_unset_device(struct omap_overlay_manager *mgr);
182
183 bool dss_ovl_is_enabled(struct omap_overlay *ovl);
184 int dss_ovl_enable(struct omap_overlay *ovl);
185 int dss_ovl_disable(struct omap_overlay *ovl);
186 int dss_ovl_set_info(struct omap_overlay *ovl,
187 struct omap_overlay_info *info);
188 void dss_ovl_get_info(struct omap_overlay *ovl,
189 struct omap_overlay_info *info);
190 int dss_ovl_set_manager(struct omap_overlay *ovl,
191 struct omap_overlay_manager *mgr);
192 int dss_ovl_unset_manager(struct omap_overlay *ovl);
193
194 /* display */
195 int dss_suspend_all_devices(void);
196 int dss_resume_all_devices(void);
197 void dss_disable_all_devices(void);
198
199 void dss_init_device(struct platform_device *pdev,
200 struct omap_dss_device *dssdev);
201 void dss_uninit_device(struct platform_device *pdev,
202 struct omap_dss_device *dssdev);
203 bool dss_use_replication(struct omap_dss_device *dssdev,
204 enum omap_color_mode mode);
205 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
206 u32 fifo_size, u32 burst_size,
207 u32 *fifo_low, u32 *fifo_high);
208
209 /* manager */
210 int dss_init_overlay_managers(struct platform_device *pdev);
211 void dss_uninit_overlay_managers(struct platform_device *pdev);
212 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
213 const struct omap_overlay_manager_info *info);
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
215 struct omap_dss_device *dssdev,
216 struct omap_overlay_manager_info *info,
217 struct omap_overlay_info **overlay_infos);
218
219 /* overlay */
220 void dss_init_overlays(struct platform_device *pdev);
221 void dss_uninit_overlays(struct platform_device *pdev);
222 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
223 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
224 int dss_ovl_simple_check(struct omap_overlay *ovl,
225 const struct omap_overlay_info *info);
226 int dss_ovl_check(struct omap_overlay *ovl,
227 struct omap_overlay_info *info, struct omap_dss_device *dssdev);
228
229 /* DSS */
230 int dss_init_platform_driver(void);
231 void dss_uninit_platform_driver(void);
232
233 int dss_runtime_get(void);
234 void dss_runtime_put(void);
235
236 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
237 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
238 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
239 void dss_dump_clocks(struct seq_file *s);
240
241 void dss_dump_regs(struct seq_file *s);
242 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
243 void dss_debug_dump_clocks(struct seq_file *s);
244 #endif
245
246 void dss_sdi_init(u8 datapairs);
247 int dss_sdi_enable(void);
248 void dss_sdi_disable(void);
249
250 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
251 void dss_select_dsi_clk_source(int dsi_module,
252 enum omap_dss_clk_source clk_src);
253 void dss_select_lcd_clk_source(enum omap_channel channel,
254 enum omap_dss_clk_source clk_src);
255 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
256 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
257 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
258
259 void dss_set_venc_output(enum omap_dss_venc_type type);
260 void dss_set_dac_pwrdn_bgz(bool enable);
261
262 unsigned long dss_get_dpll4_rate(void);
263 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
264 int dss_set_clock_div(struct dss_clock_info *cinfo);
265 int dss_get_clock_div(struct dss_clock_info *cinfo);
266 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
267 struct dss_clock_info *dss_cinfo,
268 struct dispc_clock_info *dispc_cinfo);
269
270 /* SDI */
271 #ifdef CONFIG_OMAP2_DSS_SDI
272 int sdi_init(void);
273 void sdi_exit(void);
274 int sdi_init_display(struct omap_dss_device *display);
275 #else
sdi_init(void)276 static inline int sdi_init(void)
277 {
278 return 0;
279 }
sdi_exit(void)280 static inline void sdi_exit(void)
281 {
282 }
283 #endif
284
285 /* DSI */
286 #ifdef CONFIG_OMAP2_DSS_DSI
287
288 struct dentry;
289 struct file_operations;
290
291 int dsi_init_platform_driver(void);
292 void dsi_uninit_platform_driver(void);
293
294 int dsi_runtime_get(struct platform_device *dsidev);
295 void dsi_runtime_put(struct platform_device *dsidev);
296
297 void dsi_dump_clocks(struct seq_file *s);
298 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
299 const struct file_operations *debug_fops);
300 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
301 const struct file_operations *debug_fops);
302
303 int dsi_init_display(struct omap_dss_device *display);
304 void dsi_irq_handler(void);
305 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
306
307 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
308 int dsi_pll_set_clock_div(struct platform_device *dsidev,
309 struct dsi_clock_info *cinfo);
310 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
311 unsigned long req_pck, struct dsi_clock_info *cinfo,
312 struct dispc_clock_info *dispc_cinfo);
313 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
314 bool enable_hsdiv);
315 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
316 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
317 u32 fifo_size, u32 burst_size,
318 u32 *fifo_low, u32 *fifo_high);
319 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
320 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
321 struct platform_device *dsi_get_dsidev_from_id(int module);
322 #else
dsi_init_platform_driver(void)323 static inline int dsi_init_platform_driver(void)
324 {
325 return 0;
326 }
dsi_uninit_platform_driver(void)327 static inline void dsi_uninit_platform_driver(void)
328 {
329 }
dsi_runtime_get(struct platform_device * dsidev)330 static inline int dsi_runtime_get(struct platform_device *dsidev)
331 {
332 return 0;
333 }
dsi_runtime_put(struct platform_device * dsidev)334 static inline void dsi_runtime_put(struct platform_device *dsidev)
335 {
336 }
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)337 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
338 {
339 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
340 return 0;
341 }
dsi_get_pll_hsdiv_dispc_rate(struct platform_device * dsidev)342 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
343 {
344 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
345 return 0;
346 }
dsi_pll_set_clock_div(struct platform_device * dsidev,struct dsi_clock_info * cinfo)347 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
348 struct dsi_clock_info *cinfo)
349 {
350 WARN("%s: DSI not compiled in\n", __func__);
351 return -ENODEV;
352 }
dsi_pll_calc_clock_div_pck(struct platform_device * dsidev,bool is_tft,unsigned long req_pck,struct dsi_clock_info * dsi_cinfo,struct dispc_clock_info * dispc_cinfo)353 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
354 bool is_tft, unsigned long req_pck,
355 struct dsi_clock_info *dsi_cinfo,
356 struct dispc_clock_info *dispc_cinfo)
357 {
358 WARN("%s: DSI not compiled in\n", __func__);
359 return -ENODEV;
360 }
dsi_pll_init(struct platform_device * dsidev,bool enable_hsclk,bool enable_hsdiv)361 static inline int dsi_pll_init(struct platform_device *dsidev,
362 bool enable_hsclk, bool enable_hsdiv)
363 {
364 WARN("%s: DSI not compiled in\n", __func__);
365 return -ENODEV;
366 }
dsi_pll_uninit(struct platform_device * dsidev,bool disconnect_lanes)367 static inline void dsi_pll_uninit(struct platform_device *dsidev,
368 bool disconnect_lanes)
369 {
370 }
dsi_wait_pll_hsdiv_dispc_active(struct platform_device * dsidev)371 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
372 {
373 }
dsi_wait_pll_hsdiv_dsi_active(struct platform_device * dsidev)374 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
375 {
376 }
dsi_get_dsidev_from_id(int module)377 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
378 {
379 WARN("%s: DSI not compiled in, returning platform device as NULL\n",
380 __func__);
381 return NULL;
382 }
383 #endif
384
385 /* DPI */
386 #ifdef CONFIG_OMAP2_DSS_DPI
387 int dpi_init(void);
388 void dpi_exit(void);
389 int dpi_init_display(struct omap_dss_device *dssdev);
390 #else
dpi_init(void)391 static inline int dpi_init(void)
392 {
393 return 0;
394 }
dpi_exit(void)395 static inline void dpi_exit(void)
396 {
397 }
398 #endif
399
400 /* DISPC */
401 int dispc_init_platform_driver(void);
402 void dispc_uninit_platform_driver(void);
403 void dispc_dump_clocks(struct seq_file *s);
404 void dispc_dump_irqs(struct seq_file *s);
405 void dispc_dump_regs(struct seq_file *s);
406 void dispc_irq_handler(void);
407 void dispc_fake_vsync_irq(void);
408
409 int dispc_runtime_get(void);
410 void dispc_runtime_put(void);
411
412 void dispc_enable_sidle(void);
413 void dispc_disable_sidle(void);
414
415 void dispc_lcd_enable_signal_polarity(bool act_high);
416 void dispc_lcd_enable_signal(bool enable);
417 void dispc_pck_free_enable(bool enable);
418 void dispc_set_digit_size(u16 width, u16 height);
419 void dispc_enable_fifomerge(bool enable);
420 void dispc_enable_gamma_table(bool enable);
421 void dispc_set_loadmode(enum omap_dss_load_mode mode);
422
423 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
424 unsigned long dispc_fclk_rate(void);
425 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
426 struct dispc_clock_info *cinfo);
427 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
428 struct dispc_clock_info *cinfo);
429
430
431 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
432 u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
433 u32 dispc_ovl_get_burst_size(enum omap_plane plane);
434 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
435 bool ilace, bool replication);
436 int dispc_ovl_enable(enum omap_plane plane, bool enable);
437 void dispc_ovl_set_channel_out(enum omap_plane plane,
438 enum omap_channel channel);
439
440 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
441 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
442 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
443 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
444 bool dispc_mgr_go_busy(enum omap_channel channel);
445 void dispc_mgr_go(enum omap_channel channel);
446 bool dispc_mgr_is_enabled(enum omap_channel channel);
447 void dispc_mgr_enable(enum omap_channel channel, bool enable);
448 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
449 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
450 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
451 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
452 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
453 enum omap_lcd_display_type type);
454 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
455 struct omap_video_timings *timings);
456 void dispc_mgr_set_pol_freq(enum omap_channel channel,
457 enum omap_panel_config config, u8 acbi, u8 acb);
458 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
459 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
460 int dispc_mgr_set_clock_div(enum omap_channel channel,
461 struct dispc_clock_info *cinfo);
462 int dispc_mgr_get_clock_div(enum omap_channel channel,
463 struct dispc_clock_info *cinfo);
464 void dispc_mgr_setup(enum omap_channel channel,
465 struct omap_overlay_manager_info *info);
466
467 /* VENC */
468 #ifdef CONFIG_OMAP2_DSS_VENC
469 int venc_init_platform_driver(void);
470 void venc_uninit_platform_driver(void);
471 void venc_dump_regs(struct seq_file *s);
472 int venc_init_display(struct omap_dss_device *display);
473 unsigned long venc_get_pixel_clock(void);
474 #else
venc_init_platform_driver(void)475 static inline int venc_init_platform_driver(void)
476 {
477 return 0;
478 }
venc_uninit_platform_driver(void)479 static inline void venc_uninit_platform_driver(void)
480 {
481 }
venc_get_pixel_clock(void)482 static inline unsigned long venc_get_pixel_clock(void)
483 {
484 WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
485 return 0;
486 }
487 #endif
488
489 /* HDMI */
490 #ifdef CONFIG_OMAP4_DSS_HDMI
491 int hdmi_init_platform_driver(void);
492 void hdmi_uninit_platform_driver(void);
493 int hdmi_init_display(struct omap_dss_device *dssdev);
494 unsigned long hdmi_get_pixel_clock(void);
495 void hdmi_dump_regs(struct seq_file *s);
496 #else
hdmi_init_display(struct omap_dss_device * dssdev)497 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
498 {
499 return 0;
500 }
hdmi_init_platform_driver(void)501 static inline int hdmi_init_platform_driver(void)
502 {
503 return 0;
504 }
hdmi_uninit_platform_driver(void)505 static inline void hdmi_uninit_platform_driver(void)
506 {
507 }
hdmi_get_pixel_clock(void)508 static inline unsigned long hdmi_get_pixel_clock(void)
509 {
510 WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
511 return 0;
512 }
513 #endif
514 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
515 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
516 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
517 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
518 struct omap_video_timings *timings);
519 int omapdss_hdmi_read_edid(u8 *buf, int len);
520 bool omapdss_hdmi_detect(void);
521 int hdmi_panel_init(void);
522 void hdmi_panel_exit(void);
523
524 /* RFBI */
525 #ifdef CONFIG_OMAP2_DSS_RFBI
526 int rfbi_init_platform_driver(void);
527 void rfbi_uninit_platform_driver(void);
528 void rfbi_dump_regs(struct seq_file *s);
529 int rfbi_init_display(struct omap_dss_device *display);
530 #else
rfbi_init_platform_driver(void)531 static inline int rfbi_init_platform_driver(void)
532 {
533 return 0;
534 }
rfbi_uninit_platform_driver(void)535 static inline void rfbi_uninit_platform_driver(void)
536 {
537 }
538 #endif
539
540
541 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned * irq_arr)542 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
543 {
544 int b;
545 for (b = 0; b < 32; ++b) {
546 if (irqstatus & (1 << b))
547 irq_arr[b]++;
548 }
549 }
550 #endif
551
552 #endif
553