1 /*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
28 #include <linux/list.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/gpio.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35
36 #include <mach/cputype.h>
37
38 #include <asm/mach-types.h>
39
40 #include "musb_core.h"
41
42 #ifdef CONFIG_MACH_DAVINCI_EVM
43 #define GPIO_nVBUS_DRV 160
44 #endif
45
46 #include "davinci.h"
47 #include "cppi_dma.h"
48
49
50 #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
51 #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
52
53 struct davinci_glue {
54 struct device *dev;
55 struct platform_device *musb;
56 struct clk *clk;
57 };
58
59 /* REVISIT (PM) we should be able to keep the PHY in low power mode most
60 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
61 * and, when in host mode, autosuspending idle root ports... PHYPLLON
62 * (overriding SUSPENDM?) then likely needs to stay off.
63 */
64
phy_on(void)65 static inline void phy_on(void)
66 {
67 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
68
69 /* power everything up; start the on-chip PHY and its PLL */
70 phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
71 phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
72 __raw_writel(phy_ctrl, USB_PHY_CTRL);
73
74 /* wait for PLL to lock before proceeding */
75 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
76 cpu_relax();
77 }
78
phy_off(void)79 static inline void phy_off(void)
80 {
81 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
82
83 /* powerdown the on-chip PHY, its PLL, and the OTG block */
84 phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
85 phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
86 __raw_writel(phy_ctrl, USB_PHY_CTRL);
87 }
88
89 static int dma_off = 1;
90
davinci_musb_enable(struct musb * musb)91 static void davinci_musb_enable(struct musb *musb)
92 {
93 u32 tmp, old, val;
94
95 /* workaround: setup irqs through both register sets */
96 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
97 << DAVINCI_USB_TXINT_SHIFT;
98 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
99 old = tmp;
100 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
101 << DAVINCI_USB_RXINT_SHIFT;
102 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
103 tmp |= old;
104
105 val = ~MUSB_INTR_SOF;
106 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
107 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
108
109 if (is_dma_capable() && !dma_off)
110 printk(KERN_WARNING "%s %s: dma not reactivated\n",
111 __FILE__, __func__);
112 else
113 dma_off = 0;
114
115 /* force a DRVVBUS irq so we can start polling for ID change */
116 if (is_otg_enabled(musb))
117 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
118 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
119 }
120
121 /*
122 * Disable the HDRC and flush interrupts
123 */
davinci_musb_disable(struct musb * musb)124 static void davinci_musb_disable(struct musb *musb)
125 {
126 /* because we don't set CTRLR.UINT, "important" to:
127 * - not read/write INTRUSB/INTRUSBE
128 * - (except during initial setup, as workaround)
129 * - use INTSETR/INTCLRR instead
130 */
131 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
132 DAVINCI_USB_USBINT_MASK
133 | DAVINCI_USB_TXINT_MASK
134 | DAVINCI_USB_RXINT_MASK);
135 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
136 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
137
138 if (is_dma_capable() && !dma_off)
139 WARNING("dma still active\n");
140 }
141
142
143 #define portstate(stmt) stmt
144
145 /*
146 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
147 * which doesn't wire DRVVBUS to the FET that switches it. Unclear
148 * if that's a problem with the DM6446 chip or just with that board.
149 *
150 * In either case, the DM355 EVM automates DRVVBUS the normal way,
151 * when J10 is out, and TI documents it as handling OTG.
152 */
153
154 #ifdef CONFIG_MACH_DAVINCI_EVM
155
156 static int vbus_state = -1;
157
158 /* I2C operations are always synchronous, and require a task context.
159 * With unloaded systems, using the shared workqueue seems to suffice
160 * to satisfy the 100msec A_WAIT_VRISE timeout...
161 */
evm_deferred_drvvbus(struct work_struct * ignored)162 static void evm_deferred_drvvbus(struct work_struct *ignored)
163 {
164 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
165 vbus_state = !vbus_state;
166 }
167
168 #endif /* EVM */
169
davinci_musb_source_power(struct musb * musb,int is_on,int immediate)170 static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
171 {
172 #ifdef CONFIG_MACH_DAVINCI_EVM
173 if (is_on)
174 is_on = 1;
175
176 if (vbus_state == is_on)
177 return;
178 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
179
180 if (machine_is_davinci_evm()) {
181 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
182
183 if (immediate)
184 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
185 else
186 schedule_work(&evm_vbus_work);
187 }
188 if (immediate)
189 vbus_state = is_on;
190 #endif
191 }
192
davinci_musb_set_vbus(struct musb * musb,int is_on)193 static void davinci_musb_set_vbus(struct musb *musb, int is_on)
194 {
195 WARN_ON(is_on && is_peripheral_active(musb));
196 davinci_musb_source_power(musb, is_on, 0);
197 }
198
199
200 #define POLL_SECONDS 2
201
202 static struct timer_list otg_workaround;
203
otg_timer(unsigned long _musb)204 static void otg_timer(unsigned long _musb)
205 {
206 struct musb *musb = (void *)_musb;
207 void __iomem *mregs = musb->mregs;
208 u8 devctl;
209 unsigned long flags;
210
211 /* We poll because DaVinci's won't expose several OTG-critical
212 * status change events (from the transceiver) otherwise.
213 */
214 devctl = musb_readb(mregs, MUSB_DEVCTL);
215 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
216 otg_state_string(musb->xceiv->state));
217
218 spin_lock_irqsave(&musb->lock, flags);
219 switch (musb->xceiv->state) {
220 case OTG_STATE_A_WAIT_VFALL:
221 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
222 * seems to mis-handle session "start" otherwise (or in our
223 * case "recover"), in routine "VBUS was valid by the time
224 * VBUSERR got reported during enumeration" cases.
225 */
226 if (devctl & MUSB_DEVCTL_VBUS) {
227 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
228 break;
229 }
230 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
231 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
232 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
233 break;
234 case OTG_STATE_B_IDLE:
235 if (!is_peripheral_enabled(musb))
236 break;
237
238 /* There's no ID-changed IRQ, so we have no good way to tell
239 * when to switch to the A-Default state machine (by setting
240 * the DEVCTL.SESSION flag).
241 *
242 * Workaround: whenever we're in B_IDLE, try setting the
243 * session flag every few seconds. If it works, ID was
244 * grounded and we're now in the A-Default state machine.
245 *
246 * NOTE setting the session flag is _supposed_ to trigger
247 * SRP, but clearly it doesn't.
248 */
249 musb_writeb(mregs, MUSB_DEVCTL,
250 devctl | MUSB_DEVCTL_SESSION);
251 devctl = musb_readb(mregs, MUSB_DEVCTL);
252 if (devctl & MUSB_DEVCTL_BDEVICE)
253 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
254 else
255 musb->xceiv->state = OTG_STATE_A_IDLE;
256 break;
257 default:
258 break;
259 }
260 spin_unlock_irqrestore(&musb->lock, flags);
261 }
262
davinci_musb_interrupt(int irq,void * __hci)263 static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
264 {
265 unsigned long flags;
266 irqreturn_t retval = IRQ_NONE;
267 struct musb *musb = __hci;
268 void __iomem *tibase = musb->ctrl_base;
269 struct cppi *cppi;
270 u32 tmp;
271
272 spin_lock_irqsave(&musb->lock, flags);
273
274 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
275 * the Mentor registers (except for setup), use the TI ones and EOI.
276 *
277 * Docs describe irq "vector" registers associated with the CPPI and
278 * USB EOI registers. These hold a bitmask corresponding to the
279 * current IRQ, not an irq handler address. Would using those bits
280 * resolve some of the races observed in this dispatch code??
281 */
282
283 /* CPPI interrupts share the same IRQ line, but have their own
284 * mask, state, "vector", and EOI registers.
285 */
286 cppi = container_of(musb->dma_controller, struct cppi, controller);
287 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
288 retval = cppi_interrupt(irq, __hci);
289
290 /* ack and handle non-CPPI interrupts */
291 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
292 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
293 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
294
295 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
296 >> DAVINCI_USB_RXINT_SHIFT;
297 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
298 >> DAVINCI_USB_TXINT_SHIFT;
299 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
300 >> DAVINCI_USB_USBINT_SHIFT;
301
302 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
303 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
304 * switch appropriately between halves of the OTG state machine.
305 * Managing DEVCTL.SESSION per Mentor docs requires we know its
306 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
307 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
308 */
309 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
310 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
311 void __iomem *mregs = musb->mregs;
312 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
313 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
314
315 err = is_host_enabled(musb)
316 && (musb->int_usb & MUSB_INTR_VBUSERROR);
317 if (err) {
318 /* The Mentor core doesn't debounce VBUS as needed
319 * to cope with device connect current spikes. This
320 * means it's not uncommon for bus-powered devices
321 * to get VBUS errors during enumeration.
322 *
323 * This is a workaround, but newer RTL from Mentor
324 * seems to allow a better one: "re"starting sessions
325 * without waiting (on EVM, a **long** time) for VBUS
326 * to stop registering in devctl.
327 */
328 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
329 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
330 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
331 WARNING("VBUS error workaround (delay coming)\n");
332 } else if (is_host_enabled(musb) && drvvbus) {
333 MUSB_HST_MODE(musb);
334 musb->xceiv->default_a = 1;
335 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
336 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
337 del_timer(&otg_workaround);
338 } else {
339 musb->is_active = 0;
340 MUSB_DEV_MODE(musb);
341 musb->xceiv->default_a = 0;
342 musb->xceiv->state = OTG_STATE_B_IDLE;
343 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
344 }
345
346 /* NOTE: this must complete poweron within 100 msec
347 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
348 */
349 davinci_musb_source_power(musb, drvvbus, 0);
350 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
351 drvvbus ? "on" : "off",
352 otg_state_string(musb->xceiv->state),
353 err ? " ERROR" : "",
354 devctl);
355 retval = IRQ_HANDLED;
356 }
357
358 if (musb->int_tx || musb->int_rx || musb->int_usb)
359 retval |= musb_interrupt(musb);
360
361 /* irq stays asserted until EOI is written */
362 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
363
364 /* poll for ID change */
365 if (is_otg_enabled(musb)
366 && musb->xceiv->state == OTG_STATE_B_IDLE)
367 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
368
369 spin_unlock_irqrestore(&musb->lock, flags);
370
371 return retval;
372 }
373
davinci_musb_set_mode(struct musb * musb,u8 mode)374 static int davinci_musb_set_mode(struct musb *musb, u8 mode)
375 {
376 /* EVM can't do this (right?) */
377 return -EIO;
378 }
379
davinci_musb_init(struct musb * musb)380 static int davinci_musb_init(struct musb *musb)
381 {
382 void __iomem *tibase = musb->ctrl_base;
383 u32 revision;
384
385 usb_nop_xceiv_register();
386 musb->xceiv = otg_get_transceiver();
387 if (!musb->xceiv)
388 return -ENODEV;
389
390 musb->mregs += DAVINCI_BASE_OFFSET;
391
392 /* returns zero if e.g. not clocked */
393 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
394 if (revision == 0)
395 goto fail;
396
397 if (is_host_enabled(musb))
398 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
399
400 davinci_musb_source_power(musb, 0, 1);
401
402 /* dm355 EVM swaps D+/D- for signal integrity, and
403 * is clocked from the main 24 MHz crystal.
404 */
405 if (machine_is_davinci_dm355_evm()) {
406 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
407
408 phy_ctrl &= ~(3 << 9);
409 phy_ctrl |= USBPHY_DATAPOL;
410 __raw_writel(phy_ctrl, USB_PHY_CTRL);
411 }
412
413 /* On dm355, the default-A state machine needs DRVVBUS control.
414 * If we won't be a host, there's no need to turn it on.
415 */
416 if (cpu_is_davinci_dm355()) {
417 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
418
419 if (is_host_enabled(musb)) {
420 deepsleep &= ~DRVVBUS_OVERRIDE;
421 } else {
422 deepsleep &= ~DRVVBUS_FORCE;
423 deepsleep |= DRVVBUS_OVERRIDE;
424 }
425 __raw_writel(deepsleep, DM355_DEEPSLEEP);
426 }
427
428 /* reset the controller */
429 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
430
431 /* start the on-chip PHY and its PLL */
432 phy_on();
433
434 msleep(5);
435
436 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
437 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
438 revision, __raw_readl(USB_PHY_CTRL),
439 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
440
441 musb->isr = davinci_musb_interrupt;
442 return 0;
443
444 fail:
445 otg_put_transceiver(musb->xceiv);
446 usb_nop_xceiv_unregister();
447 return -ENODEV;
448 }
449
davinci_musb_exit(struct musb * musb)450 static int davinci_musb_exit(struct musb *musb)
451 {
452 if (is_host_enabled(musb))
453 del_timer_sync(&otg_workaround);
454
455 /* force VBUS off */
456 if (cpu_is_davinci_dm355()) {
457 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
458
459 deepsleep &= ~DRVVBUS_FORCE;
460 deepsleep |= DRVVBUS_OVERRIDE;
461 __raw_writel(deepsleep, DM355_DEEPSLEEP);
462 }
463
464 davinci_musb_source_power(musb, 0 /*off*/, 1);
465
466 /* delay, to avoid problems with module reload */
467 if (is_host_enabled(musb) && musb->xceiv->default_a) {
468 int maxdelay = 30;
469 u8 devctl, warn = 0;
470
471 /* if there's no peripheral connected, this can take a
472 * long time to fall, especially on EVM with huge C133.
473 */
474 do {
475 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
476 if (!(devctl & MUSB_DEVCTL_VBUS))
477 break;
478 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
479 warn = devctl & MUSB_DEVCTL_VBUS;
480 dev_dbg(musb->controller, "VBUS %d\n",
481 warn >> MUSB_DEVCTL_VBUS_SHIFT);
482 }
483 msleep(1000);
484 maxdelay--;
485 } while (maxdelay > 0);
486
487 /* in OTG mode, another host might be connected */
488 if (devctl & MUSB_DEVCTL_VBUS)
489 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
490 }
491
492 phy_off();
493
494 otg_put_transceiver(musb->xceiv);
495 usb_nop_xceiv_unregister();
496
497 return 0;
498 }
499
500 static const struct musb_platform_ops davinci_ops = {
501 .init = davinci_musb_init,
502 .exit = davinci_musb_exit,
503
504 .enable = davinci_musb_enable,
505 .disable = davinci_musb_disable,
506
507 .set_mode = davinci_musb_set_mode,
508
509 .set_vbus = davinci_musb_set_vbus,
510 };
511
512 static u64 davinci_dmamask = DMA_BIT_MASK(32);
513
davinci_probe(struct platform_device * pdev)514 static int __init davinci_probe(struct platform_device *pdev)
515 {
516 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
517 struct platform_device *musb;
518 struct davinci_glue *glue;
519 struct clk *clk;
520
521 int ret = -ENOMEM;
522
523 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
524 if (!glue) {
525 dev_err(&pdev->dev, "failed to allocate glue context\n");
526 goto err0;
527 }
528
529 musb = platform_device_alloc("musb-hdrc", -1);
530 if (!musb) {
531 dev_err(&pdev->dev, "failed to allocate musb device\n");
532 goto err1;
533 }
534
535 clk = clk_get(&pdev->dev, "usb");
536 if (IS_ERR(clk)) {
537 dev_err(&pdev->dev, "failed to get clock\n");
538 ret = PTR_ERR(clk);
539 goto err2;
540 }
541
542 ret = clk_enable(clk);
543 if (ret) {
544 dev_err(&pdev->dev, "failed to enable clock\n");
545 goto err3;
546 }
547
548 musb->dev.parent = &pdev->dev;
549 musb->dev.dma_mask = &davinci_dmamask;
550 musb->dev.coherent_dma_mask = davinci_dmamask;
551
552 glue->dev = &pdev->dev;
553 glue->musb = musb;
554 glue->clk = clk;
555
556 pdata->platform_ops = &davinci_ops;
557
558 platform_set_drvdata(pdev, glue);
559
560 ret = platform_device_add_resources(musb, pdev->resource,
561 pdev->num_resources);
562 if (ret) {
563 dev_err(&pdev->dev, "failed to add resources\n");
564 goto err4;
565 }
566
567 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
568 if (ret) {
569 dev_err(&pdev->dev, "failed to add platform_data\n");
570 goto err4;
571 }
572
573 ret = platform_device_add(musb);
574 if (ret) {
575 dev_err(&pdev->dev, "failed to register musb device\n");
576 goto err4;
577 }
578
579 return 0;
580
581 err4:
582 clk_disable(clk);
583
584 err3:
585 clk_put(clk);
586
587 err2:
588 platform_device_put(musb);
589
590 err1:
591 kfree(glue);
592
593 err0:
594 return ret;
595 }
596
davinci_remove(struct platform_device * pdev)597 static int __exit davinci_remove(struct platform_device *pdev)
598 {
599 struct davinci_glue *glue = platform_get_drvdata(pdev);
600
601 platform_device_del(glue->musb);
602 platform_device_put(glue->musb);
603 clk_disable(glue->clk);
604 clk_put(glue->clk);
605 kfree(glue);
606
607 return 0;
608 }
609
610 static struct platform_driver davinci_driver = {
611 .remove = __exit_p(davinci_remove),
612 .driver = {
613 .name = "musb-davinci",
614 },
615 };
616
617 MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
618 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
619 MODULE_LICENSE("GPL v2");
620
davinci_init(void)621 static int __init davinci_init(void)
622 {
623 return platform_driver_probe(&davinci_driver, davinci_probe);
624 }
625 subsys_initcall(davinci_init);
626
davinci_exit(void)627 static void __exit davinci_exit(void)
628 {
629 platform_driver_unregister(&davinci_driver);
630 }
631 module_exit(davinci_exit);
632