1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
25
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
30
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
33 #include "pci-quirks.h"
34
35 /* xHCI PCI Configuration Registers */
36 #define XHCI_SBRN_OFFSET (0x60)
37
38 /* Max number of USB devices for any host controller - limit in section 6.1 */
39 #define MAX_HC_SLOTS 256
40 /* Section 5.3.3 - MaxPorts */
41 #define MAX_HC_PORTS 127
42
43 /*
44 * xHCI register interface.
45 * This corresponds to the eXtensible Host Controller Interface (xHCI)
46 * Revision 0.95 specification
47 */
48
49 /**
50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
51 * @hc_capbase: length of the capabilities register and HC version number
52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
55 * @hcc_params: HCCPARAMS - Capability Parameters
56 * @db_off: DBOFF - Doorbell array offset
57 * @run_regs_off: RTSOFF - Runtime register space offset
58 */
59 struct xhci_cap_regs {
60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
67 /* Reserved up to (CAPLENGTH - 0x1C) */
68 };
69
70 /* hc_capbase bitmasks */
71 /* bits 7:0 - how long is the Capabilities register */
72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73 /* bits 31:16 */
74 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
77 /* bits 0:7, Max Device Slots */
78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79 #define HCS_SLOTS_MASK 0xff
80 /* bits 8:18, Max Interrupters */
81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
86 /* bits 0:3, frames or uframes that SW needs to queue transactions
87 * ahead of the HW to meet periodic deadlines */
88 #define HCS_IST(p) (((p) >> 0) & 0xf)
89 /* bits 4:7, max number of Event Ring segments */
90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94
95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101 /* HCCPARAMS - hcc_params - bitmasks */
102 /* true: HC can use 64-bit address pointers */
103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104 /* true: HC can do bandwidth negotiation */
105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106 /* true: HC uses 64-byte Device Context structures
107 * FIXME 64-byte context structures aren't supported yet.
108 */
109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110 /* true: HC has port power switches */
111 #define HCC_PPC(p) ((p) & (1 << 3))
112 /* true: HC has port indicators */
113 #define HCS_INDICATOR(p) ((p) & (1 << 4))
114 /* true: HC has Light HC Reset Capability */
115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116 /* true: HC supports latency tolerance messaging */
117 #define HCC_LTC(p) ((p) & (1 << 6))
118 /* true: no secondary Stream ID Support */
119 #define HCC_NSS(p) ((p) & (1 << 7))
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125 /* db_off bitmask - bits 0:1 reserved */
126 #define DBOFF_MASK (~0x3)
127
128 /* run_regs_off bitmask - bits 0:4 reserved */
129 #define RTSOFF_MASK (~0x1f)
130
131
132 /* Number of registers per port */
133 #define NUM_PORT_REGS 4
134
135 /**
136 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
137 * @command: USBCMD - xHC command register
138 * @status: USBSTS - xHC status register
139 * @page_size: This indicates the page size that the host controller
140 * supports. If bit n is set, the HC supports a page size
141 * of 2^(n+12), up to a 128MB page size.
142 * 4K is the minimum page size.
143 * @cmd_ring: CRP - 64-bit Command Ring Pointer
144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
145 * @config_reg: CONFIG - Configure Register
146 * @port_status_base: PORTSCn - base address for Port Status and Control
147 * Each port has a Port Status and Control register,
148 * followed by a Port Power Management Status and Control
149 * register, a Port Link Info register, and a reserved
150 * register.
151 * @port_power_base: PORTPMSCn - base address for
152 * Port Power Management Status and Control
153 * @port_link_base: PORTLIn - base address for Port Link Info (current
154 * Link PM state and control) for USB 2.1 and USB 3.0
155 * devices.
156 */
157 struct xhci_op_regs {
158 __le32 command;
159 __le32 status;
160 __le32 page_size;
161 __le32 reserved1;
162 __le32 reserved2;
163 __le32 dev_notification;
164 __le64 cmd_ring;
165 /* rsvd: offset 0x20-2F */
166 __le32 reserved3[4];
167 __le64 dcbaa_ptr;
168 __le32 config_reg;
169 /* rsvd: offset 0x3C-3FF */
170 __le32 reserved4[241];
171 /* port 1 registers, which serve as a base address for other ports */
172 __le32 port_status_base;
173 __le32 port_power_base;
174 __le32 port_link_base;
175 __le32 reserved5;
176 /* registers for ports 2-255 */
177 __le32 reserved6[NUM_PORT_REGS*254];
178 };
179
180 /* USBCMD - USB command - command bitmasks */
181 /* start/stop HC execution - do not write unless HC is halted*/
182 #define CMD_RUN XHCI_CMD_RUN
183 /* Reset HC - resets internal HC state machine and all registers (except
184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
185 * The xHCI driver must reinitialize the xHC after setting this bit.
186 */
187 #define CMD_RESET (1 << 1)
188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
189 #define CMD_EIE XHCI_CMD_EIE
190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
191 #define CMD_HSEIE XHCI_CMD_HSEIE
192 /* bits 4:6 are reserved (and should be preserved on writes). */
193 /* light reset (port status stays unchanged) - reset completed when this is 0 */
194 #define CMD_LRESET (1 << 7)
195 /* host controller save/restore state. */
196 #define CMD_CSS (1 << 8)
197 #define CMD_CRS (1 << 9)
198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
199 #define CMD_EWE XHCI_CMD_EWE
200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
202 * '0' means the xHC can power it off if all ports are in the disconnect,
203 * disabled, or powered-off state.
204 */
205 #define CMD_PM_INDEX (1 << 11)
206 /* bits 12:31 are reserved (and should be preserved on writes). */
207
208 /* USBSTS - USB status - status bitmasks */
209 /* HC not running - set to 1 when run/stop bit is cleared. */
210 #define STS_HALT XHCI_STS_HALT
211 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
212 #define STS_FATAL (1 << 2)
213 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
214 #define STS_EINT (1 << 3)
215 /* port change detect */
216 #define STS_PORT (1 << 4)
217 /* bits 5:7 reserved and zeroed */
218 /* save state status - '1' means xHC is saving state */
219 #define STS_SAVE (1 << 8)
220 /* restore state status - '1' means xHC is restoring state */
221 #define STS_RESTORE (1 << 9)
222 /* true: save or restore error */
223 #define STS_SRE (1 << 10)
224 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
225 #define STS_CNR XHCI_STS_CNR
226 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
227 #define STS_HCE (1 << 12)
228 /* bits 13:31 reserved and should be preserved */
229
230 /*
231 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
232 * Generate a device notification event when the HC sees a transaction with a
233 * notification type that matches a bit set in this bit field.
234 */
235 #define DEV_NOTE_MASK (0xffff)
236 #define ENABLE_DEV_NOTE(x) (1 << (x))
237 /* Most of the device notification types should only be used for debug.
238 * SW does need to pay attention to function wake notifications.
239 */
240 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
241
242 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
243 /* bit 0 is the command ring cycle state */
244 /* stop ring operation after completion of the currently executing command */
245 #define CMD_RING_PAUSE (1 << 1)
246 /* stop ring immediately - abort the currently executing command */
247 #define CMD_RING_ABORT (1 << 2)
248 /* true: command ring is running */
249 #define CMD_RING_RUNNING (1 << 3)
250 /* bits 4:5 reserved and should be preserved */
251 /* Command Ring pointer - bit mask for the lower 32 bits. */
252 #define CMD_RING_RSVD_BITS (0x3f)
253
254 /* CONFIG - Configure Register - config_reg bitmasks */
255 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
256 #define MAX_DEVS(p) ((p) & 0xff)
257 /* bits 8:31 - reserved and should be preserved */
258
259 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
260 /* true: device connected */
261 #define PORT_CONNECT (1 << 0)
262 /* true: port enabled */
263 #define PORT_PE (1 << 1)
264 /* bit 2 reserved and zeroed */
265 /* true: port has an over-current condition */
266 #define PORT_OC (1 << 3)
267 /* true: port reset signaling asserted */
268 #define PORT_RESET (1 << 4)
269 /* Port Link State - bits 5:8
270 * A read gives the current link PM state of the port,
271 * a write with Link State Write Strobe set sets the link state.
272 */
273 #define PORT_PLS_MASK (0xf << 5)
274 #define XDEV_U0 (0x0 << 5)
275 #define XDEV_U2 (0x2 << 5)
276 #define XDEV_U3 (0x3 << 5)
277 #define XDEV_RESUME (0xf << 5)
278 /* true: port has power (see HCC_PPC) */
279 #define PORT_POWER (1 << 9)
280 /* bits 10:13 indicate device speed:
281 * 0 - undefined speed - port hasn't be initialized by a reset yet
282 * 1 - full speed
283 * 2 - low speed
284 * 3 - high speed
285 * 4 - super speed
286 * 5-15 reserved
287 */
288 #define DEV_SPEED_MASK (0xf << 10)
289 #define XDEV_FS (0x1 << 10)
290 #define XDEV_LS (0x2 << 10)
291 #define XDEV_HS (0x3 << 10)
292 #define XDEV_SS (0x4 << 10)
293 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
294 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
295 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
296 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
297 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
298 /* Bits 20:23 in the Slot Context are the speed for the device */
299 #define SLOT_SPEED_FS (XDEV_FS << 10)
300 #define SLOT_SPEED_LS (XDEV_LS << 10)
301 #define SLOT_SPEED_HS (XDEV_HS << 10)
302 #define SLOT_SPEED_SS (XDEV_SS << 10)
303 /* Port Indicator Control */
304 #define PORT_LED_OFF (0 << 14)
305 #define PORT_LED_AMBER (1 << 14)
306 #define PORT_LED_GREEN (2 << 14)
307 #define PORT_LED_MASK (3 << 14)
308 /* Port Link State Write Strobe - set this when changing link state */
309 #define PORT_LINK_STROBE (1 << 16)
310 /* true: connect status change */
311 #define PORT_CSC (1 << 17)
312 /* true: port enable change */
313 #define PORT_PEC (1 << 18)
314 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
315 * into an enabled state, and the device into the default state. A "warm" reset
316 * also resets the link, forcing the device through the link training sequence.
317 * SW can also look at the Port Reset register to see when warm reset is done.
318 */
319 #define PORT_WRC (1 << 19)
320 /* true: over-current change */
321 #define PORT_OCC (1 << 20)
322 /* true: reset change - 1 to 0 transition of PORT_RESET */
323 #define PORT_RC (1 << 21)
324 /* port link status change - set on some port link state transitions:
325 * Transition Reason
326 * ------------------------------------------------------------------------------
327 * - U3 to Resume Wakeup signaling from a device
328 * - Resume to Recovery to U0 USB 3.0 device resume
329 * - Resume to U0 USB 2.0 device resume
330 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
331 * - U3 to U0 Software resume of USB 2.0 device complete
332 * - U2 to U0 L1 resume of USB 2.1 device complete
333 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
334 * - U0 to disabled L1 entry error with USB 2.1 device
335 * - Any state to inactive Error on USB 3.0 port
336 */
337 #define PORT_PLC (1 << 22)
338 /* port configure error change - port failed to configure its link partner */
339 #define PORT_CEC (1 << 23)
340 /* bit 24 reserved */
341 /* wake on connect (enable) */
342 #define PORT_WKCONN_E (1 << 25)
343 /* wake on disconnect (enable) */
344 #define PORT_WKDISC_E (1 << 26)
345 /* wake on over-current (enable) */
346 #define PORT_WKOC_E (1 << 27)
347 /* bits 28:29 reserved */
348 /* true: device is removable - for USB 3.0 roothub emulation */
349 #define PORT_DEV_REMOVE (1 << 30)
350 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
351 #define PORT_WR (1 << 31)
352
353 /* We mark duplicate entries with -1 */
354 #define DUPLICATE_ENTRY ((u8)(-1))
355
356 /* Port Power Management Status and Control - port_power_base bitmasks */
357 /* Inactivity timer value for transitions into U1, in microseconds.
358 * Timeout can be up to 127us. 0xFF means an infinite timeout.
359 */
360 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
361 /* Inactivity timer value for transitions into U2 */
362 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
363 /* Bits 24:31 for port testing */
364
365 /* USB2 Protocol PORTSPMSC */
366 #define PORT_L1S_MASK 7
367 #define PORT_L1S_SUCCESS 1
368 #define PORT_RWE (1 << 3)
369 #define PORT_HIRD(p) (((p) & 0xf) << 4)
370 #define PORT_HIRD_MASK (0xf << 4)
371 #define PORT_L1DS(p) (((p) & 0xff) << 8)
372 #define PORT_HLE (1 << 16)
373
374 /**
375 * struct xhci_intr_reg - Interrupt Register Set
376 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
377 * interrupts and check for pending interrupts.
378 * @irq_control: IMOD - Interrupt Moderation Register.
379 * Used to throttle interrupts.
380 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
381 * @erst_base: ERST base address.
382 * @erst_dequeue: Event ring dequeue pointer.
383 *
384 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
385 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
386 * multiple segments of the same size. The HC places events on the ring and
387 * "updates the Cycle bit in the TRBs to indicate to software the current
388 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
389 * updates the dequeue pointer.
390 */
391 struct xhci_intr_reg {
392 __le32 irq_pending;
393 __le32 irq_control;
394 __le32 erst_size;
395 __le32 rsvd;
396 __le64 erst_base;
397 __le64 erst_dequeue;
398 };
399
400 /* irq_pending bitmasks */
401 #define ER_IRQ_PENDING(p) ((p) & 0x1)
402 /* bits 2:31 need to be preserved */
403 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
404 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
405 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
406 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
407
408 /* irq_control bitmasks */
409 /* Minimum interval between interrupts (in 250ns intervals). The interval
410 * between interrupts will be longer if there are no events on the event ring.
411 * Default is 4000 (1 ms).
412 */
413 #define ER_IRQ_INTERVAL_MASK (0xffff)
414 /* Counter used to count down the time to the next interrupt - HW use only */
415 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
416
417 /* erst_size bitmasks */
418 /* Preserve bits 16:31 of erst_size */
419 #define ERST_SIZE_MASK (0xffff << 16)
420
421 /* erst_dequeue bitmasks */
422 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
423 * where the current dequeue pointer lies. This is an optional HW hint.
424 */
425 #define ERST_DESI_MASK (0x7)
426 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
427 * a work queue (or delayed service routine)?
428 */
429 #define ERST_EHB (1 << 3)
430 #define ERST_PTR_MASK (0xf)
431
432 /**
433 * struct xhci_run_regs
434 * @microframe_index:
435 * MFINDEX - current microframe number
436 *
437 * Section 5.5 Host Controller Runtime Registers:
438 * "Software should read and write these registers using only Dword (32 bit)
439 * or larger accesses"
440 */
441 struct xhci_run_regs {
442 __le32 microframe_index;
443 __le32 rsvd[7];
444 struct xhci_intr_reg ir_set[128];
445 };
446
447 /**
448 * struct doorbell_array
449 *
450 * Bits 0 - 7: Endpoint target
451 * Bits 8 - 15: RsvdZ
452 * Bits 16 - 31: Stream ID
453 *
454 * Section 5.6
455 */
456 struct xhci_doorbell_array {
457 __le32 doorbell[256];
458 };
459
460 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
461 #define DB_VALUE_HOST 0x00000000
462
463 /**
464 * struct xhci_protocol_caps
465 * @revision: major revision, minor revision, capability ID,
466 * and next capability pointer.
467 * @name_string: Four ASCII characters to say which spec this xHC
468 * follows, typically "USB ".
469 * @port_info: Port offset, count, and protocol-defined information.
470 */
471 struct xhci_protocol_caps {
472 u32 revision;
473 u32 name_string;
474 u32 port_info;
475 };
476
477 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
478 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
479 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
480
481 /**
482 * struct xhci_container_ctx
483 * @type: Type of context. Used to calculated offsets to contained contexts.
484 * @size: Size of the context data
485 * @bytes: The raw context data given to HW
486 * @dma: dma address of the bytes
487 *
488 * Represents either a Device or Input context. Holds a pointer to the raw
489 * memory used for the context (bytes) and dma address of it (dma).
490 */
491 struct xhci_container_ctx {
492 unsigned type;
493 #define XHCI_CTX_TYPE_DEVICE 0x1
494 #define XHCI_CTX_TYPE_INPUT 0x2
495
496 int size;
497
498 u8 *bytes;
499 dma_addr_t dma;
500 };
501
502 /**
503 * struct xhci_slot_ctx
504 * @dev_info: Route string, device speed, hub info, and last valid endpoint
505 * @dev_info2: Max exit latency for device number, root hub port number
506 * @tt_info: tt_info is used to construct split transaction tokens
507 * @dev_state: slot state and device address
508 *
509 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
510 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
511 * reserved at the end of the slot context for HC internal use.
512 */
513 struct xhci_slot_ctx {
514 __le32 dev_info;
515 __le32 dev_info2;
516 __le32 tt_info;
517 __le32 dev_state;
518 /* offset 0x10 to 0x1f reserved for HC internal use */
519 __le32 reserved[4];
520 };
521
522 /* dev_info bitmasks */
523 /* Route String - 0:19 */
524 #define ROUTE_STRING_MASK (0xfffff)
525 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
526 #define DEV_SPEED (0xf << 20)
527 /* bit 24 reserved */
528 /* Is this LS/FS device connected through a HS hub? - bit 25 */
529 #define DEV_MTT (0x1 << 25)
530 /* Set if the device is a hub - bit 26 */
531 #define DEV_HUB (0x1 << 26)
532 /* Index of the last valid endpoint context in this device context - 27:31 */
533 #define LAST_CTX_MASK (0x1f << 27)
534 #define LAST_CTX(p) ((p) << 27)
535 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
536 #define SLOT_FLAG (1 << 0)
537 #define EP0_FLAG (1 << 1)
538
539 /* dev_info2 bitmasks */
540 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
541 #define MAX_EXIT (0xffff)
542 /* Root hub port number that is needed to access the USB device */
543 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
544 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
545 /* Maximum number of ports under a hub device */
546 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
547
548 /* tt_info bitmasks */
549 /*
550 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
551 * The Slot ID of the hub that isolates the high speed signaling from
552 * this low or full-speed device. '0' if attached to root hub port.
553 */
554 #define TT_SLOT (0xff)
555 /*
556 * The number of the downstream facing port of the high-speed hub
557 * '0' if the device is not low or full speed.
558 */
559 #define TT_PORT (0xff << 8)
560 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
561
562 /* dev_state bitmasks */
563 /* USB device address - assigned by the HC */
564 #define DEV_ADDR_MASK (0xff)
565 /* bits 8:26 reserved */
566 /* Slot state */
567 #define SLOT_STATE (0x1f << 27)
568 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
569
570 #define SLOT_STATE_DISABLED 0
571 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
572 #define SLOT_STATE_DEFAULT 1
573 #define SLOT_STATE_ADDRESSED 2
574 #define SLOT_STATE_CONFIGURED 3
575
576 /**
577 * struct xhci_ep_ctx
578 * @ep_info: endpoint state, streams, mult, and interval information.
579 * @ep_info2: information on endpoint type, max packet size, max burst size,
580 * error count, and whether the HC will force an event for all
581 * transactions.
582 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
583 * defines one stream, this points to the endpoint transfer ring.
584 * Otherwise, it points to a stream context array, which has a
585 * ring pointer for each flow.
586 * @tx_info:
587 * Average TRB lengths for the endpoint ring and
588 * max payload within an Endpoint Service Interval Time (ESIT).
589 *
590 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
591 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
592 * reserved at the end of the endpoint context for HC internal use.
593 */
594 struct xhci_ep_ctx {
595 __le32 ep_info;
596 __le32 ep_info2;
597 __le64 deq;
598 __le32 tx_info;
599 /* offset 0x14 - 0x1f reserved for HC internal use */
600 __le32 reserved[3];
601 };
602
603 /* ep_info bitmasks */
604 /*
605 * Endpoint State - bits 0:2
606 * 0 - disabled
607 * 1 - running
608 * 2 - halted due to halt condition - ok to manipulate endpoint ring
609 * 3 - stopped
610 * 4 - TRB error
611 * 5-7 - reserved
612 */
613 #define EP_STATE_MASK (0xf)
614 #define EP_STATE_DISABLED 0
615 #define EP_STATE_RUNNING 1
616 #define EP_STATE_HALTED 2
617 #define EP_STATE_STOPPED 3
618 #define EP_STATE_ERROR 4
619 /* Mult - Max number of burtst within an interval, in EP companion desc. */
620 #define EP_MULT(p) (((p) & 0x3) << 8)
621 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
622 /* bits 10:14 are Max Primary Streams */
623 /* bit 15 is Linear Stream Array */
624 /* Interval - period between requests to an endpoint - 125u increments. */
625 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
626 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
627 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
628 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
629 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
630 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
631 #define EP_HAS_LSA (1 << 15)
632
633 /* ep_info2 bitmasks */
634 /*
635 * Force Event - generate transfer events for all TRBs for this endpoint
636 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
637 */
638 #define FORCE_EVENT (0x1)
639 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
640 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
641 #define EP_TYPE(p) ((p) << 3)
642 #define ISOC_OUT_EP 1
643 #define BULK_OUT_EP 2
644 #define INT_OUT_EP 3
645 #define CTRL_EP 4
646 #define ISOC_IN_EP 5
647 #define BULK_IN_EP 6
648 #define INT_IN_EP 7
649 /* bit 6 reserved */
650 /* bit 7 is Host Initiate Disable - for disabling stream selection */
651 #define MAX_BURST(p) (((p)&0xff) << 8)
652 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
653 #define MAX_PACKET(p) (((p)&0xffff) << 16)
654 #define MAX_PACKET_MASK (0xffff << 16)
655 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
656
657 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
658 * USB2.0 spec 9.6.6.
659 */
660 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
661
662 /* tx_info bitmasks */
663 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
664 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
665 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
666
667 /* deq bitmasks */
668 #define EP_CTX_CYCLE_MASK (1 << 0)
669
670
671 /**
672 * struct xhci_input_control_context
673 * Input control context; see section 6.2.5.
674 *
675 * @drop_context: set the bit of the endpoint context you want to disable
676 * @add_context: set the bit of the endpoint context you want to enable
677 */
678 struct xhci_input_control_ctx {
679 __le32 drop_flags;
680 __le32 add_flags;
681 __le32 rsvd2[6];
682 };
683
684 #define EP_IS_ADDED(ctrl_ctx, i) \
685 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
686 #define EP_IS_DROPPED(ctrl_ctx, i) \
687 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
688
689 /* Represents everything that is needed to issue a command on the command ring.
690 * It's useful to pre-allocate these for commands that cannot fail due to
691 * out-of-memory errors, like freeing streams.
692 */
693 struct xhci_command {
694 /* Input context for changing device state */
695 struct xhci_container_ctx *in_ctx;
696 u32 status;
697 /* If completion is null, no one is waiting on this command
698 * and the structure can be freed after the command completes.
699 */
700 struct completion *completion;
701 union xhci_trb *command_trb;
702 struct list_head cmd_list;
703 };
704
705 /* drop context bitmasks */
706 #define DROP_EP(x) (0x1 << x)
707 /* add context bitmasks */
708 #define ADD_EP(x) (0x1 << x)
709
710 struct xhci_stream_ctx {
711 /* 64-bit stream ring address, cycle state, and stream type */
712 __le64 stream_ring;
713 /* offset 0x14 - 0x1f reserved for HC internal use */
714 __le32 reserved[2];
715 };
716
717 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
718 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
719 /* Secondary stream array type, dequeue pointer is to a transfer ring */
720 #define SCT_SEC_TR 0
721 /* Primary stream array type, dequeue pointer is to a transfer ring */
722 #define SCT_PRI_TR 1
723 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
724 #define SCT_SSA_8 2
725 #define SCT_SSA_16 3
726 #define SCT_SSA_32 4
727 #define SCT_SSA_64 5
728 #define SCT_SSA_128 6
729 #define SCT_SSA_256 7
730
731 /* Assume no secondary streams for now */
732 struct xhci_stream_info {
733 struct xhci_ring **stream_rings;
734 /* Number of streams, including stream 0 (which drivers can't use) */
735 unsigned int num_streams;
736 /* The stream context array may be bigger than
737 * the number of streams the driver asked for
738 */
739 struct xhci_stream_ctx *stream_ctx_array;
740 unsigned int num_stream_ctxs;
741 dma_addr_t ctx_array_dma;
742 /* For mapping physical TRB addresses to segments in stream rings */
743 struct radix_tree_root trb_address_map;
744 struct xhci_command *free_streams_command;
745 };
746
747 #define SMALL_STREAM_ARRAY_SIZE 256
748 #define MEDIUM_STREAM_ARRAY_SIZE 1024
749
750 /* Some Intel xHCI host controllers need software to keep track of the bus
751 * bandwidth. Keep track of endpoint info here. Each root port is allocated
752 * the full bus bandwidth. We must also treat TTs (including each port under a
753 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
754 * (DMI) also limits the total bandwidth (across all domains) that can be used.
755 */
756 struct xhci_bw_info {
757 /* ep_interval is zero-based */
758 unsigned int ep_interval;
759 /* mult and num_packets are one-based */
760 unsigned int mult;
761 unsigned int num_packets;
762 unsigned int max_packet_size;
763 unsigned int max_esit_payload;
764 unsigned int type;
765 };
766
767 /* "Block" sizes in bytes the hardware uses for different device speeds.
768 * The logic in this part of the hardware limits the number of bits the hardware
769 * can use, so must represent bandwidth in a less precise manner to mimic what
770 * the scheduler hardware computes.
771 */
772 #define FS_BLOCK 1
773 #define HS_BLOCK 4
774 #define SS_BLOCK 16
775 #define DMI_BLOCK 32
776
777 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
778 * with each byte transferred. SuperSpeed devices have an initial overhead to
779 * set up bursts. These are in blocks, see above. LS overhead has already been
780 * translated into FS blocks.
781 */
782 #define DMI_OVERHEAD 8
783 #define DMI_OVERHEAD_BURST 4
784 #define SS_OVERHEAD 8
785 #define SS_OVERHEAD_BURST 32
786 #define HS_OVERHEAD 26
787 #define FS_OVERHEAD 20
788 #define LS_OVERHEAD 128
789 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
790 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
791 * of overhead associated with split transfers crossing microframe boundaries.
792 * 31 blocks is pure protocol overhead.
793 */
794 #define TT_HS_OVERHEAD (31 + 94)
795 #define TT_DMI_OVERHEAD (25 + 12)
796
797 /* Bandwidth limits in blocks */
798 #define FS_BW_LIMIT 1285
799 #define TT_BW_LIMIT 1320
800 #define HS_BW_LIMIT 1607
801 #define SS_BW_LIMIT_IN 3906
802 #define DMI_BW_LIMIT_IN 3906
803 #define SS_BW_LIMIT_OUT 3906
804 #define DMI_BW_LIMIT_OUT 3906
805
806 /* Percentage of bus bandwidth reserved for non-periodic transfers */
807 #define FS_BW_RESERVED 10
808 #define HS_BW_RESERVED 20
809 #define SS_BW_RESERVED 10
810
811 struct xhci_virt_ep {
812 struct xhci_ring *ring;
813 /* Related to endpoints that are configured to use stream IDs only */
814 struct xhci_stream_info *stream_info;
815 /* Temporary storage in case the configure endpoint command fails and we
816 * have to restore the device state to the previous state
817 */
818 struct xhci_ring *new_ring;
819 unsigned int ep_state;
820 #define SET_DEQ_PENDING (1 << 0)
821 #define EP_HALTED (1 << 1) /* For stall handling */
822 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
823 /* Transitioning the endpoint to using streams, don't enqueue URBs */
824 #define EP_GETTING_STREAMS (1 << 3)
825 #define EP_HAS_STREAMS (1 << 4)
826 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
827 #define EP_GETTING_NO_STREAMS (1 << 5)
828 /* ---- Related to URB cancellation ---- */
829 struct list_head cancelled_td_list;
830 /* The TRB that was last reported in a stopped endpoint ring */
831 union xhci_trb *stopped_trb;
832 struct xhci_td *stopped_td;
833 unsigned int stopped_stream;
834 /* Watchdog timer for stop endpoint command to cancel URBs */
835 struct timer_list stop_cmd_timer;
836 int stop_cmds_pending;
837 struct xhci_hcd *xhci;
838 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
839 * command. We'll need to update the ring's dequeue segment and dequeue
840 * pointer after the command completes.
841 */
842 struct xhci_segment *queued_deq_seg;
843 union xhci_trb *queued_deq_ptr;
844 /*
845 * Sometimes the xHC can not process isochronous endpoint ring quickly
846 * enough, and it will miss some isoc tds on the ring and generate
847 * a Missed Service Error Event.
848 * Set skip flag when receive a Missed Service Error Event and
849 * process the missed tds on the endpoint ring.
850 */
851 bool skip;
852 /* Bandwidth checking storage */
853 struct xhci_bw_info bw_info;
854 struct list_head bw_endpoint_list;
855 };
856
857 enum xhci_overhead_type {
858 LS_OVERHEAD_TYPE = 0,
859 FS_OVERHEAD_TYPE,
860 HS_OVERHEAD_TYPE,
861 };
862
863 struct xhci_interval_bw {
864 unsigned int num_packets;
865 /* Sorted by max packet size.
866 * Head of the list is the greatest max packet size.
867 */
868 struct list_head endpoints;
869 /* How many endpoints of each speed are present. */
870 unsigned int overhead[3];
871 };
872
873 #define XHCI_MAX_INTERVAL 16
874
875 struct xhci_interval_bw_table {
876 unsigned int interval0_esit_payload;
877 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
878 /* Includes reserved bandwidth for async endpoints */
879 unsigned int bw_used;
880 unsigned int ss_bw_in;
881 unsigned int ss_bw_out;
882 };
883
884
885 struct xhci_virt_device {
886 struct usb_device *udev;
887 /*
888 * Commands to the hardware are passed an "input context" that
889 * tells the hardware what to change in its data structures.
890 * The hardware will return changes in an "output context" that
891 * software must allocate for the hardware. We need to keep
892 * track of input and output contexts separately because
893 * these commands might fail and we don't trust the hardware.
894 */
895 struct xhci_container_ctx *out_ctx;
896 /* Used for addressing devices and configuration changes */
897 struct xhci_container_ctx *in_ctx;
898 /* Rings saved to ensure old alt settings can be re-instated */
899 struct xhci_ring **ring_cache;
900 int num_rings_cached;
901 /* Store xHC assigned device address */
902 int address;
903 #define XHCI_MAX_RINGS_CACHED 31
904 struct xhci_virt_ep eps[31];
905 struct completion cmd_completion;
906 /* Status of the last command issued for this device */
907 u32 cmd_status;
908 struct list_head cmd_list;
909 u8 fake_port;
910 u8 real_port;
911 struct xhci_interval_bw_table *bw_table;
912 struct xhci_tt_bw_info *tt_info;
913 };
914
915 /*
916 * For each roothub, keep track of the bandwidth information for each periodic
917 * interval.
918 *
919 * If a high speed hub is attached to the roothub, each TT associated with that
920 * hub is a separate bandwidth domain. The interval information for the
921 * endpoints on the devices under that TT will appear in the TT structure.
922 */
923 struct xhci_root_port_bw_info {
924 struct list_head tts;
925 unsigned int num_active_tts;
926 struct xhci_interval_bw_table bw_table;
927 };
928
929 struct xhci_tt_bw_info {
930 struct list_head tt_list;
931 int slot_id;
932 int ttport;
933 struct xhci_interval_bw_table bw_table;
934 int active_eps;
935 };
936
937
938 /**
939 * struct xhci_device_context_array
940 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
941 */
942 struct xhci_device_context_array {
943 /* 64-bit device addresses; we only write 32-bit addresses */
944 __le64 dev_context_ptrs[MAX_HC_SLOTS];
945 /* private xHCD pointers */
946 dma_addr_t dma;
947 };
948 /* TODO: write function to set the 64-bit device DMA address */
949 /*
950 * TODO: change this to be dynamically sized at HC mem init time since the HC
951 * might not be able to handle the maximum number of devices possible.
952 */
953
954
955 struct xhci_transfer_event {
956 /* 64-bit buffer address, or immediate data */
957 __le64 buffer;
958 __le32 transfer_len;
959 /* This field is interpreted differently based on the type of TRB */
960 __le32 flags;
961 };
962
963 /** Transfer Event bit fields **/
964 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
965
966 /* Completion Code - only applicable for some types of TRBs */
967 #define COMP_CODE_MASK (0xff << 24)
968 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
969 #define COMP_SUCCESS 1
970 /* Data Buffer Error */
971 #define COMP_DB_ERR 2
972 /* Babble Detected Error */
973 #define COMP_BABBLE 3
974 /* USB Transaction Error */
975 #define COMP_TX_ERR 4
976 /* TRB Error - some TRB field is invalid */
977 #define COMP_TRB_ERR 5
978 /* Stall Error - USB device is stalled */
979 #define COMP_STALL 6
980 /* Resource Error - HC doesn't have memory for that device configuration */
981 #define COMP_ENOMEM 7
982 /* Bandwidth Error - not enough room in schedule for this dev config */
983 #define COMP_BW_ERR 8
984 /* No Slots Available Error - HC ran out of device slots */
985 #define COMP_ENOSLOTS 9
986 /* Invalid Stream Type Error */
987 #define COMP_STREAM_ERR 10
988 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
989 #define COMP_EBADSLT 11
990 /* Endpoint Not Enabled Error */
991 #define COMP_EBADEP 12
992 /* Short Packet */
993 #define COMP_SHORT_TX 13
994 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
995 #define COMP_UNDERRUN 14
996 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
997 #define COMP_OVERRUN 15
998 /* Virtual Function Event Ring Full Error */
999 #define COMP_VF_FULL 16
1000 /* Parameter Error - Context parameter is invalid */
1001 #define COMP_EINVAL 17
1002 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1003 #define COMP_BW_OVER 18
1004 /* Context State Error - illegal context state transition requested */
1005 #define COMP_CTX_STATE 19
1006 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1007 #define COMP_PING_ERR 20
1008 /* Event Ring is full */
1009 #define COMP_ER_FULL 21
1010 /* Incompatible Device Error */
1011 #define COMP_DEV_ERR 22
1012 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1013 #define COMP_MISSED_INT 23
1014 /* Successfully stopped command ring */
1015 #define COMP_CMD_STOP 24
1016 /* Successfully aborted current command and stopped command ring */
1017 #define COMP_CMD_ABORT 25
1018 /* Stopped - transfer was terminated by a stop endpoint command */
1019 #define COMP_STOP 26
1020 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1021 #define COMP_STOP_INVAL 27
1022 /* Control Abort Error - Debug Capability - control pipe aborted */
1023 #define COMP_DBG_ABORT 28
1024 /* Max Exit Latency Too Large Error */
1025 #define COMP_MEL_ERR 29
1026 /* TRB type 30 reserved */
1027 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1028 #define COMP_BUFF_OVER 31
1029 /* Event Lost Error - xHC has an "internal event overrun condition" */
1030 #define COMP_ISSUES 32
1031 /* Undefined Error - reported when other error codes don't apply */
1032 #define COMP_UNKNOWN 33
1033 /* Invalid Stream ID Error */
1034 #define COMP_STRID_ERR 34
1035 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1036 #define COMP_2ND_BW_ERR 35
1037 /* Split Transaction Error */
1038 #define COMP_SPLIT_ERR 36
1039
1040 struct xhci_link_trb {
1041 /* 64-bit segment pointer*/
1042 __le64 segment_ptr;
1043 __le32 intr_target;
1044 __le32 control;
1045 };
1046
1047 /* control bitfields */
1048 #define LINK_TOGGLE (0x1<<1)
1049
1050 /* Command completion event TRB */
1051 struct xhci_event_cmd {
1052 /* Pointer to command TRB, or the value passed by the event data trb */
1053 __le64 cmd_trb;
1054 __le32 status;
1055 __le32 flags;
1056 };
1057
1058 /* flags bitmasks */
1059 /* bits 16:23 are the virtual function ID */
1060 /* bits 24:31 are the slot ID */
1061 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1062 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1063
1064 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1065 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1066 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1067
1068 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1069 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1070 #define LAST_EP_INDEX 30
1071
1072 /* Set TR Dequeue Pointer command TRB fields */
1073 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1074 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1075
1076
1077 /* Port Status Change Event TRB fields */
1078 /* Port ID - bits 31:24 */
1079 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1080
1081 /* Normal TRB fields */
1082 /* transfer_len bitmasks - bits 0:16 */
1083 #define TRB_LEN(p) ((p) & 0x1ffff)
1084 /* Interrupter Target - which MSI-X vector to target the completion event at */
1085 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1086 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1087 #define TRB_TBC(p) (((p) & 0x3) << 7)
1088 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1089
1090 /* Cycle bit - indicates TRB ownership by HC or HCD */
1091 #define TRB_CYCLE (1<<0)
1092 /*
1093 * Force next event data TRB to be evaluated before task switch.
1094 * Used to pass OS data back after a TD completes.
1095 */
1096 #define TRB_ENT (1<<1)
1097 /* Interrupt on short packet */
1098 #define TRB_ISP (1<<2)
1099 /* Set PCIe no snoop attribute */
1100 #define TRB_NO_SNOOP (1<<3)
1101 /* Chain multiple TRBs into a TD */
1102 #define TRB_CHAIN (1<<4)
1103 /* Interrupt on completion */
1104 #define TRB_IOC (1<<5)
1105 /* The buffer pointer contains immediate data */
1106 #define TRB_IDT (1<<6)
1107
1108 /* Block Event Interrupt */
1109 #define TRB_BEI (1<<9)
1110
1111 /* Control transfer TRB specific fields */
1112 #define TRB_DIR_IN (1<<16)
1113 #define TRB_TX_TYPE(p) ((p) << 16)
1114 #define TRB_DATA_OUT 2
1115 #define TRB_DATA_IN 3
1116
1117 /* Isochronous TRB specific fields */
1118 #define TRB_SIA (1<<31)
1119
1120 struct xhci_generic_trb {
1121 __le32 field[4];
1122 };
1123
1124 union xhci_trb {
1125 struct xhci_link_trb link;
1126 struct xhci_transfer_event trans_event;
1127 struct xhci_event_cmd event_cmd;
1128 struct xhci_generic_trb generic;
1129 };
1130
1131 /* TRB bit mask */
1132 #define TRB_TYPE_BITMASK (0xfc00)
1133 #define TRB_TYPE(p) ((p) << 10)
1134 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1135 /* TRB type IDs */
1136 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1137 #define TRB_NORMAL 1
1138 /* setup stage for control transfers */
1139 #define TRB_SETUP 2
1140 /* data stage for control transfers */
1141 #define TRB_DATA 3
1142 /* status stage for control transfers */
1143 #define TRB_STATUS 4
1144 /* isoc transfers */
1145 #define TRB_ISOC 5
1146 /* TRB for linking ring segments */
1147 #define TRB_LINK 6
1148 #define TRB_EVENT_DATA 7
1149 /* Transfer Ring No-op (not for the command ring) */
1150 #define TRB_TR_NOOP 8
1151 /* Command TRBs */
1152 /* Enable Slot Command */
1153 #define TRB_ENABLE_SLOT 9
1154 /* Disable Slot Command */
1155 #define TRB_DISABLE_SLOT 10
1156 /* Address Device Command */
1157 #define TRB_ADDR_DEV 11
1158 /* Configure Endpoint Command */
1159 #define TRB_CONFIG_EP 12
1160 /* Evaluate Context Command */
1161 #define TRB_EVAL_CONTEXT 13
1162 /* Reset Endpoint Command */
1163 #define TRB_RESET_EP 14
1164 /* Stop Transfer Ring Command */
1165 #define TRB_STOP_RING 15
1166 /* Set Transfer Ring Dequeue Pointer Command */
1167 #define TRB_SET_DEQ 16
1168 /* Reset Device Command */
1169 #define TRB_RESET_DEV 17
1170 /* Force Event Command (opt) */
1171 #define TRB_FORCE_EVENT 18
1172 /* Negotiate Bandwidth Command (opt) */
1173 #define TRB_NEG_BANDWIDTH 19
1174 /* Set Latency Tolerance Value Command (opt) */
1175 #define TRB_SET_LT 20
1176 /* Get port bandwidth Command */
1177 #define TRB_GET_BW 21
1178 /* Force Header Command - generate a transaction or link management packet */
1179 #define TRB_FORCE_HEADER 22
1180 /* No-op Command - not for transfer rings */
1181 #define TRB_CMD_NOOP 23
1182 /* TRB IDs 24-31 reserved */
1183 /* Event TRBS */
1184 /* Transfer Event */
1185 #define TRB_TRANSFER 32
1186 /* Command Completion Event */
1187 #define TRB_COMPLETION 33
1188 /* Port Status Change Event */
1189 #define TRB_PORT_STATUS 34
1190 /* Bandwidth Request Event (opt) */
1191 #define TRB_BANDWIDTH_EVENT 35
1192 /* Doorbell Event (opt) */
1193 #define TRB_DOORBELL 36
1194 /* Host Controller Event */
1195 #define TRB_HC_EVENT 37
1196 /* Device Notification Event - device sent function wake notification */
1197 #define TRB_DEV_NOTE 38
1198 /* MFINDEX Wrap Event - microframe counter wrapped */
1199 #define TRB_MFINDEX_WRAP 39
1200 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1201
1202 /* Nec vendor-specific command completion event. */
1203 #define TRB_NEC_CMD_COMP 48
1204 /* Get NEC firmware revision. */
1205 #define TRB_NEC_GET_FW 49
1206
1207 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1208 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1209 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1210 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1211 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1212 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1213
1214 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1215 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1216
1217 /*
1218 * TRBS_PER_SEGMENT must be a multiple of 4,
1219 * since the command ring is 64-byte aligned.
1220 * It must also be greater than 16.
1221 */
1222 #define TRBS_PER_SEGMENT 64
1223 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1224 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1225 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1226 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1227 * Change this if you change TRBS_PER_SEGMENT!
1228 */
1229 #define SEGMENT_SHIFT 10
1230 /* TRB buffer pointers can't cross 64KB boundaries */
1231 #define TRB_MAX_BUFF_SHIFT 16
1232 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1233
1234 struct xhci_segment {
1235 union xhci_trb *trbs;
1236 /* private to HCD */
1237 struct xhci_segment *next;
1238 dma_addr_t dma;
1239 };
1240
1241 struct xhci_td {
1242 struct list_head td_list;
1243 struct list_head cancelled_td_list;
1244 struct urb *urb;
1245 struct xhci_segment *start_seg;
1246 union xhci_trb *first_trb;
1247 union xhci_trb *last_trb;
1248 };
1249
1250 struct xhci_dequeue_state {
1251 struct xhci_segment *new_deq_seg;
1252 union xhci_trb *new_deq_ptr;
1253 int new_cycle_state;
1254 };
1255
1256 struct xhci_ring {
1257 struct xhci_segment *first_seg;
1258 union xhci_trb *enqueue;
1259 struct xhci_segment *enq_seg;
1260 unsigned int enq_updates;
1261 union xhci_trb *dequeue;
1262 struct xhci_segment *deq_seg;
1263 unsigned int deq_updates;
1264 struct list_head td_list;
1265 /*
1266 * Write the cycle state into the TRB cycle field to give ownership of
1267 * the TRB to the host controller (if we are the producer), or to check
1268 * if we own the TRB (if we are the consumer). See section 4.9.1.
1269 */
1270 u32 cycle_state;
1271 unsigned int stream_id;
1272 bool last_td_was_short;
1273 };
1274
1275 struct xhci_erst_entry {
1276 /* 64-bit event ring segment address */
1277 __le64 seg_addr;
1278 __le32 seg_size;
1279 /* Set to zero */
1280 __le32 rsvd;
1281 };
1282
1283 struct xhci_erst {
1284 struct xhci_erst_entry *entries;
1285 unsigned int num_entries;
1286 /* xhci->event_ring keeps track of segment dma addresses */
1287 dma_addr_t erst_dma_addr;
1288 /* Num entries the ERST can contain */
1289 unsigned int erst_size;
1290 };
1291
1292 struct xhci_scratchpad {
1293 u64 *sp_array;
1294 dma_addr_t sp_dma;
1295 void **sp_buffers;
1296 dma_addr_t *sp_dma_buffers;
1297 };
1298
1299 struct urb_priv {
1300 int length;
1301 int td_cnt;
1302 struct xhci_td *td[0];
1303 };
1304
1305 /*
1306 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1307 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1308 * meaning 64 ring segments.
1309 * Initial allocated size of the ERST, in number of entries */
1310 #define ERST_NUM_SEGS 1
1311 /* Initial allocated size of the ERST, in number of entries */
1312 #define ERST_SIZE 64
1313 /* Initial number of event segment rings allocated */
1314 #define ERST_ENTRIES 1
1315 /* Poll every 60 seconds */
1316 #define POLL_TIMEOUT 60
1317 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1318 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1319 /* XXX: Make these module parameters */
1320
1321 struct s3_save {
1322 u32 command;
1323 u32 dev_nt;
1324 u64 dcbaa_ptr;
1325 u32 config_reg;
1326 u32 irq_pending;
1327 u32 irq_control;
1328 u32 erst_size;
1329 u64 erst_base;
1330 u64 erst_dequeue;
1331 };
1332
1333 /* Use for lpm */
1334 struct dev_info {
1335 u32 dev_id;
1336 struct list_head list;
1337 };
1338
1339 struct xhci_bus_state {
1340 unsigned long bus_suspended;
1341 unsigned long next_statechange;
1342
1343 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1344 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1345 u32 port_c_suspend;
1346 u32 suspended_ports;
1347 unsigned long resume_done[USB_MAXCHILDREN];
1348 };
1349
hcd_index(struct usb_hcd * hcd)1350 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1351 {
1352 if (hcd->speed == HCD_USB3)
1353 return 0;
1354 else
1355 return 1;
1356 }
1357
1358 /* There is one xhci_hcd structure per controller */
1359 struct xhci_hcd {
1360 struct usb_hcd *main_hcd;
1361 struct usb_hcd *shared_hcd;
1362 /* glue to PCI and HCD framework */
1363 struct xhci_cap_regs __iomem *cap_regs;
1364 struct xhci_op_regs __iomem *op_regs;
1365 struct xhci_run_regs __iomem *run_regs;
1366 struct xhci_doorbell_array __iomem *dba;
1367 /* Our HCD's current interrupter register set */
1368 struct xhci_intr_reg __iomem *ir_set;
1369
1370 /* Cached register copies of read-only HC data */
1371 __u32 hcs_params1;
1372 __u32 hcs_params2;
1373 __u32 hcs_params3;
1374 __u32 hcc_params;
1375
1376 spinlock_t lock;
1377
1378 /* packed release number */
1379 u8 sbrn;
1380 u16 hci_version;
1381 u8 max_slots;
1382 u8 max_interrupters;
1383 u8 max_ports;
1384 u8 isoc_threshold;
1385 int event_ring_max;
1386 int addr_64;
1387 /* 4KB min, 128MB max */
1388 int page_size;
1389 /* Valid values are 12 to 20, inclusive */
1390 int page_shift;
1391 /* msi-x vectors */
1392 int msix_count;
1393 struct msix_entry *msix_entries;
1394 /* data structures */
1395 struct xhci_device_context_array *dcbaa;
1396 struct xhci_ring *cmd_ring;
1397 unsigned int cmd_ring_reserved_trbs;
1398 struct xhci_ring *event_ring;
1399 struct xhci_erst erst;
1400 /* Scratchpad */
1401 struct xhci_scratchpad *scratchpad;
1402 /* Store LPM test failed devices' information */
1403 struct list_head lpm_failed_devs;
1404
1405 /* slot enabling and address device helpers */
1406 struct completion addr_dev;
1407 int slot_id;
1408 /* Internal mirror of the HW's dcbaa */
1409 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1410 /* For keeping track of bandwidth domains per roothub. */
1411 struct xhci_root_port_bw_info *rh_bw;
1412
1413 /* DMA pools */
1414 struct dma_pool *device_pool;
1415 struct dma_pool *segment_pool;
1416 struct dma_pool *small_streams_pool;
1417 struct dma_pool *medium_streams_pool;
1418
1419 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1420 /* Poll the rings - for debugging */
1421 struct timer_list event_ring_timer;
1422 int zombie;
1423 #endif
1424 /* Host controller watchdog timer structures */
1425 unsigned int xhc_state;
1426
1427 u32 command;
1428 struct s3_save s3;
1429 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1430 *
1431 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1432 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1433 * that sees this status (other than the timer that set it) should stop touching
1434 * hardware immediately. Interrupt handlers should return immediately when
1435 * they see this status (any time they drop and re-acquire xhci->lock).
1436 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1437 * putting the TD on the canceled list, etc.
1438 *
1439 * There are no reports of xHCI host controllers that display this issue.
1440 */
1441 #define XHCI_STATE_DYING (1 << 0)
1442 #define XHCI_STATE_HALTED (1 << 1)
1443 /* Statistics */
1444 int error_bitmask;
1445 unsigned int quirks;
1446 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1447 #define XHCI_RESET_EP_QUIRK (1 << 1)
1448 #define XHCI_NEC_HOST (1 << 2)
1449 #define XHCI_AMD_PLL_FIX (1 << 3)
1450 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1451 /*
1452 * Certain Intel host controllers have a limit to the number of endpoint
1453 * contexts they can handle. Ideally, they would signal that they can't handle
1454 * anymore endpoint contexts by returning a Resource Error for the Configure
1455 * Endpoint command, but they don't. Instead they expect software to keep track
1456 * of the number of active endpoints for them, across configure endpoint
1457 * commands, reset device commands, disable slot commands, and address device
1458 * commands.
1459 */
1460 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1461 #define XHCI_BROKEN_MSI (1 << 6)
1462 #define XHCI_RESET_ON_RESUME (1 << 7)
1463 #define XHCI_SW_BW_CHECKING (1 << 8)
1464 #define XHCI_AMD_0x96_HOST (1 << 9)
1465 unsigned int num_active_eps;
1466 unsigned int limit_active_eps;
1467 /* There are two roothubs to keep track of bus suspend info for */
1468 struct xhci_bus_state bus_state[2];
1469 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1470 u8 *port_array;
1471 /* Array of pointers to USB 3.0 PORTSC registers */
1472 __le32 __iomem **usb3_ports;
1473 unsigned int num_usb3_ports;
1474 /* Array of pointers to USB 2.0 PORTSC registers */
1475 __le32 __iomem **usb2_ports;
1476 unsigned int num_usb2_ports;
1477 /* support xHCI 0.96 spec USB2 software LPM */
1478 unsigned sw_lpm_support:1;
1479 /* support xHCI 1.0 spec USB2 hardware LPM */
1480 unsigned hw_lpm_support:1;
1481 };
1482
1483 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1484 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1485 {
1486 return *((struct xhci_hcd **) (hcd->hcd_priv));
1487 }
1488
xhci_to_hcd(struct xhci_hcd * xhci)1489 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1490 {
1491 return xhci->main_hcd;
1492 }
1493
1494 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1495 #define XHCI_DEBUG 1
1496 #else
1497 #define XHCI_DEBUG 0
1498 #endif
1499
1500 #define xhci_dbg(xhci, fmt, args...) \
1501 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1502 #define xhci_info(xhci, fmt, args...) \
1503 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1504 #define xhci_err(xhci, fmt, args...) \
1505 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1506 #define xhci_warn(xhci, fmt, args...) \
1507 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1508
1509 /* TODO: copied from ehci.h - can be refactored? */
1510 /* xHCI spec says all registers are little endian */
xhci_readl(const struct xhci_hcd * xhci,__le32 __iomem * regs)1511 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1512 __le32 __iomem *regs)
1513 {
1514 return readl(regs);
1515 }
xhci_writel(struct xhci_hcd * xhci,const unsigned int val,__le32 __iomem * regs)1516 static inline void xhci_writel(struct xhci_hcd *xhci,
1517 const unsigned int val, __le32 __iomem *regs)
1518 {
1519 writel(val, regs);
1520 }
1521
1522 /*
1523 * Registers should always be accessed with double word or quad word accesses.
1524 *
1525 * Some xHCI implementations may support 64-bit address pointers. Registers
1526 * with 64-bit address pointers should be written to with dword accesses by
1527 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1528 * xHCI implementations that do not support 64-bit address pointers will ignore
1529 * the high dword, and write order is irrelevant.
1530 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1531 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1532 __le64 __iomem *regs)
1533 {
1534 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1535 u64 val_lo = readl(ptr);
1536 u64 val_hi = readl(ptr + 1);
1537 return val_lo + (val_hi << 32);
1538 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1539 static inline void xhci_write_64(struct xhci_hcd *xhci,
1540 const u64 val, __le64 __iomem *regs)
1541 {
1542 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1543 u32 val_lo = lower_32_bits(val);
1544 u32 val_hi = upper_32_bits(val);
1545
1546 writel(val_lo, ptr);
1547 writel(val_hi, ptr + 1);
1548 }
1549
xhci_link_trb_quirk(struct xhci_hcd * xhci)1550 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1551 {
1552 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1553 }
1554
1555 /* xHCI debugging */
1556 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1557 void xhci_print_registers(struct xhci_hcd *xhci);
1558 void xhci_dbg_regs(struct xhci_hcd *xhci);
1559 void xhci_print_run_regs(struct xhci_hcd *xhci);
1560 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1561 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1562 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1563 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1564 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1565 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1566 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1567 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1568 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1569 struct xhci_container_ctx *ctx);
1570 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1571 unsigned int slot_id, unsigned int ep_index,
1572 struct xhci_virt_ep *ep);
1573
1574 /* xHCI memory management */
1575 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1576 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1577 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1578 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1579 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1580 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1581 struct usb_device *udev);
1582 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1583 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1584 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1585 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1586 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1587 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1588 struct xhci_bw_info *ep_bw,
1589 struct xhci_interval_bw_table *bw_table,
1590 struct usb_device *udev,
1591 struct xhci_virt_ep *virt_ep,
1592 struct xhci_tt_bw_info *tt_info);
1593 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1594 struct xhci_virt_device *virt_dev,
1595 int old_active_eps);
1596 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1597 void xhci_update_bw_info(struct xhci_hcd *xhci,
1598 struct xhci_container_ctx *in_ctx,
1599 struct xhci_input_control_ctx *ctrl_ctx,
1600 struct xhci_virt_device *virt_dev);
1601 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1602 struct xhci_container_ctx *in_ctx,
1603 struct xhci_container_ctx *out_ctx,
1604 unsigned int ep_index);
1605 void xhci_slot_copy(struct xhci_hcd *xhci,
1606 struct xhci_container_ctx *in_ctx,
1607 struct xhci_container_ctx *out_ctx);
1608 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1609 struct usb_device *udev, struct usb_host_endpoint *ep,
1610 gfp_t mem_flags);
1611 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1612 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1613 struct xhci_virt_device *virt_dev,
1614 unsigned int ep_index);
1615 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1616 unsigned int num_stream_ctxs,
1617 unsigned int num_streams, gfp_t flags);
1618 void xhci_free_stream_info(struct xhci_hcd *xhci,
1619 struct xhci_stream_info *stream_info);
1620 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1621 struct xhci_ep_ctx *ep_ctx,
1622 struct xhci_stream_info *stream_info);
1623 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1624 struct xhci_ep_ctx *ep_ctx,
1625 struct xhci_virt_ep *ep);
1626 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1627 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1628 struct xhci_ring *xhci_dma_to_transfer_ring(
1629 struct xhci_virt_ep *ep,
1630 u64 address);
1631 struct xhci_ring *xhci_stream_id_to_ring(
1632 struct xhci_virt_device *dev,
1633 unsigned int ep_index,
1634 unsigned int stream_id);
1635 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1636 bool allocate_in_ctx, bool allocate_completion,
1637 gfp_t mem_flags);
1638 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1639 void xhci_free_command(struct xhci_hcd *xhci,
1640 struct xhci_command *command);
1641
1642 #ifdef CONFIG_PCI
1643 /* xHCI PCI glue */
1644 int xhci_register_pci(void);
1645 void xhci_unregister_pci(void);
1646 #else
xhci_register_pci(void)1647 static inline int xhci_register_pci(void) { return 0; }
xhci_unregister_pci(void)1648 static inline void xhci_unregister_pci(void) {}
1649 #endif
1650
1651 /* xHCI host controller glue */
1652 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1653 void xhci_quiesce(struct xhci_hcd *xhci);
1654 int xhci_halt(struct xhci_hcd *xhci);
1655 int xhci_reset(struct xhci_hcd *xhci);
1656 int xhci_init(struct usb_hcd *hcd);
1657 int xhci_run(struct usb_hcd *hcd);
1658 void xhci_stop(struct usb_hcd *hcd);
1659 void xhci_shutdown(struct usb_hcd *hcd);
1660 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1661
1662 #ifdef CONFIG_PM
1663 int xhci_suspend(struct xhci_hcd *xhci);
1664 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1665 #else
1666 #define xhci_suspend NULL
1667 #define xhci_resume NULL
1668 #endif
1669
1670 int xhci_get_frame(struct usb_hcd *hcd);
1671 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1672 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1673 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1674 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1675 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1676 struct xhci_virt_device *virt_dev,
1677 struct usb_device *hdev,
1678 struct usb_tt *tt, gfp_t mem_flags);
1679 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1680 struct usb_host_endpoint **eps, unsigned int num_eps,
1681 unsigned int num_streams, gfp_t mem_flags);
1682 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1683 struct usb_host_endpoint **eps, unsigned int num_eps,
1684 gfp_t mem_flags);
1685 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1686 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1687 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1688 struct usb_device *udev, int enable);
1689 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1690 struct usb_tt *tt, gfp_t mem_flags);
1691 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1692 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1693 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1694 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1695 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1696 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1697 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1698 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1699
1700 /* xHCI ring, segment, TRB, and TD functions */
1701 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1702 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1703 union xhci_trb *start_trb, union xhci_trb *end_trb,
1704 dma_addr_t suspect_dma);
1705 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1706 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1707 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1708 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1709 u32 slot_id);
1710 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1711 u32 field1, u32 field2, u32 field3, u32 field4);
1712 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1713 unsigned int ep_index, int suspend);
1714 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1715 int slot_id, unsigned int ep_index);
1716 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1717 int slot_id, unsigned int ep_index);
1718 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1719 int slot_id, unsigned int ep_index);
1720 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1721 struct urb *urb, int slot_id, unsigned int ep_index);
1722 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1723 u32 slot_id, bool command_must_succeed);
1724 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1725 u32 slot_id);
1726 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1727 unsigned int ep_index);
1728 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1729 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1730 unsigned int slot_id, unsigned int ep_index,
1731 unsigned int stream_id, struct xhci_td *cur_td,
1732 struct xhci_dequeue_state *state);
1733 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1734 unsigned int slot_id, unsigned int ep_index,
1735 unsigned int stream_id,
1736 struct xhci_dequeue_state *deq_state);
1737 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1738 struct usb_device *udev, unsigned int ep_index);
1739 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1740 unsigned int slot_id, unsigned int ep_index,
1741 struct xhci_dequeue_state *deq_state);
1742 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1743 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1744 unsigned int ep_index, unsigned int stream_id);
1745
1746 /* xHCI roothub code */
1747 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1748 int port_id, u32 link_state);
1749 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1750 int port_id, u32 port_bit);
1751 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1752 char *buf, u16 wLength);
1753 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1754
1755 #ifdef CONFIG_PM
1756 int xhci_bus_suspend(struct usb_hcd *hcd);
1757 int xhci_bus_resume(struct usb_hcd *hcd);
1758 #else
1759 #define xhci_bus_suspend NULL
1760 #define xhci_bus_resume NULL
1761 #endif /* CONFIG_PM */
1762
1763 u32 xhci_port_state_to_neutral(u32 state);
1764 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1765 u16 port);
1766 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1767
1768 /* xHCI contexts */
1769 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1770 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1771 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1772
1773 #endif /* __LINUX_XHCI_HCD_H */
1774