1 /*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/gpio.h>
37 #include <linux/spi/spi.h>
38 #include <linux/freezer.h>
39 #include <linux/module.h>
40 #include "max3107.h"
41
42 static const struct baud_table brg26_ext[] = {
43 { 300, MAX3107_BRG26_B300 },
44 { 600, MAX3107_BRG26_B600 },
45 { 1200, MAX3107_BRG26_B1200 },
46 { 2400, MAX3107_BRG26_B2400 },
47 { 4800, MAX3107_BRG26_B4800 },
48 { 9600, MAX3107_BRG26_B9600 },
49 { 19200, MAX3107_BRG26_B19200 },
50 { 57600, MAX3107_BRG26_B57600 },
51 { 115200, MAX3107_BRG26_B115200 },
52 { 230400, MAX3107_BRG26_B230400 },
53 { 460800, MAX3107_BRG26_B460800 },
54 { 921600, MAX3107_BRG26_B921600 },
55 { 0, 0 }
56 };
57
58 static const struct baud_table brg13_int[] = {
59 { 300, MAX3107_BRG13_IB300 },
60 { 600, MAX3107_BRG13_IB600 },
61 { 1200, MAX3107_BRG13_IB1200 },
62 { 2400, MAX3107_BRG13_IB2400 },
63 { 4800, MAX3107_BRG13_IB4800 },
64 { 9600, MAX3107_BRG13_IB9600 },
65 { 19200, MAX3107_BRG13_IB19200 },
66 { 57600, MAX3107_BRG13_IB57600 },
67 { 115200, MAX3107_BRG13_IB115200 },
68 { 230400, MAX3107_BRG13_IB230400 },
69 { 460800, MAX3107_BRG13_IB460800 },
70 { 921600, MAX3107_BRG13_IB921600 },
71 { 0, 0 }
72 };
73
get_new_brg(int baud,struct max3107_port * s)74 static u32 get_new_brg(int baud, struct max3107_port *s)
75 {
76 int i;
77 const struct baud_table *baud_tbl = s->baud_tbl;
78
79 for (i = 0; i < 13; i++) {
80 if (baud == baud_tbl[i].baud)
81 return baud_tbl[i].new_brg;
82 }
83
84 return 0;
85 }
86
87 /* Perform SPI transfer for write/read of device register(s) */
max3107_rw(struct max3107_port * s,u8 * tx,u8 * rx,int len)88 int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
89 {
90 struct spi_message spi_msg;
91 struct spi_transfer spi_xfer;
92
93 /* Initialize SPI ,message */
94 spi_message_init(&spi_msg);
95
96 /* Initialize SPI transfer */
97 memset(&spi_xfer, 0, sizeof spi_xfer);
98 spi_xfer.len = len;
99 spi_xfer.tx_buf = tx;
100 spi_xfer.rx_buf = rx;
101 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
102
103 /* Add SPI transfer to SPI message */
104 spi_message_add_tail(&spi_xfer, &spi_msg);
105
106 #ifdef DBG_TRACE_SPI_DATA
107 {
108 int i;
109 pr_info("tx len %d:\n", spi_xfer.len);
110 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
111 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
112 pr_info("\n");
113 }
114 #endif
115
116 /* Perform synchronous SPI transfer */
117 if (spi_sync(s->spi, &spi_msg)) {
118 dev_err(&s->spi->dev, "spi_sync failure\n");
119 return -EIO;
120 }
121
122 #ifdef DBG_TRACE_SPI_DATA
123 if (spi_xfer.rx_buf) {
124 int i;
125 pr_info("rx len %d:\n", spi_xfer.len);
126 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
127 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
128 pr_info("\n");
129 }
130 #endif
131 return 0;
132 }
133 EXPORT_SYMBOL_GPL(max3107_rw);
134
135 /* Puts received data to circular buffer */
put_data_to_circ_buf(struct max3107_port * s,unsigned char * data,int len)136 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
137 int len)
138 {
139 struct uart_port *port = &s->port;
140 struct tty_struct *tty;
141
142 if (!port->state)
143 return;
144
145 tty = port->state->port.tty;
146 if (!tty)
147 return;
148
149 /* Insert received data */
150 tty_insert_flip_string(tty, data, len);
151 /* Update RX counter */
152 port->icount.rx += len;
153 }
154
155 /* Handle data receiving */
max3107_handlerx(struct max3107_port * s,u16 rxlvl)156 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
157 {
158 int i;
159 int j;
160 int len; /* SPI transfer buffer length */
161 u16 *buf;
162 u8 *valid_str;
163
164 if (!s->rx_enabled)
165 /* RX is disabled */
166 return;
167
168 if (rxlvl == 0) {
169 /* RX fifo is empty */
170 return;
171 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
172 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
173 /* Ensure sanity of RX level */
174 rxlvl = MAX3107_RX_FIFO_SIZE;
175 }
176 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
177 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
178 return;
179 }
180 buf = s->rxbuf;
181 valid_str = s->rxstr;
182 while (rxlvl) {
183 pr_debug("rxlvl %d\n", rxlvl);
184 /* Clear buffer */
185 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
186 len = 0;
187 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
188 /* First disable RX FIFO interrupt */
189 pr_debug("Disabling RX INT\n");
190 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
191 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
192 buf[0] |= s->irqen_reg;
193 len++;
194 }
195 /* Just increase the length by amount of words in FIFO since
196 * buffer was zeroed and SPI transfer of 0x0000 means reading
197 * from RX FIFO
198 */
199 len += rxlvl;
200 /* Append RX level query */
201 buf[len] = MAX3107_RXFIFOLVL_REG;
202 len++;
203
204 /* Perform the SPI transfer */
205 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
206 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
207 return;
208 }
209
210 /* Skip RX FIFO interrupt disabling word if it was added */
211 j = ((len - 1) - rxlvl);
212 /* Read received words */
213 for (i = 0; i < rxlvl; i++, j++)
214 valid_str[i] = (u8)buf[j];
215 put_data_to_circ_buf(s, valid_str, rxlvl);
216 /* Get new RX level */
217 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
218 }
219
220 if (s->rx_enabled) {
221 /* RX still enabled, re-enable RX FIFO interrupt */
222 pr_debug("Enabling RX INT\n");
223 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
224 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
225 buf[0] |= s->irqen_reg;
226 if (max3107_rw(s, (u8 *)buf, NULL, 2))
227 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
228 }
229
230 /* Push the received data to receivers */
231 if (s->port.state->port.tty)
232 tty_flip_buffer_push(s->port.state->port.tty);
233 }
234
235
236 /* Handle data sending */
max3107_handletx(struct max3107_port * s)237 static void max3107_handletx(struct max3107_port *s)
238 {
239 struct circ_buf *xmit = &s->port.state->xmit;
240 int i;
241 unsigned long flags;
242 int len; /* SPI transfer buffer length */
243 u16 *buf;
244
245 if (!s->tx_fifo_empty)
246 /* Don't send more data before previous data is sent */
247 return;
248
249 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
250 /* No data to send or TX is stopped */
251 return;
252
253 if (!s->txbuf) {
254 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
255 return;
256 }
257 buf = s->txbuf;
258 /* Get length of data pending in circular buffer */
259 len = uart_circ_chars_pending(xmit);
260 if (len) {
261 /* Limit to size of TX FIFO */
262 if (len > MAX3107_TX_FIFO_SIZE)
263 len = MAX3107_TX_FIFO_SIZE;
264
265 pr_debug("txlen %d\n", len);
266
267 /* Update TX counter */
268 s->port.icount.tx += len;
269
270 /* TX FIFO will no longer be empty */
271 s->tx_fifo_empty = 0;
272
273 i = 0;
274 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
275 /* First disable TX empty interrupt */
276 pr_debug("Disabling TE INT\n");
277 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
278 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
279 buf[i] |= s->irqen_reg;
280 i++;
281 len++;
282 }
283 /* Add data to send */
284 spin_lock_irqsave(&s->port.lock, flags);
285 for ( ; i < len ; i++) {
286 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
287 buf[i] |= ((u16)xmit->buf[xmit->tail] &
288 MAX3107_SPI_TX_DATA_MASK);
289 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
290 }
291 spin_unlock_irqrestore(&s->port.lock, flags);
292 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
293 /* Enable TX empty interrupt */
294 pr_debug("Enabling TE INT\n");
295 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
296 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
297 buf[i] |= s->irqen_reg;
298 i++;
299 len++;
300 }
301 if (!s->tx_enabled) {
302 /* Enable TX */
303 pr_debug("Enable TX\n");
304 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
305 spin_lock_irqsave(&s->data_lock, flags);
306 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
307 buf[i] |= s->mode1_reg;
308 spin_unlock_irqrestore(&s->data_lock, flags);
309 s->tx_enabled = 1;
310 i++;
311 len++;
312 }
313
314 /* Perform the SPI transfer */
315 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
316 dev_err(&s->spi->dev,
317 "SPI transfer TX handling failed\n");
318 return;
319 }
320 }
321
322 /* Indicate wake up if circular buffer is getting low on data */
323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
324 uart_write_wakeup(&s->port);
325
326 }
327
328 /* Handle interrupts
329 * Also reads and returns current RX FIFO level
330 */
handle_interrupt(struct max3107_port * s)331 static u16 handle_interrupt(struct max3107_port *s)
332 {
333 u16 buf[4]; /* Buffer for SPI transfers */
334 u8 irq_status;
335 u16 rx_level;
336 unsigned long flags;
337
338 /* Read IRQ status register */
339 buf[0] = MAX3107_IRQSTS_REG;
340 /* Read status IRQ status register */
341 buf[1] = MAX3107_STS_IRQSTS_REG;
342 /* Read LSR IRQ status register */
343 buf[2] = MAX3107_LSR_IRQSTS_REG;
344 /* Query RX level */
345 buf[3] = MAX3107_RXFIFOLVL_REG;
346
347 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
348 dev_err(&s->spi->dev,
349 "SPI transfer for INTR handling failed\n");
350 return 0;
351 }
352
353 irq_status = (u8)buf[0];
354 pr_debug("IRQSTS %x\n", irq_status);
355 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
356
357 if (irq_status & MAX3107_IRQ_LSR_BIT) {
358 /* LSR interrupt */
359 if (buf[2] & MAX3107_LSR_RXTO_BIT)
360 /* RX timeout interrupt,
361 * handled by normal RX handling
362 */
363 pr_debug("RX TO INT\n");
364 }
365
366 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
367 /* Tx empty interrupt,
368 * disable TX and set tx_fifo_empty flag
369 */
370 pr_debug("TE INT, disabling TX\n");
371 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
372 spin_lock_irqsave(&s->data_lock, flags);
373 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
374 buf[0] |= s->mode1_reg;
375 spin_unlock_irqrestore(&s->data_lock, flags);
376 if (max3107_rw(s, (u8 *)buf, NULL, 2))
377 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
378 s->tx_enabled = 0;
379 s->tx_fifo_empty = 1;
380 }
381
382 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
383 /* RX FIFO interrupt,
384 * handled by normal RX handling
385 */
386 pr_debug("RFIFO INT\n");
387
388 /* Return RX level */
389 return rx_level;
390 }
391
392 /* Trigger work thread*/
max3107_dowork(struct max3107_port * s)393 static void max3107_dowork(struct max3107_port *s)
394 {
395 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
396 queue_work(s->workqueue, &s->work);
397 else
398 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
399 }
400
401 /* Work thread */
max3107_work(struct work_struct * w)402 static void max3107_work(struct work_struct *w)
403 {
404 struct max3107_port *s = container_of(w, struct max3107_port, work);
405 u16 rxlvl = 0;
406 int len; /* SPI transfer buffer length */
407 u16 buf[5]; /* Buffer for SPI transfers */
408 unsigned long flags;
409
410 /* Start by reading current RX FIFO level */
411 buf[0] = MAX3107_RXFIFOLVL_REG;
412 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
413 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
414 rxlvl = 0;
415 } else {
416 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
417 }
418
419 do {
420 pr_debug("rxlvl %d\n", rxlvl);
421
422 /* Handle RX */
423 max3107_handlerx(s, rxlvl);
424 rxlvl = 0;
425
426 if (s->handle_irq) {
427 /* Handle pending interrupts
428 * We also get new RX FIFO level since new data may
429 * have been received while pushing received data to
430 * receivers
431 */
432 s->handle_irq = 0;
433 rxlvl = handle_interrupt(s);
434 }
435
436 /* Handle TX */
437 max3107_handletx(s);
438
439 /* Handle configuration changes */
440 len = 0;
441 spin_lock_irqsave(&s->data_lock, flags);
442 if (s->mode1_commit) {
443 pr_debug("mode1_commit\n");
444 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
445 buf[len++] |= s->mode1_reg;
446 s->mode1_commit = 0;
447 }
448 if (s->lcr_commit) {
449 pr_debug("lcr_commit\n");
450 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
451 buf[len++] |= s->lcr_reg;
452 s->lcr_commit = 0;
453 }
454 if (s->brg_commit) {
455 pr_debug("brg_commit\n");
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 16) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
460 buf[len++] |= ((s->brg_cfg >> 8) &
461 MAX3107_SPI_TX_DATA_MASK);
462 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
463 buf[len++] |= ((s->brg_cfg) & 0xff);
464 s->brg_commit = 0;
465 }
466 spin_unlock_irqrestore(&s->data_lock, flags);
467
468 if (len > 0) {
469 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
470 dev_err(&s->spi->dev,
471 "SPI transfer config failed\n");
472 }
473
474 /* Reloop if interrupt handling indicated data in RX FIFO */
475 } while (rxlvl);
476
477 }
478
479 /* Set sleep mode */
max3107_set_sleep(struct max3107_port * s,int mode)480 static void max3107_set_sleep(struct max3107_port *s, int mode)
481 {
482 u16 buf[1]; /* Buffer for SPI transfer */
483 unsigned long flags;
484 pr_debug("enter, mode %d\n", mode);
485
486 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
487 spin_lock_irqsave(&s->data_lock, flags);
488 switch (mode) {
489 case MAX3107_DISABLE_FORCED_SLEEP:
490 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
491 break;
492 case MAX3107_ENABLE_FORCED_SLEEP:
493 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
494 break;
495 case MAX3107_DISABLE_AUTOSLEEP:
496 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
497 break;
498 case MAX3107_ENABLE_AUTOSLEEP:
499 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
500 break;
501 default:
502 spin_unlock_irqrestore(&s->data_lock, flags);
503 dev_warn(&s->spi->dev, "invalid sleep mode\n");
504 return;
505 }
506 buf[0] |= s->mode1_reg;
507 spin_unlock_irqrestore(&s->data_lock, flags);
508
509 if (max3107_rw(s, (u8 *)buf, NULL, 2))
510 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
511
512 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
513 mode == MAX3107_DISABLE_FORCED_SLEEP)
514 msleep(MAX3107_WAKEUP_DELAY);
515 }
516
517 /* Perform full register initialization */
max3107_register_init(struct max3107_port * s)518 static void max3107_register_init(struct max3107_port *s)
519 {
520 u16 buf[11]; /* Buffer for SPI transfers */
521
522 /* 1. Configure baud rate, 9600 as default */
523 s->baud = 9600;
524 /* the below is default*/
525 if (s->ext_clk) {
526 s->brg_cfg = MAX3107_BRG26_B9600;
527 s->baud_tbl = (struct baud_table *)brg26_ext;
528 } else {
529 s->brg_cfg = MAX3107_BRG13_IB9600;
530 s->baud_tbl = (struct baud_table *)brg13_int;
531 }
532
533 if (s->pdata->init)
534 s->pdata->init(s);
535
536 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
537 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
538 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
539 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
540 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
541 | ((s->brg_cfg) & 0xff);
542
543 /* 2. Configure LCR register, 8N1 mode by default */
544 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
545 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
546 | s->lcr_reg;
547
548 /* 3. Configure MODE 1 register */
549 s->mode1_reg = 0;
550 /* Enable IRQ pin */
551 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
552 /* Disable TX */
553 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
554 s->tx_enabled = 0;
555 /* RX is enabled */
556 s->rx_enabled = 1;
557 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
558 | s->mode1_reg;
559
560 /* 4. Configure MODE 2 register */
561 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
562 if (s->loopback) {
563 /* Enable loopback */
564 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
565 }
566 /* Reset FIFOs */
567 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
568 s->tx_fifo_empty = 1;
569
570 /* 5. Configure FIFO trigger level register */
571 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
572 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
573 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
574
575 /* 6. Configure flow control levels */
576 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
577 /* Flow control halt level 96, resume level 48 */
578 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
579
580 /* 7. Configure flow control */
581 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
582 /* Enable auto CTS and auto RTS flow control */
583 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
584
585 /* 8. Configure RX timeout register */
586 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
587 /* Timeout after 48 character intervals */
588 buf[9] |= 0x0030;
589
590 /* 9. Configure LSR interrupt enable register */
591 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
592 /* Enable RX timeout interrupt */
593 buf[10] |= MAX3107_LSR_RXTO_BIT;
594
595 /* Perform SPI transfer */
596 if (max3107_rw(s, (u8 *)buf, NULL, 22))
597 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
598
599 /* 10. Clear IRQ status register by reading it */
600 buf[0] = MAX3107_IRQSTS_REG;
601
602 /* 11. Configure interrupt enable register */
603 /* Enable LSR interrupt */
604 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
605 /* Enable RX FIFO interrupt */
606 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
607 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
608 | s->irqen_reg;
609
610 /* 12. Clear FIFO reset that was set in step 6 */
611 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
612 if (s->loopback) {
613 /* Keep loopback enabled */
614 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
615 }
616
617 /* Perform SPI transfer */
618 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
619 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
620
621 }
622
623 /* IRQ handler */
max3107_irq(int irqno,void * dev_id)624 static irqreturn_t max3107_irq(int irqno, void *dev_id)
625 {
626 struct max3107_port *s = dev_id;
627
628 if (irqno != s->spi->irq) {
629 /* Unexpected IRQ */
630 return IRQ_NONE;
631 }
632
633 /* Indicate irq */
634 s->handle_irq = 1;
635
636 /* Trigger work thread */
637 max3107_dowork(s);
638
639 return IRQ_HANDLED;
640 }
641
642 /* HW suspension function
643 *
644 * Currently autosleep is used to decrease current consumption, alternative
645 * approach would be to set the chip to reset mode if UART is not being
646 * used but that would mess the GPIOs
647 *
648 */
max3107_hw_susp(struct max3107_port * s,int suspend)649 void max3107_hw_susp(struct max3107_port *s, int suspend)
650 {
651 pr_debug("enter, suspend %d\n", suspend);
652
653 if (suspend) {
654 /* Suspend requested,
655 * enable autosleep to decrease current consumption
656 */
657 s->suspended = 1;
658 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
659 } else {
660 /* Resume requested,
661 * disable autosleep
662 */
663 s->suspended = 0;
664 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
665 }
666 }
667 EXPORT_SYMBOL_GPL(max3107_hw_susp);
668
669 /* Modem status IRQ enabling */
max3107_enable_ms(struct uart_port * port)670 static void max3107_enable_ms(struct uart_port *port)
671 {
672 /* Modem status not supported */
673 }
674
675 /* Data send function */
max3107_start_tx(struct uart_port * port)676 static void max3107_start_tx(struct uart_port *port)
677 {
678 struct max3107_port *s = container_of(port, struct max3107_port, port);
679
680 /* Trigger work thread for sending data */
681 max3107_dowork(s);
682 }
683
684 /* Function for checking that there is no pending transfers */
max3107_tx_empty(struct uart_port * port)685 static unsigned int max3107_tx_empty(struct uart_port *port)
686 {
687 struct max3107_port *s = container_of(port, struct max3107_port, port);
688
689 pr_debug("returning %d\n",
690 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
691 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
692 }
693
694 /* Function for stopping RX */
max3107_stop_rx(struct uart_port * port)695 static void max3107_stop_rx(struct uart_port *port)
696 {
697 struct max3107_port *s = container_of(port, struct max3107_port, port);
698 unsigned long flags;
699
700 /* Set RX disabled in MODE 1 register */
701 spin_lock_irqsave(&s->data_lock, flags);
702 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
703 s->mode1_commit = 1;
704 spin_unlock_irqrestore(&s->data_lock, flags);
705 /* Set RX disabled */
706 s->rx_enabled = 0;
707 /* Trigger work thread for doing the actual configuration change */
708 max3107_dowork(s);
709 }
710
711 /* Function for returning control pin states */
max3107_get_mctrl(struct uart_port * port)712 static unsigned int max3107_get_mctrl(struct uart_port *port)
713 {
714 /* DCD and DSR are not wired and CTS/RTS is handled automatically
715 * so just indicate DSR and CAR asserted
716 */
717 return TIOCM_DSR | TIOCM_CAR;
718 }
719
720 /* Function for setting control pin states */
max3107_set_mctrl(struct uart_port * port,unsigned int mctrl)721 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
722 {
723 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
724 * so do nothing
725 */
726 }
727
728 /* Function for configuring UART parameters */
max3107_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)729 static void max3107_set_termios(struct uart_port *port,
730 struct ktermios *termios,
731 struct ktermios *old)
732 {
733 struct max3107_port *s = container_of(port, struct max3107_port, port);
734 struct tty_struct *tty;
735 int baud;
736 u16 new_lcr = 0;
737 u32 new_brg = 0;
738 unsigned long flags;
739
740 if (!port->state)
741 return;
742
743 tty = port->state->port.tty;
744 if (!tty)
745 return;
746
747 /* Get new LCR register values */
748 /* Word size */
749 if ((termios->c_cflag & CSIZE) == CS7)
750 new_lcr |= MAX3107_LCR_WORD_LEN_7;
751 else
752 new_lcr |= MAX3107_LCR_WORD_LEN_8;
753
754 /* Parity */
755 if (termios->c_cflag & PARENB) {
756 new_lcr |= MAX3107_LCR_PARITY_BIT;
757 if (!(termios->c_cflag & PARODD))
758 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
759 }
760
761 /* Stop bits */
762 if (termios->c_cflag & CSTOPB) {
763 /* 2 stop bits */
764 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
765 }
766
767 /* Mask termios capabilities we don't support */
768 termios->c_cflag &= ~CMSPAR;
769
770 /* Set status ignore mask */
771 s->port.ignore_status_mask = 0;
772 if (termios->c_iflag & IGNPAR)
773 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
774
775 /* Set low latency to immediately handle pushed data */
776 s->port.state->port.tty->low_latency = 1;
777
778 /* Get new baud rate generator configuration */
779 baud = tty_get_baud_rate(tty);
780
781 spin_lock_irqsave(&s->data_lock, flags);
782 new_brg = get_new_brg(baud, s);
783 /* if can't find the corrent config, use previous */
784 if (!new_brg) {
785 baud = s->baud;
786 new_brg = s->brg_cfg;
787 }
788 spin_unlock_irqrestore(&s->data_lock, flags);
789 tty_termios_encode_baud_rate(termios, baud, baud);
790 s->baud = baud;
791
792 /* Update timeout according to new baud rate */
793 uart_update_timeout(port, termios->c_cflag, baud);
794
795 spin_lock_irqsave(&s->data_lock, flags);
796 if (s->lcr_reg != new_lcr) {
797 s->lcr_reg = new_lcr;
798 s->lcr_commit = 1;
799 }
800 if (s->brg_cfg != new_brg) {
801 s->brg_cfg = new_brg;
802 s->brg_commit = 1;
803 }
804 spin_unlock_irqrestore(&s->data_lock, flags);
805
806 /* Trigger work thread for doing the actual configuration change */
807 max3107_dowork(s);
808 }
809
810 /* Port shutdown function */
max3107_shutdown(struct uart_port * port)811 static void max3107_shutdown(struct uart_port *port)
812 {
813 struct max3107_port *s = container_of(port, struct max3107_port, port);
814
815 if (s->suspended && s->pdata->hw_suspend)
816 s->pdata->hw_suspend(s, 0);
817
818 /* Free the interrupt */
819 free_irq(s->spi->irq, s);
820
821 if (s->workqueue) {
822 /* Flush and destroy work queue */
823 flush_workqueue(s->workqueue);
824 destroy_workqueue(s->workqueue);
825 s->workqueue = NULL;
826 }
827
828 /* Suspend HW */
829 if (s->pdata->hw_suspend)
830 s->pdata->hw_suspend(s, 1);
831 }
832
833 /* Port startup function */
max3107_startup(struct uart_port * port)834 static int max3107_startup(struct uart_port *port)
835 {
836 struct max3107_port *s = container_of(port, struct max3107_port, port);
837
838 /* Initialize work queue */
839 s->workqueue = create_freezable_workqueue("max3107");
840 if (!s->workqueue) {
841 dev_err(&s->spi->dev, "Workqueue creation failed\n");
842 return -EBUSY;
843 }
844 INIT_WORK(&s->work, max3107_work);
845
846 /* Setup IRQ */
847 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
848 "max3107", s)) {
849 dev_err(&s->spi->dev, "IRQ reguest failed\n");
850 destroy_workqueue(s->workqueue);
851 s->workqueue = NULL;
852 return -EBUSY;
853 }
854
855 /* Resume HW */
856 if (s->pdata->hw_suspend)
857 s->pdata->hw_suspend(s, 0);
858
859 /* Init registers */
860 max3107_register_init(s);
861
862 return 0;
863 }
864
865 /* Port type function */
max3107_type(struct uart_port * port)866 static const char *max3107_type(struct uart_port *port)
867 {
868 struct max3107_port *s = container_of(port, struct max3107_port, port);
869 return s->spi->modalias;
870 }
871
872 /* Port release function */
max3107_release_port(struct uart_port * port)873 static void max3107_release_port(struct uart_port *port)
874 {
875 /* Do nothing */
876 }
877
878 /* Port request function */
max3107_request_port(struct uart_port * port)879 static int max3107_request_port(struct uart_port *port)
880 {
881 /* Do nothing */
882 return 0;
883 }
884
885 /* Port config function */
max3107_config_port(struct uart_port * port,int flags)886 static void max3107_config_port(struct uart_port *port, int flags)
887 {
888 struct max3107_port *s = container_of(port, struct max3107_port, port);
889 s->port.type = PORT_MAX3107;
890 }
891
892 /* Port verify function */
max3107_verify_port(struct uart_port * port,struct serial_struct * ser)893 static int max3107_verify_port(struct uart_port *port,
894 struct serial_struct *ser)
895 {
896 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
897 return 0;
898
899 return -EINVAL;
900 }
901
902 /* Port stop TX function */
max3107_stop_tx(struct uart_port * port)903 static void max3107_stop_tx(struct uart_port *port)
904 {
905 /* Do nothing */
906 }
907
908 /* Port break control function */
max3107_break_ctl(struct uart_port * port,int break_state)909 static void max3107_break_ctl(struct uart_port *port, int break_state)
910 {
911 /* We don't support break control, do nothing */
912 }
913
914
915 /* Port functions */
916 static struct uart_ops max3107_ops = {
917 .tx_empty = max3107_tx_empty,
918 .set_mctrl = max3107_set_mctrl,
919 .get_mctrl = max3107_get_mctrl,
920 .stop_tx = max3107_stop_tx,
921 .start_tx = max3107_start_tx,
922 .stop_rx = max3107_stop_rx,
923 .enable_ms = max3107_enable_ms,
924 .break_ctl = max3107_break_ctl,
925 .startup = max3107_startup,
926 .shutdown = max3107_shutdown,
927 .set_termios = max3107_set_termios,
928 .type = max3107_type,
929 .release_port = max3107_release_port,
930 .request_port = max3107_request_port,
931 .config_port = max3107_config_port,
932 .verify_port = max3107_verify_port,
933 };
934
935 /* UART driver data */
936 static struct uart_driver max3107_uart_driver = {
937 .owner = THIS_MODULE,
938 .driver_name = "ttyMAX",
939 .dev_name = "ttyMAX",
940 .nr = 1,
941 };
942
943 static int driver_registered = 0;
944
945
946
947 /* 'Generic' platform data */
948 static struct max3107_plat generic_plat_data = {
949 .loopback = 0,
950 .ext_clk = 1,
951 .hw_suspend = max3107_hw_susp,
952 .polled_mode = 0,
953 .poll_time = 0,
954 };
955
956
957 /*******************************************************************/
958
959 /**
960 * max3107_probe - SPI bus probe entry point
961 * @spi: the spi device
962 *
963 * SPI wants us to probe this device and if appropriate claim it.
964 * Perform any platform specific requirements and then initialise
965 * the device.
966 */
967
max3107_probe(struct spi_device * spi,struct max3107_plat * pdata)968 int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
969 {
970 struct max3107_port *s;
971 u16 buf[2]; /* Buffer for SPI transfers */
972 int retval;
973
974 pr_info("enter max3107 probe\n");
975
976 /* Allocate port structure */
977 s = kzalloc(sizeof(*s), GFP_KERNEL);
978 if (!s) {
979 pr_err("Allocating port structure failed\n");
980 return -ENOMEM;
981 }
982
983 s->pdata = pdata;
984
985 /* SPI Rx buffer
986 * +2 for RX FIFO interrupt
987 * disabling and RX level query
988 */
989 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
990 if (!s->rxbuf) {
991 pr_err("Allocating RX buffer failed\n");
992 retval = -ENOMEM;
993 goto err_free4;
994 }
995 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
996 if (!s->rxstr) {
997 pr_err("Allocating RX buffer failed\n");
998 retval = -ENOMEM;
999 goto err_free3;
1000 }
1001 /* SPI Tx buffer
1002 * SPI transfer buffer
1003 * +3 for TX FIFO empty
1004 * interrupt disabling and
1005 * enabling and TX enabling
1006 */
1007 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1008 if (!s->txbuf) {
1009 pr_err("Allocating TX buffer failed\n");
1010 retval = -ENOMEM;
1011 goto err_free2;
1012 }
1013 /* Initialize shared data lock */
1014 spin_lock_init(&s->data_lock);
1015
1016 /* SPI intializations */
1017 dev_set_drvdata(&spi->dev, s);
1018 spi->mode = SPI_MODE_0;
1019 spi->dev.platform_data = pdata;
1020 spi->bits_per_word = 16;
1021 s->ext_clk = pdata->ext_clk;
1022 s->loopback = pdata->loopback;
1023 spi_setup(spi);
1024 s->spi = spi;
1025
1026 /* Check REV ID to ensure we are talking to what we expect */
1027 buf[0] = MAX3107_REVID_REG;
1028 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1029 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1030 retval = -EIO;
1031 goto err_free1;
1032 }
1033 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1034 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1035 dev_err(&s->spi->dev, "REVID %x does not match\n",
1036 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1037 retval = -ENODEV;
1038 goto err_free1;
1039 }
1040
1041 /* Disable all interrupts */
1042 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1043 buf[0] |= 0x0000;
1044
1045 /* Configure clock source */
1046 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1047 if (s->ext_clk) {
1048 /* External clock */
1049 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1050 }
1051
1052 /* PLL bypass ON */
1053 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1054
1055 /* Perform SPI transfer */
1056 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1057 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1058 retval = -EIO;
1059 goto err_free1;
1060 }
1061
1062 /* Register UART driver */
1063 if (!driver_registered) {
1064 retval = uart_register_driver(&max3107_uart_driver);
1065 if (retval) {
1066 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1067 goto err_free1;
1068 }
1069 driver_registered = 1;
1070 }
1071
1072 /* Initialize UART port data */
1073 s->port.fifosize = 128;
1074 s->port.ops = &max3107_ops;
1075 s->port.line = 0;
1076 s->port.dev = &spi->dev;
1077 s->port.uartclk = 9600;
1078 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1079 s->port.irq = s->spi->irq;
1080 s->port.type = PORT_MAX3107;
1081
1082 /* Add UART port */
1083 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1084 if (retval < 0) {
1085 dev_err(&s->spi->dev, "Adding UART port failed\n");
1086 goto err_free1;
1087 }
1088
1089 if (pdata->configure) {
1090 retval = pdata->configure(s);
1091 if (retval < 0)
1092 goto err_free1;
1093 }
1094
1095 /* Go to suspend mode */
1096 if (pdata->hw_suspend)
1097 pdata->hw_suspend(s, 1);
1098
1099 return 0;
1100
1101 err_free1:
1102 kfree(s->txbuf);
1103 err_free2:
1104 kfree(s->rxstr);
1105 err_free3:
1106 kfree(s->rxbuf);
1107 err_free4:
1108 kfree(s);
1109 return retval;
1110 }
1111 EXPORT_SYMBOL_GPL(max3107_probe);
1112
1113 /* Driver remove function */
max3107_remove(struct spi_device * spi)1114 int max3107_remove(struct spi_device *spi)
1115 {
1116 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1117
1118 pr_info("enter max3107 remove\n");
1119
1120 /* Remove port */
1121 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1122 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1123
1124
1125 /* Free TxRx buffer */
1126 kfree(s->rxbuf);
1127 kfree(s->rxstr);
1128 kfree(s->txbuf);
1129
1130 /* Free port structure */
1131 kfree(s);
1132
1133 return 0;
1134 }
1135 EXPORT_SYMBOL_GPL(max3107_remove);
1136
1137 /* Driver suspend function */
max3107_suspend(struct spi_device * spi,pm_message_t state)1138 int max3107_suspend(struct spi_device *spi, pm_message_t state)
1139 {
1140 #ifdef CONFIG_PM
1141 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1142
1143 pr_debug("enter suspend\n");
1144
1145 /* Suspend UART port */
1146 uart_suspend_port(&max3107_uart_driver, &s->port);
1147
1148 /* Go to suspend mode */
1149 if (s->pdata->hw_suspend)
1150 s->pdata->hw_suspend(s, 1);
1151 #endif /* CONFIG_PM */
1152 return 0;
1153 }
1154 EXPORT_SYMBOL_GPL(max3107_suspend);
1155
1156 /* Driver resume function */
max3107_resume(struct spi_device * spi)1157 int max3107_resume(struct spi_device *spi)
1158 {
1159 #ifdef CONFIG_PM
1160 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1161
1162 pr_debug("enter resume\n");
1163
1164 /* Resume from suspend */
1165 if (s->pdata->hw_suspend)
1166 s->pdata->hw_suspend(s, 0);
1167
1168 /* Resume UART port */
1169 uart_resume_port(&max3107_uart_driver, &s->port);
1170 #endif /* CONFIG_PM */
1171 return 0;
1172 }
1173 EXPORT_SYMBOL_GPL(max3107_resume);
1174
max3107_probe_generic(struct spi_device * spi)1175 static int max3107_probe_generic(struct spi_device *spi)
1176 {
1177 return max3107_probe(spi, &generic_plat_data);
1178 }
1179
1180 /* Spi driver data */
1181 static struct spi_driver max3107_driver = {
1182 .driver = {
1183 .name = "max3107",
1184 .owner = THIS_MODULE,
1185 },
1186 .probe = max3107_probe_generic,
1187 .remove = __devexit_p(max3107_remove),
1188 .suspend = max3107_suspend,
1189 .resume = max3107_resume,
1190 };
1191
1192 /* Driver init function */
max3107_init(void)1193 static int __init max3107_init(void)
1194 {
1195 pr_info("enter max3107 init\n");
1196 return spi_register_driver(&max3107_driver);
1197 }
1198
1199 /* Driver exit function */
max3107_exit(void)1200 static void __exit max3107_exit(void)
1201 {
1202 pr_info("enter max3107 exit\n");
1203 /* Unregister UART driver */
1204 if (driver_registered)
1205 uart_unregister_driver(&max3107_uart_driver);
1206 spi_unregister_driver(&max3107_driver);
1207 }
1208
1209 module_init(max3107_init);
1210 module_exit(max3107_exit);
1211
1212 MODULE_DESCRIPTION("MAX3107 driver");
1213 MODULE_AUTHOR("Aavamobile");
1214 MODULE_ALIAS("spi:max3107");
1215 MODULE_LICENSE("GPL v2");
1216