1 /*
2 * Driver for CPM (SCC/SMC) serial ports; core driver
3 *
4 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
5 * Based on ppc8xx.c by Thomas Gleixner
6 * Based on drivers/serial/amba.c by Russell King
7 *
8 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
9 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
10 *
11 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
12 * (C) 2004 Intracom, S.A.
13 * (C) 2005-2006 MontaVista Software, Inc.
14 * Vitaly Bordug <vbordug@ru.mvista.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 *
30 */
31
32 #include <linux/module.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/serial.h>
38 #include <linux/console.h>
39 #include <linux/sysrq.h>
40 #include <linux/device.h>
41 #include <linux/bootmem.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/fs_uart_pd.h>
44 #include <linux/of_platform.h>
45 #include <linux/gpio.h>
46 #include <linux/of_gpio.h>
47 #include <linux/clk.h>
48
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/delay.h>
52 #include <asm/fs_pd.h>
53 #include <asm/udbg.h>
54
55 #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56 #define SUPPORT_SYSRQ
57 #endif
58
59 #include <linux/serial_core.h>
60 #include <linux/kernel.h>
61
62 #include "cpm_uart.h"
63
64
65 /**************************************************************/
66
67 static int cpm_uart_tx_pump(struct uart_port *port);
68 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
69 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
70 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
71
72 /**************************************************************/
73
74 #define HW_BUF_SPD_THRESHOLD 9600
75
76 /*
77 * Check, if transmit buffers are processed
78 */
cpm_uart_tx_empty(struct uart_port * port)79 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
80 {
81 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
82 cbd_t __iomem *bdp = pinfo->tx_bd_base;
83 int ret = 0;
84
85 while (1) {
86 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
87 break;
88
89 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
90 ret = TIOCSER_TEMT;
91 break;
92 }
93 bdp++;
94 }
95
96 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
97
98 return ret;
99 }
100
cpm_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)101 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
102 {
103 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
104
105 if (pinfo->gpios[GPIO_RTS] >= 0)
106 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
107
108 if (pinfo->gpios[GPIO_DTR] >= 0)
109 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
110 }
111
cpm_uart_get_mctrl(struct uart_port * port)112 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
113 {
114 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
115 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
116
117 if (pinfo->gpios[GPIO_CTS] >= 0) {
118 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
119 mctrl &= ~TIOCM_CTS;
120 }
121
122 if (pinfo->gpios[GPIO_DSR] >= 0) {
123 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
124 mctrl &= ~TIOCM_DSR;
125 }
126
127 if (pinfo->gpios[GPIO_DCD] >= 0) {
128 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
129 mctrl &= ~TIOCM_CAR;
130 }
131
132 if (pinfo->gpios[GPIO_RI] >= 0) {
133 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
134 mctrl |= TIOCM_RNG;
135 }
136
137 return mctrl;
138 }
139
140 /*
141 * Stop transmitter
142 */
cpm_uart_stop_tx(struct uart_port * port)143 static void cpm_uart_stop_tx(struct uart_port *port)
144 {
145 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
146 smc_t __iomem *smcp = pinfo->smcp;
147 scc_t __iomem *sccp = pinfo->sccp;
148
149 pr_debug("CPM uart[%d]:stop tx\n", port->line);
150
151 if (IS_SMC(pinfo))
152 clrbits8(&smcp->smc_smcm, SMCM_TX);
153 else
154 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
155 }
156
157 /*
158 * Start transmitter
159 */
cpm_uart_start_tx(struct uart_port * port)160 static void cpm_uart_start_tx(struct uart_port *port)
161 {
162 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
163 smc_t __iomem *smcp = pinfo->smcp;
164 scc_t __iomem *sccp = pinfo->sccp;
165
166 pr_debug("CPM uart[%d]:start tx\n", port->line);
167
168 if (IS_SMC(pinfo)) {
169 if (in_8(&smcp->smc_smcm) & SMCM_TX)
170 return;
171 } else {
172 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
173 return;
174 }
175
176 if (cpm_uart_tx_pump(port) != 0) {
177 if (IS_SMC(pinfo)) {
178 setbits8(&smcp->smc_smcm, SMCM_TX);
179 } else {
180 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
181 }
182 }
183 }
184
185 /*
186 * Stop receiver
187 */
cpm_uart_stop_rx(struct uart_port * port)188 static void cpm_uart_stop_rx(struct uart_port *port)
189 {
190 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
191 smc_t __iomem *smcp = pinfo->smcp;
192 scc_t __iomem *sccp = pinfo->sccp;
193
194 pr_debug("CPM uart[%d]:stop rx\n", port->line);
195
196 if (IS_SMC(pinfo))
197 clrbits8(&smcp->smc_smcm, SMCM_RX);
198 else
199 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
200 }
201
202 /*
203 * Enable Modem status interrupts
204 */
cpm_uart_enable_ms(struct uart_port * port)205 static void cpm_uart_enable_ms(struct uart_port *port)
206 {
207 pr_debug("CPM uart[%d]:enable ms\n", port->line);
208 }
209
210 /*
211 * Generate a break.
212 */
cpm_uart_break_ctl(struct uart_port * port,int break_state)213 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
214 {
215 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
216
217 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
218 break_state);
219
220 if (break_state)
221 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
222 else
223 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
224 }
225
226 /*
227 * Transmit characters, refill buffer descriptor, if possible
228 */
cpm_uart_int_tx(struct uart_port * port)229 static void cpm_uart_int_tx(struct uart_port *port)
230 {
231 pr_debug("CPM uart[%d]:TX INT\n", port->line);
232
233 cpm_uart_tx_pump(port);
234 }
235
236 #ifdef CONFIG_CONSOLE_POLL
237 static int serial_polled;
238 #endif
239
240 /*
241 * Receive characters
242 */
cpm_uart_int_rx(struct uart_port * port)243 static void cpm_uart_int_rx(struct uart_port *port)
244 {
245 int i;
246 unsigned char ch;
247 u8 *cp;
248 struct tty_struct *tty = port->state->port.tty;
249 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
250 cbd_t __iomem *bdp;
251 u16 status;
252 unsigned int flg;
253
254 pr_debug("CPM uart[%d]:RX INT\n", port->line);
255
256 /* Just loop through the closed BDs and copy the characters into
257 * the buffer.
258 */
259 bdp = pinfo->rx_cur;
260 for (;;) {
261 #ifdef CONFIG_CONSOLE_POLL
262 if (unlikely(serial_polled)) {
263 serial_polled = 0;
264 return;
265 }
266 #endif
267 /* get status */
268 status = in_be16(&bdp->cbd_sc);
269 /* If this one is empty, return happy */
270 if (status & BD_SC_EMPTY)
271 break;
272
273 /* get number of characters, and check spce in flip-buffer */
274 i = in_be16(&bdp->cbd_datlen);
275
276 /* If we have not enough room in tty flip buffer, then we try
277 * later, which will be the next rx-interrupt or a timeout
278 */
279 if(tty_buffer_request_room(tty, i) < i) {
280 printk(KERN_WARNING "No room in flip buffer\n");
281 return;
282 }
283
284 /* get pointer */
285 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
286
287 /* loop through the buffer */
288 while (i-- > 0) {
289 ch = *cp++;
290 port->icount.rx++;
291 flg = TTY_NORMAL;
292
293 if (status &
294 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
295 goto handle_error;
296 if (uart_handle_sysrq_char(port, ch))
297 continue;
298 #ifdef CONFIG_CONSOLE_POLL
299 if (unlikely(serial_polled)) {
300 serial_polled = 0;
301 return;
302 }
303 #endif
304 error_return:
305 tty_insert_flip_char(tty, ch, flg);
306
307 } /* End while (i--) */
308
309 /* This BD is ready to be used again. Clear status. get next */
310 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
311 BD_SC_OV | BD_SC_ID);
312 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
313
314 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
315 bdp = pinfo->rx_bd_base;
316 else
317 bdp++;
318
319 } /* End for (;;) */
320
321 /* Write back buffer pointer */
322 pinfo->rx_cur = bdp;
323
324 /* activate BH processing */
325 tty_flip_buffer_push(tty);
326
327 return;
328
329 /* Error processing */
330
331 handle_error:
332 /* Statistics */
333 if (status & BD_SC_BR)
334 port->icount.brk++;
335 if (status & BD_SC_PR)
336 port->icount.parity++;
337 if (status & BD_SC_FR)
338 port->icount.frame++;
339 if (status & BD_SC_OV)
340 port->icount.overrun++;
341
342 /* Mask out ignored conditions */
343 status &= port->read_status_mask;
344
345 /* Handle the remaining ones */
346 if (status & BD_SC_BR)
347 flg = TTY_BREAK;
348 else if (status & BD_SC_PR)
349 flg = TTY_PARITY;
350 else if (status & BD_SC_FR)
351 flg = TTY_FRAME;
352
353 /* overrun does not affect the current character ! */
354 if (status & BD_SC_OV) {
355 ch = 0;
356 flg = TTY_OVERRUN;
357 /* We skip this buffer */
358 /* CHECK: Is really nothing senseful there */
359 /* ASSUMPTION: it contains nothing valid */
360 i = 0;
361 }
362 #ifdef SUPPORT_SYSRQ
363 port->sysrq = 0;
364 #endif
365 goto error_return;
366 }
367
368 /*
369 * Asynchron mode interrupt handler
370 */
cpm_uart_int(int irq,void * data)371 static irqreturn_t cpm_uart_int(int irq, void *data)
372 {
373 u8 events;
374 struct uart_port *port = data;
375 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
376 smc_t __iomem *smcp = pinfo->smcp;
377 scc_t __iomem *sccp = pinfo->sccp;
378
379 pr_debug("CPM uart[%d]:IRQ\n", port->line);
380
381 if (IS_SMC(pinfo)) {
382 events = in_8(&smcp->smc_smce);
383 out_8(&smcp->smc_smce, events);
384 if (events & SMCM_BRKE)
385 uart_handle_break(port);
386 if (events & SMCM_RX)
387 cpm_uart_int_rx(port);
388 if (events & SMCM_TX)
389 cpm_uart_int_tx(port);
390 } else {
391 events = in_be16(&sccp->scc_scce);
392 out_be16(&sccp->scc_scce, events);
393 if (events & UART_SCCM_BRKE)
394 uart_handle_break(port);
395 if (events & UART_SCCM_RX)
396 cpm_uart_int_rx(port);
397 if (events & UART_SCCM_TX)
398 cpm_uart_int_tx(port);
399 }
400 return (events) ? IRQ_HANDLED : IRQ_NONE;
401 }
402
cpm_uart_startup(struct uart_port * port)403 static int cpm_uart_startup(struct uart_port *port)
404 {
405 int retval;
406 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
407
408 pr_debug("CPM uart[%d]:startup\n", port->line);
409
410 /* If the port is not the console, make sure rx is disabled. */
411 if (!(pinfo->flags & FLAG_CONSOLE)) {
412 /* Disable UART rx */
413 if (IS_SMC(pinfo)) {
414 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
415 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
416 } else {
417 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
418 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
419 }
420 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
421 }
422 /* Install interrupt handler. */
423 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
424 if (retval)
425 return retval;
426
427 /* Startup rx-int */
428 if (IS_SMC(pinfo)) {
429 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
430 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
431 } else {
432 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
433 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
434 }
435
436 return 0;
437 }
438
cpm_uart_wait_until_send(struct uart_cpm_port * pinfo)439 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
440 {
441 set_current_state(TASK_UNINTERRUPTIBLE);
442 schedule_timeout(pinfo->wait_closing);
443 }
444
445 /*
446 * Shutdown the uart
447 */
cpm_uart_shutdown(struct uart_port * port)448 static void cpm_uart_shutdown(struct uart_port *port)
449 {
450 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
451
452 pr_debug("CPM uart[%d]:shutdown\n", port->line);
453
454 /* free interrupt handler */
455 free_irq(port->irq, port);
456
457 /* If the port is not the console, disable Rx and Tx. */
458 if (!(pinfo->flags & FLAG_CONSOLE)) {
459 /* Wait for all the BDs marked sent */
460 while(!cpm_uart_tx_empty(port)) {
461 set_current_state(TASK_UNINTERRUPTIBLE);
462 schedule_timeout(2);
463 }
464
465 if (pinfo->wait_closing)
466 cpm_uart_wait_until_send(pinfo);
467
468 /* Stop uarts */
469 if (IS_SMC(pinfo)) {
470 smc_t __iomem *smcp = pinfo->smcp;
471 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
472 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
473 } else {
474 scc_t __iomem *sccp = pinfo->sccp;
475 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
476 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
477 }
478
479 /* Shut them really down and reinit buffer descriptors */
480 if (IS_SMC(pinfo)) {
481 out_be16(&pinfo->smcup->smc_brkcr, 0);
482 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
483 } else {
484 out_be16(&pinfo->sccup->scc_brkcr, 0);
485 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
486 }
487
488 cpm_uart_initbd(pinfo);
489 }
490 }
491
cpm_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)492 static void cpm_uart_set_termios(struct uart_port *port,
493 struct ktermios *termios,
494 struct ktermios *old)
495 {
496 int baud;
497 unsigned long flags;
498 u16 cval, scval, prev_mode;
499 int bits, sbits;
500 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
501 smc_t __iomem *smcp = pinfo->smcp;
502 scc_t __iomem *sccp = pinfo->sccp;
503
504 pr_debug("CPM uart[%d]:set_termios\n", port->line);
505
506 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
507 if (baud <= HW_BUF_SPD_THRESHOLD ||
508 (pinfo->port.state && pinfo->port.state->port.tty->low_latency))
509 pinfo->rx_fifosize = 1;
510 else
511 pinfo->rx_fifosize = RX_BUF_SIZE;
512
513 /* Character length programmed into the mode register is the
514 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
515 * 1 or 2 stop bits, minus 1.
516 * The value 'bits' counts this for us.
517 */
518 cval = 0;
519 scval = 0;
520
521 /* byte size */
522 switch (termios->c_cflag & CSIZE) {
523 case CS5:
524 bits = 5;
525 break;
526 case CS6:
527 bits = 6;
528 break;
529 case CS7:
530 bits = 7;
531 break;
532 case CS8:
533 bits = 8;
534 break;
535 /* Never happens, but GCC is too dumb to figure it out */
536 default:
537 bits = 8;
538 break;
539 }
540 sbits = bits - 5;
541
542 if (termios->c_cflag & CSTOPB) {
543 cval |= SMCMR_SL; /* Two stops */
544 scval |= SCU_PSMR_SL;
545 bits++;
546 }
547
548 if (termios->c_cflag & PARENB) {
549 cval |= SMCMR_PEN;
550 scval |= SCU_PSMR_PEN;
551 bits++;
552 if (!(termios->c_cflag & PARODD)) {
553 cval |= SMCMR_PM_EVEN;
554 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
555 }
556 }
557
558 /*
559 * Update the timeout
560 */
561 uart_update_timeout(port, termios->c_cflag, baud);
562
563 /*
564 * Set up parity check flag
565 */
566 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
567
568 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
569 if (termios->c_iflag & INPCK)
570 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
571 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
572 port->read_status_mask |= BD_SC_BR;
573
574 /*
575 * Characters to ignore
576 */
577 port->ignore_status_mask = 0;
578 if (termios->c_iflag & IGNPAR)
579 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
580 if (termios->c_iflag & IGNBRK) {
581 port->ignore_status_mask |= BD_SC_BR;
582 /*
583 * If we're ignore parity and break indicators, ignore
584 * overruns too. (For real raw support).
585 */
586 if (termios->c_iflag & IGNPAR)
587 port->ignore_status_mask |= BD_SC_OV;
588 }
589 /*
590 * !!! ignore all characters if CREAD is not set
591 */
592 if ((termios->c_cflag & CREAD) == 0)
593 port->read_status_mask &= ~BD_SC_EMPTY;
594
595 spin_lock_irqsave(&port->lock, flags);
596
597 /* Start bit has not been added (so don't, because we would just
598 * subtract it later), and we need to add one for the number of
599 * stops bits (there is always at least one).
600 */
601 bits++;
602 if (IS_SMC(pinfo)) {
603 /*
604 * MRBLR can be changed while an SMC/SCC is operating only
605 * if it is done in a single bus cycle with one 16-bit move
606 * (not two 8-bit bus cycles back-to-back). This occurs when
607 * the cp shifts control to the next RxBD, so the change does
608 * not take effect immediately. To guarantee the exact RxBD
609 * on which the change occurs, change MRBLR only while the
610 * SMC/SCC receiver is disabled.
611 */
612 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
613
614 /* Set the mode register. We want to keep a copy of the
615 * enables, because we want to put them back if they were
616 * present.
617 */
618 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
619 /* Output in *one* operation, so we don't interrupt RX/TX if they
620 * were already enabled. */
621 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
622 SMCMR_SM_UART | prev_mode);
623 } else {
624 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
625 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
626 }
627
628 if (pinfo->clk)
629 clk_set_rate(pinfo->clk, baud);
630 else
631 cpm_set_brg(pinfo->brg - 1, baud);
632 spin_unlock_irqrestore(&port->lock, flags);
633 }
634
cpm_uart_type(struct uart_port * port)635 static const char *cpm_uart_type(struct uart_port *port)
636 {
637 pr_debug("CPM uart[%d]:uart_type\n", port->line);
638
639 return port->type == PORT_CPM ? "CPM UART" : NULL;
640 }
641
642 /*
643 * verify the new serial_struct (for TIOCSSERIAL).
644 */
cpm_uart_verify_port(struct uart_port * port,struct serial_struct * ser)645 static int cpm_uart_verify_port(struct uart_port *port,
646 struct serial_struct *ser)
647 {
648 int ret = 0;
649
650 pr_debug("CPM uart[%d]:verify_port\n", port->line);
651
652 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
653 ret = -EINVAL;
654 if (ser->irq < 0 || ser->irq >= nr_irqs)
655 ret = -EINVAL;
656 if (ser->baud_base < 9600)
657 ret = -EINVAL;
658 return ret;
659 }
660
661 /*
662 * Transmit characters, refill buffer descriptor, if possible
663 */
cpm_uart_tx_pump(struct uart_port * port)664 static int cpm_uart_tx_pump(struct uart_port *port)
665 {
666 cbd_t __iomem *bdp;
667 u8 *p;
668 int count;
669 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
670 struct circ_buf *xmit = &port->state->xmit;
671
672 /* Handle xon/xoff */
673 if (port->x_char) {
674 /* Pick next descriptor and fill from buffer */
675 bdp = pinfo->tx_cur;
676
677 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
678
679 *p++ = port->x_char;
680
681 out_be16(&bdp->cbd_datlen, 1);
682 setbits16(&bdp->cbd_sc, BD_SC_READY);
683 /* Get next BD. */
684 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
685 bdp = pinfo->tx_bd_base;
686 else
687 bdp++;
688 pinfo->tx_cur = bdp;
689
690 port->icount.tx++;
691 port->x_char = 0;
692 return 1;
693 }
694
695 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
696 cpm_uart_stop_tx(port);
697 return 0;
698 }
699
700 /* Pick next descriptor and fill from buffer */
701 bdp = pinfo->tx_cur;
702
703 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
704 xmit->tail != xmit->head) {
705 count = 0;
706 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
707 while (count < pinfo->tx_fifosize) {
708 *p++ = xmit->buf[xmit->tail];
709 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
710 port->icount.tx++;
711 count++;
712 if (xmit->head == xmit->tail)
713 break;
714 }
715 out_be16(&bdp->cbd_datlen, count);
716 setbits16(&bdp->cbd_sc, BD_SC_READY);
717 /* Get next BD. */
718 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
719 bdp = pinfo->tx_bd_base;
720 else
721 bdp++;
722 }
723 pinfo->tx_cur = bdp;
724
725 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
726 uart_write_wakeup(port);
727
728 if (uart_circ_empty(xmit)) {
729 cpm_uart_stop_tx(port);
730 return 0;
731 }
732
733 return 1;
734 }
735
736 /*
737 * init buffer descriptors
738 */
cpm_uart_initbd(struct uart_cpm_port * pinfo)739 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
740 {
741 int i;
742 u8 *mem_addr;
743 cbd_t __iomem *bdp;
744
745 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
746
747 /* Set the physical address of the host memory
748 * buffers in the buffer descriptors, and the
749 * virtual address for us to work with.
750 */
751 mem_addr = pinfo->mem_addr;
752 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
753 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
754 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
755 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
756 mem_addr += pinfo->rx_fifosize;
757 }
758
759 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
760 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
761
762 /* Set the physical address of the host memory
763 * buffers in the buffer descriptors, and the
764 * virtual address for us to work with.
765 */
766 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
767 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
768 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
769 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
770 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
771 mem_addr += pinfo->tx_fifosize;
772 }
773
774 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
775 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
776 }
777
cpm_uart_init_scc(struct uart_cpm_port * pinfo)778 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
779 {
780 scc_t __iomem *scp;
781 scc_uart_t __iomem *sup;
782
783 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
784
785 scp = pinfo->sccp;
786 sup = pinfo->sccup;
787
788 /* Store address */
789 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
790 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
791 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
792 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
793
794 /* Set up the uart parameters in the
795 * parameter ram.
796 */
797
798 cpm_set_scc_fcr(sup);
799
800 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
801 out_be16(&sup->scc_maxidl, pinfo->rx_fifosize);
802 out_be16(&sup->scc_brkcr, 1);
803 out_be16(&sup->scc_parec, 0);
804 out_be16(&sup->scc_frmec, 0);
805 out_be16(&sup->scc_nosec, 0);
806 out_be16(&sup->scc_brkec, 0);
807 out_be16(&sup->scc_uaddr1, 0);
808 out_be16(&sup->scc_uaddr2, 0);
809 out_be16(&sup->scc_toseq, 0);
810 out_be16(&sup->scc_char1, 0x8000);
811 out_be16(&sup->scc_char2, 0x8000);
812 out_be16(&sup->scc_char3, 0x8000);
813 out_be16(&sup->scc_char4, 0x8000);
814 out_be16(&sup->scc_char5, 0x8000);
815 out_be16(&sup->scc_char6, 0x8000);
816 out_be16(&sup->scc_char7, 0x8000);
817 out_be16(&sup->scc_char8, 0x8000);
818 out_be16(&sup->scc_rccm, 0xc0ff);
819
820 /* Send the CPM an initialize command.
821 */
822 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
823
824 /* Set UART mode, 8 bit, no parity, one stop.
825 * Enable receive and transmit.
826 */
827 out_be32(&scp->scc_gsmrh, 0);
828 out_be32(&scp->scc_gsmrl,
829 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
830
831 /* Enable rx interrupts and clear all pending events. */
832 out_be16(&scp->scc_sccm, 0);
833 out_be16(&scp->scc_scce, 0xffff);
834 out_be16(&scp->scc_dsr, 0x7e7e);
835 out_be16(&scp->scc_psmr, 0x3000);
836
837 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
838 }
839
cpm_uart_init_smc(struct uart_cpm_port * pinfo)840 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
841 {
842 smc_t __iomem *sp;
843 smc_uart_t __iomem *up;
844
845 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
846
847 sp = pinfo->smcp;
848 up = pinfo->smcup;
849
850 /* Store address */
851 out_be16(&pinfo->smcup->smc_rbase,
852 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
853 out_be16(&pinfo->smcup->smc_tbase,
854 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
855
856 /*
857 * In case SMC1 is being relocated...
858 */
859 #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
860 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
861 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
862 out_be32(&up->smc_rstate, 0);
863 out_be32(&up->smc_tstate, 0);
864 out_be16(&up->smc_brkcr, 1); /* number of break chars */
865 out_be16(&up->smc_brkec, 0);
866 #endif
867
868 /* Set up the uart parameters in the
869 * parameter ram.
870 */
871 cpm_set_smc_fcr(up);
872
873 /* Using idle character time requires some additional tuning. */
874 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
875 out_be16(&up->smc_maxidl, pinfo->rx_fifosize);
876 out_be16(&up->smc_brklen, 0);
877 out_be16(&up->smc_brkec, 0);
878 out_be16(&up->smc_brkcr, 1);
879
880 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
881
882 /* Set UART mode, 8 bit, no parity, one stop.
883 * Enable receive and transmit.
884 */
885 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
886
887 /* Enable only rx interrupts clear all pending events. */
888 out_8(&sp->smc_smcm, 0);
889 out_8(&sp->smc_smce, 0xff);
890
891 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
892 }
893
894 /*
895 * Initialize port. This is called from early_console stuff
896 * so we have to be careful here !
897 */
cpm_uart_request_port(struct uart_port * port)898 static int cpm_uart_request_port(struct uart_port *port)
899 {
900 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
901 int ret;
902
903 pr_debug("CPM uart[%d]:request port\n", port->line);
904
905 if (pinfo->flags & FLAG_CONSOLE)
906 return 0;
907
908 if (IS_SMC(pinfo)) {
909 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
910 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
911 } else {
912 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
913 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
914 }
915
916 ret = cpm_uart_allocbuf(pinfo, 0);
917
918 if (ret)
919 return ret;
920
921 cpm_uart_initbd(pinfo);
922 if (IS_SMC(pinfo))
923 cpm_uart_init_smc(pinfo);
924 else
925 cpm_uart_init_scc(pinfo);
926
927 return 0;
928 }
929
cpm_uart_release_port(struct uart_port * port)930 static void cpm_uart_release_port(struct uart_port *port)
931 {
932 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
933
934 if (!(pinfo->flags & FLAG_CONSOLE))
935 cpm_uart_freebuf(pinfo);
936 }
937
938 /*
939 * Configure/autoconfigure the port.
940 */
cpm_uart_config_port(struct uart_port * port,int flags)941 static void cpm_uart_config_port(struct uart_port *port, int flags)
942 {
943 pr_debug("CPM uart[%d]:config_port\n", port->line);
944
945 if (flags & UART_CONFIG_TYPE) {
946 port->type = PORT_CPM;
947 cpm_uart_request_port(port);
948 }
949 }
950
951 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
952 /*
953 * Write a string to the serial port
954 * Note that this is called with interrupts already disabled
955 */
cpm_uart_early_write(struct uart_cpm_port * pinfo,const char * string,u_int count)956 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
957 const char *string, u_int count)
958 {
959 unsigned int i;
960 cbd_t __iomem *bdp, *bdbase;
961 unsigned char *cpm_outp_addr;
962
963 /* Get the address of the host memory buffer.
964 */
965 bdp = pinfo->tx_cur;
966 bdbase = pinfo->tx_bd_base;
967
968 /*
969 * Now, do each character. This is not as bad as it looks
970 * since this is a holding FIFO and not a transmitting FIFO.
971 * We could add the complexity of filling the entire transmit
972 * buffer, but we would just wait longer between accesses......
973 */
974 for (i = 0; i < count; i++, string++) {
975 /* Wait for transmitter fifo to empty.
976 * Ready indicates output is ready, and xmt is doing
977 * that, not that it is ready for us to send.
978 */
979 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
980 ;
981
982 /* Send the character out.
983 * If the buffer address is in the CPM DPRAM, don't
984 * convert it.
985 */
986 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
987 pinfo);
988 *cpm_outp_addr = *string;
989
990 out_be16(&bdp->cbd_datlen, 1);
991 setbits16(&bdp->cbd_sc, BD_SC_READY);
992
993 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
994 bdp = bdbase;
995 else
996 bdp++;
997
998 /* if a LF, also do CR... */
999 if (*string == 10) {
1000 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1001 ;
1002
1003 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1004 pinfo);
1005 *cpm_outp_addr = 13;
1006
1007 out_be16(&bdp->cbd_datlen, 1);
1008 setbits16(&bdp->cbd_sc, BD_SC_READY);
1009
1010 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1011 bdp = bdbase;
1012 else
1013 bdp++;
1014 }
1015 }
1016
1017 /*
1018 * Finally, Wait for transmitter & holding register to empty
1019 * and restore the IER
1020 */
1021 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1022 ;
1023
1024 pinfo->tx_cur = bdp;
1025 }
1026 #endif
1027
1028 #ifdef CONFIG_CONSOLE_POLL
1029 /* Serial polling routines for writing and reading from the uart while
1030 * in an interrupt or debug context.
1031 */
1032
1033 #define GDB_BUF_SIZE 512 /* power of 2, please */
1034
1035 static char poll_buf[GDB_BUF_SIZE];
1036 static char *pollp;
1037 static int poll_chars;
1038
poll_wait_key(char * obuf,struct uart_cpm_port * pinfo)1039 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1040 {
1041 u_char c, *cp;
1042 volatile cbd_t *bdp;
1043 int i;
1044
1045 /* Get the address of the host memory buffer.
1046 */
1047 bdp = pinfo->rx_cur;
1048 while (bdp->cbd_sc & BD_SC_EMPTY)
1049 ;
1050
1051 /* If the buffer address is in the CPM DPRAM, don't
1052 * convert it.
1053 */
1054 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1055
1056 if (obuf) {
1057 i = c = bdp->cbd_datlen;
1058 while (i-- > 0)
1059 *obuf++ = *cp++;
1060 } else
1061 c = *cp;
1062 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1063 bdp->cbd_sc |= BD_SC_EMPTY;
1064
1065 if (bdp->cbd_sc & BD_SC_WRAP)
1066 bdp = pinfo->rx_bd_base;
1067 else
1068 bdp++;
1069 pinfo->rx_cur = (cbd_t *)bdp;
1070
1071 return (int)c;
1072 }
1073
cpm_get_poll_char(struct uart_port * port)1074 static int cpm_get_poll_char(struct uart_port *port)
1075 {
1076 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1077
1078 if (!serial_polled) {
1079 serial_polled = 1;
1080 poll_chars = 0;
1081 }
1082 if (poll_chars <= 0) {
1083 poll_chars = poll_wait_key(poll_buf, pinfo);
1084 pollp = poll_buf;
1085 }
1086 poll_chars--;
1087 return *pollp++;
1088 }
1089
cpm_put_poll_char(struct uart_port * port,unsigned char c)1090 static void cpm_put_poll_char(struct uart_port *port,
1091 unsigned char c)
1092 {
1093 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1094 static char ch[2];
1095
1096 ch[0] = (char)c;
1097 cpm_uart_early_write(pinfo, ch, 1);
1098 }
1099 #endif /* CONFIG_CONSOLE_POLL */
1100
1101 static struct uart_ops cpm_uart_pops = {
1102 .tx_empty = cpm_uart_tx_empty,
1103 .set_mctrl = cpm_uart_set_mctrl,
1104 .get_mctrl = cpm_uart_get_mctrl,
1105 .stop_tx = cpm_uart_stop_tx,
1106 .start_tx = cpm_uart_start_tx,
1107 .stop_rx = cpm_uart_stop_rx,
1108 .enable_ms = cpm_uart_enable_ms,
1109 .break_ctl = cpm_uart_break_ctl,
1110 .startup = cpm_uart_startup,
1111 .shutdown = cpm_uart_shutdown,
1112 .set_termios = cpm_uart_set_termios,
1113 .type = cpm_uart_type,
1114 .release_port = cpm_uart_release_port,
1115 .request_port = cpm_uart_request_port,
1116 .config_port = cpm_uart_config_port,
1117 .verify_port = cpm_uart_verify_port,
1118 #ifdef CONFIG_CONSOLE_POLL
1119 .poll_get_char = cpm_get_poll_char,
1120 .poll_put_char = cpm_put_poll_char,
1121 #endif
1122 };
1123
1124 struct uart_cpm_port cpm_uart_ports[UART_NR];
1125
cpm_uart_init_port(struct device_node * np,struct uart_cpm_port * pinfo)1126 static int cpm_uart_init_port(struct device_node *np,
1127 struct uart_cpm_port *pinfo)
1128 {
1129 const u32 *data;
1130 void __iomem *mem, *pram;
1131 int len;
1132 int ret;
1133 int i;
1134
1135 data = of_get_property(np, "clock", NULL);
1136 if (data) {
1137 struct clk *clk = clk_get(NULL, (const char*)data);
1138 if (!IS_ERR(clk))
1139 pinfo->clk = clk;
1140 }
1141 if (!pinfo->clk) {
1142 data = of_get_property(np, "fsl,cpm-brg", &len);
1143 if (!data || len != 4) {
1144 printk(KERN_ERR "CPM UART %s has no/invalid "
1145 "fsl,cpm-brg property.\n", np->name);
1146 return -EINVAL;
1147 }
1148 pinfo->brg = *data;
1149 }
1150
1151 data = of_get_property(np, "fsl,cpm-command", &len);
1152 if (!data || len != 4) {
1153 printk(KERN_ERR "CPM UART %s has no/invalid "
1154 "fsl,cpm-command property.\n", np->name);
1155 return -EINVAL;
1156 }
1157 pinfo->command = *data;
1158
1159 mem = of_iomap(np, 0);
1160 if (!mem)
1161 return -ENOMEM;
1162
1163 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1164 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1165 pinfo->sccp = mem;
1166 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1167 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1168 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1169 pinfo->flags |= FLAG_SMC;
1170 pinfo->smcp = mem;
1171 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1172 } else {
1173 ret = -ENODEV;
1174 goto out_mem;
1175 }
1176
1177 if (!pram) {
1178 ret = -ENOMEM;
1179 goto out_mem;
1180 }
1181
1182 pinfo->tx_nrfifos = TX_NUM_FIFO;
1183 pinfo->tx_fifosize = TX_BUF_SIZE;
1184 pinfo->rx_nrfifos = RX_NUM_FIFO;
1185 pinfo->rx_fifosize = RX_BUF_SIZE;
1186
1187 pinfo->port.uartclk = ppc_proc_freq;
1188 pinfo->port.mapbase = (unsigned long)mem;
1189 pinfo->port.type = PORT_CPM;
1190 pinfo->port.ops = &cpm_uart_pops,
1191 pinfo->port.iotype = UPIO_MEM;
1192 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1193 spin_lock_init(&pinfo->port.lock);
1194
1195 pinfo->port.irq = of_irq_to_resource(np, 0, NULL);
1196 if (pinfo->port.irq == NO_IRQ) {
1197 ret = -EINVAL;
1198 goto out_pram;
1199 }
1200
1201 for (i = 0; i < NUM_GPIOS; i++)
1202 pinfo->gpios[i] = of_get_gpio(np, i);
1203
1204 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1205 udbg_putc = NULL;
1206 #endif
1207
1208 return cpm_uart_request_port(&pinfo->port);
1209
1210 out_pram:
1211 cpm_uart_unmap_pram(pinfo, pram);
1212 out_mem:
1213 iounmap(mem);
1214 return ret;
1215 }
1216
1217 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1218 /*
1219 * Print a string to the serial port trying not to disturb
1220 * any possible real use of the port...
1221 *
1222 * Note that this is called with interrupts already disabled
1223 */
cpm_uart_console_write(struct console * co,const char * s,u_int count)1224 static void cpm_uart_console_write(struct console *co, const char *s,
1225 u_int count)
1226 {
1227 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1228 unsigned long flags;
1229 int nolock = oops_in_progress;
1230
1231 if (unlikely(nolock)) {
1232 local_irq_save(flags);
1233 } else {
1234 spin_lock_irqsave(&pinfo->port.lock, flags);
1235 }
1236
1237 cpm_uart_early_write(pinfo, s, count);
1238
1239 if (unlikely(nolock)) {
1240 local_irq_restore(flags);
1241 } else {
1242 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1243 }
1244 }
1245
1246
cpm_uart_console_setup(struct console * co,char * options)1247 static int __init cpm_uart_console_setup(struct console *co, char *options)
1248 {
1249 int baud = 38400;
1250 int bits = 8;
1251 int parity = 'n';
1252 int flow = 'n';
1253 int ret;
1254 struct uart_cpm_port *pinfo;
1255 struct uart_port *port;
1256
1257 struct device_node *np = NULL;
1258 int i = 0;
1259
1260 if (co->index >= UART_NR) {
1261 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1262 co->index);
1263 return -ENODEV;
1264 }
1265
1266 do {
1267 np = of_find_node_by_type(np, "serial");
1268 if (!np)
1269 return -ENODEV;
1270
1271 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1272 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1273 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1274 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1275 i--;
1276 } while (i++ != co->index);
1277
1278 pinfo = &cpm_uart_ports[co->index];
1279
1280 pinfo->flags |= FLAG_CONSOLE;
1281 port = &pinfo->port;
1282
1283 ret = cpm_uart_init_port(np, pinfo);
1284 of_node_put(np);
1285 if (ret)
1286 return ret;
1287
1288 if (options) {
1289 uart_parse_options(options, &baud, &parity, &bits, &flow);
1290 } else {
1291 if ((baud = uart_baudrate()) == -1)
1292 baud = 9600;
1293 }
1294
1295 if (IS_SMC(pinfo)) {
1296 out_be16(&pinfo->smcup->smc_brkcr, 0);
1297 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1298 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1299 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1300 } else {
1301 out_be16(&pinfo->sccup->scc_brkcr, 0);
1302 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1303 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1304 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1305 }
1306
1307 ret = cpm_uart_allocbuf(pinfo, 1);
1308
1309 if (ret)
1310 return ret;
1311
1312 cpm_uart_initbd(pinfo);
1313
1314 if (IS_SMC(pinfo))
1315 cpm_uart_init_smc(pinfo);
1316 else
1317 cpm_uart_init_scc(pinfo);
1318
1319 uart_set_options(port, co, baud, parity, bits, flow);
1320 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1321
1322 return 0;
1323 }
1324
1325 static struct uart_driver cpm_reg;
1326 static struct console cpm_scc_uart_console = {
1327 .name = "ttyCPM",
1328 .write = cpm_uart_console_write,
1329 .device = uart_console_device,
1330 .setup = cpm_uart_console_setup,
1331 .flags = CON_PRINTBUFFER,
1332 .index = -1,
1333 .data = &cpm_reg,
1334 };
1335
cpm_uart_console_init(void)1336 static int __init cpm_uart_console_init(void)
1337 {
1338 register_console(&cpm_scc_uart_console);
1339 return 0;
1340 }
1341
1342 console_initcall(cpm_uart_console_init);
1343
1344 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1345 #else
1346 #define CPM_UART_CONSOLE NULL
1347 #endif
1348
1349 static struct uart_driver cpm_reg = {
1350 .owner = THIS_MODULE,
1351 .driver_name = "ttyCPM",
1352 .dev_name = "ttyCPM",
1353 .major = SERIAL_CPM_MAJOR,
1354 .minor = SERIAL_CPM_MINOR,
1355 .cons = CPM_UART_CONSOLE,
1356 .nr = UART_NR,
1357 };
1358
1359 static int probe_index;
1360
cpm_uart_probe(struct platform_device * ofdev)1361 static int __devinit cpm_uart_probe(struct platform_device *ofdev)
1362 {
1363 int index = probe_index++;
1364 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1365 int ret;
1366
1367 pinfo->port.line = index;
1368
1369 if (index >= UART_NR)
1370 return -ENODEV;
1371
1372 dev_set_drvdata(&ofdev->dev, pinfo);
1373
1374 /* initialize the device pointer for the port */
1375 pinfo->port.dev = &ofdev->dev;
1376
1377 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1378 if (ret)
1379 return ret;
1380
1381 return uart_add_one_port(&cpm_reg, &pinfo->port);
1382 }
1383
cpm_uart_remove(struct platform_device * ofdev)1384 static int __devexit cpm_uart_remove(struct platform_device *ofdev)
1385 {
1386 struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev);
1387 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1388 }
1389
1390 static struct of_device_id cpm_uart_match[] = {
1391 {
1392 .compatible = "fsl,cpm1-smc-uart",
1393 },
1394 {
1395 .compatible = "fsl,cpm1-scc-uart",
1396 },
1397 {
1398 .compatible = "fsl,cpm2-smc-uart",
1399 },
1400 {
1401 .compatible = "fsl,cpm2-scc-uart",
1402 },
1403 {}
1404 };
1405
1406 static struct platform_driver cpm_uart_driver = {
1407 .driver = {
1408 .name = "cpm_uart",
1409 .owner = THIS_MODULE,
1410 .of_match_table = cpm_uart_match,
1411 },
1412 .probe = cpm_uart_probe,
1413 .remove = cpm_uart_remove,
1414 };
1415
cpm_uart_init(void)1416 static int __init cpm_uart_init(void)
1417 {
1418 int ret = uart_register_driver(&cpm_reg);
1419 if (ret)
1420 return ret;
1421
1422 ret = platform_driver_register(&cpm_uart_driver);
1423 if (ret)
1424 uart_unregister_driver(&cpm_reg);
1425
1426 return ret;
1427 }
1428
cpm_uart_exit(void)1429 static void __exit cpm_uart_exit(void)
1430 {
1431 platform_driver_unregister(&cpm_uart_driver);
1432 uart_unregister_driver(&cpm_reg);
1433 }
1434
1435 module_init(cpm_uart_init);
1436 module_exit(cpm_uart_exit);
1437
1438 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1439 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1440 MODULE_LICENSE("GPL");
1441 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1442