1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/etherdevice.h>
36 #include <linux/vmalloc.h>
37 #include <linux/usb.h>
38 #include <net/mac80211.h>
39 #include "debug.h"
40
41 #define RF_CHANGE_BY_INIT 0
42 #define RF_CHANGE_BY_IPS BIT(28)
43 #define RF_CHANGE_BY_PS BIT(29)
44 #define RF_CHANGE_BY_HW BIT(30)
45 #define RF_CHANGE_BY_SW BIT(31)
46
47 #define IQK_ADDA_REG_NUM 16
48 #define IQK_MAC_REG_NUM 4
49
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
52
53 /* QoS related. */
54 /*aci: 0x00 Best Effort*/
55 /*aci: 0x01 Background*/
56 /*aci: 0x10 Video*/
57 /*aci: 0x11 Voice*/
58 /*Max: define total number.*/
59 #define AC0_BE 0
60 #define AC1_BK 1
61 #define AC2_VI 2
62 #define AC3_VO 3
63 #define AC_MAX 4
64 #define QOS_QUEUE_NUM 4
65 #define RTL_MAC80211_NUM_QUEUE 5
66 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
67
68 #define QBSS_LOAD_SIZE 5
69 #define MAX_WMMELE_LENGTH 64
70
71 #define TOTAL_CAM_ENTRY 32
72
73 /*slot time for 11g. */
74 #define RTL_SLOT_TIME_9 9
75 #define RTL_SLOT_TIME_20 20
76
77 /*related with tcp/ip. */
78 /*if_ehther.h*/
79 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
80 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
81 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
82 #define SNAP_SIZE 6
83 #define PROTOC_TYPE_SIZE 2
84
85 /*related with 802.11 frame*/
86 #define MAC80211_3ADDR_LEN 24
87 #define MAC80211_4ADDR_LEN 30
88
89 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
90 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
91 #define MAX_PG_GROUP 13
92 #define CHANNEL_GROUP_MAX_2G 3
93 #define CHANNEL_GROUP_IDX_5GL 3
94 #define CHANNEL_GROUP_IDX_5GM 6
95 #define CHANNEL_GROUP_IDX_5GH 9
96 #define CHANNEL_GROUP_MAX_5G 9
97 #define CHANNEL_MAX_NUMBER_2G 14
98 #define AVG_THERMAL_NUM 8
99 #define MAX_TID_COUNT 9
100
101 /* for early mode */
102 #define FCS_LEN 4
103 #define EM_HDR_LEN 8
104 enum intf_type {
105 INTF_PCI = 0,
106 INTF_USB = 1,
107 };
108
109 enum radio_path {
110 RF90_PATH_A = 0,
111 RF90_PATH_B = 1,
112 RF90_PATH_C = 2,
113 RF90_PATH_D = 3,
114 };
115
116 enum rt_eeprom_type {
117 EEPROM_93C46,
118 EEPROM_93C56,
119 EEPROM_BOOT_EFUSE,
120 };
121
122 enum rtl_status {
123 RTL_STATUS_INTERFACE_START = 0,
124 };
125
126 enum hardware_type {
127 HARDWARE_TYPE_RTL8192E,
128 HARDWARE_TYPE_RTL8192U,
129 HARDWARE_TYPE_RTL8192SE,
130 HARDWARE_TYPE_RTL8192SU,
131 HARDWARE_TYPE_RTL8192CE,
132 HARDWARE_TYPE_RTL8192CU,
133 HARDWARE_TYPE_RTL8192DE,
134 HARDWARE_TYPE_RTL8192DU,
135 HARDWARE_TYPE_RTL8723E,
136 HARDWARE_TYPE_RTL8723U,
137
138 /* keep it last */
139 HARDWARE_TYPE_NUM
140 };
141
142 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
143 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
144 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
145 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
146 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
147 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
148 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
149 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
150 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
151 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
152 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
153 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
154 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
155 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
156 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
157 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
158 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
159 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
160 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
161 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
162 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
163 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
164 #define IS_HARDWARE_TYPE_8723(rtlhal) \
165 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
166 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
167 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
168
169 #define RX_HAL_IS_CCK_RATE(_pdesc)\
170 (_pdesc->rxmcs == DESC92_RATE1M || \
171 _pdesc->rxmcs == DESC92_RATE2M || \
172 _pdesc->rxmcs == DESC92_RATE5_5M || \
173 _pdesc->rxmcs == DESC92_RATE11M)
174
175 enum scan_operation_backup_opt {
176 SCAN_OPT_BACKUP = 0,
177 SCAN_OPT_RESTORE,
178 SCAN_OPT_MAX
179 };
180
181 /*RF state.*/
182 enum rf_pwrstate {
183 ERFON,
184 ERFSLEEP,
185 ERFOFF
186 };
187
188 struct bb_reg_def {
189 u32 rfintfs;
190 u32 rfintfi;
191 u32 rfintfo;
192 u32 rfintfe;
193 u32 rf3wire_offset;
194 u32 rflssi_select;
195 u32 rftxgain_stage;
196 u32 rfhssi_para1;
197 u32 rfhssi_para2;
198 u32 rfswitch_control;
199 u32 rfagc_control1;
200 u32 rfagc_control2;
201 u32 rfrxiq_imbalance;
202 u32 rfrx_afe;
203 u32 rftxiq_imbalance;
204 u32 rftx_afe;
205 u32 rflssi_readback;
206 u32 rflssi_readbackpi;
207 };
208
209 enum io_type {
210 IO_CMD_PAUSE_DM_BY_SCAN = 0,
211 IO_CMD_RESUME_DM_BY_SCAN = 1,
212 };
213
214 enum hw_variables {
215 HW_VAR_ETHER_ADDR,
216 HW_VAR_MULTICAST_REG,
217 HW_VAR_BASIC_RATE,
218 HW_VAR_BSSID,
219 HW_VAR_MEDIA_STATUS,
220 HW_VAR_SECURITY_CONF,
221 HW_VAR_BEACON_INTERVAL,
222 HW_VAR_ATIM_WINDOW,
223 HW_VAR_LISTEN_INTERVAL,
224 HW_VAR_CS_COUNTER,
225 HW_VAR_DEFAULTKEY0,
226 HW_VAR_DEFAULTKEY1,
227 HW_VAR_DEFAULTKEY2,
228 HW_VAR_DEFAULTKEY3,
229 HW_VAR_SIFS,
230 HW_VAR_DIFS,
231 HW_VAR_EIFS,
232 HW_VAR_SLOT_TIME,
233 HW_VAR_ACK_PREAMBLE,
234 HW_VAR_CW_CONFIG,
235 HW_VAR_CW_VALUES,
236 HW_VAR_RATE_FALLBACK_CONTROL,
237 HW_VAR_CONTENTION_WINDOW,
238 HW_VAR_RETRY_COUNT,
239 HW_VAR_TR_SWITCH,
240 HW_VAR_COMMAND,
241 HW_VAR_WPA_CONFIG,
242 HW_VAR_AMPDU_MIN_SPACE,
243 HW_VAR_SHORTGI_DENSITY,
244 HW_VAR_AMPDU_FACTOR,
245 HW_VAR_MCS_RATE_AVAILABLE,
246 HW_VAR_AC_PARAM,
247 HW_VAR_ACM_CTRL,
248 HW_VAR_DIS_Req_Qsize,
249 HW_VAR_CCX_CHNL_LOAD,
250 HW_VAR_CCX_NOISE_HISTOGRAM,
251 HW_VAR_CCX_CLM_NHM,
252 HW_VAR_TxOPLimit,
253 HW_VAR_TURBO_MODE,
254 HW_VAR_RF_STATE,
255 HW_VAR_RF_OFF_BY_HW,
256 HW_VAR_BUS_SPEED,
257 HW_VAR_SET_DEV_POWER,
258
259 HW_VAR_RCR,
260 HW_VAR_RATR_0,
261 HW_VAR_RRSR,
262 HW_VAR_CPU_RST,
263 HW_VAR_CECHK_BSSID,
264 HW_VAR_LBK_MODE,
265 HW_VAR_AES_11N_FIX,
266 HW_VAR_USB_RX_AGGR,
267 HW_VAR_USER_CONTROL_TURBO_MODE,
268 HW_VAR_RETRY_LIMIT,
269 HW_VAR_INIT_TX_RATE,
270 HW_VAR_TX_RATE_REG,
271 HW_VAR_EFUSE_USAGE,
272 HW_VAR_EFUSE_BYTES,
273 HW_VAR_AUTOLOAD_STATUS,
274 HW_VAR_RF_2R_DISABLE,
275 HW_VAR_SET_RPWM,
276 HW_VAR_H2C_FW_PWRMODE,
277 HW_VAR_H2C_FW_JOINBSSRPT,
278 HW_VAR_FW_PSMODE_STATUS,
279 HW_VAR_1X1_RECV_COMBINE,
280 HW_VAR_STOP_SEND_BEACON,
281 HW_VAR_TSF_TIMER,
282 HW_VAR_IO_CMD,
283
284 HW_VAR_RF_RECOVERY,
285 HW_VAR_H2C_FW_UPDATE_GTK,
286 HW_VAR_WF_MASK,
287 HW_VAR_WF_CRC,
288 HW_VAR_WF_IS_MAC_ADDR,
289 HW_VAR_H2C_FW_OFFLOAD,
290 HW_VAR_RESET_WFCRC,
291
292 HW_VAR_HANDLE_FW_C2H,
293 HW_VAR_DL_FW_RSVD_PAGE,
294 HW_VAR_AID,
295 HW_VAR_HW_SEQ_ENABLE,
296 HW_VAR_CORRECT_TSF,
297 HW_VAR_BCN_VALID,
298 HW_VAR_FWLPS_RF_ON,
299 HW_VAR_DUAL_TSF_RST,
300 HW_VAR_SWITCH_EPHY_WoWLAN,
301 HW_VAR_INT_MIGRATION,
302 HW_VAR_INT_AC,
303 HW_VAR_RF_TIMING,
304
305 HW_VAR_MRC,
306
307 HW_VAR_MGT_FILTER,
308 HW_VAR_CTRL_FILTER,
309 HW_VAR_DATA_FILTER,
310 };
311
312 enum _RT_MEDIA_STATUS {
313 RT_MEDIA_DISCONNECT = 0,
314 RT_MEDIA_CONNECT = 1
315 };
316
317 enum rt_oem_id {
318 RT_CID_DEFAULT = 0,
319 RT_CID_8187_ALPHA0 = 1,
320 RT_CID_8187_SERCOMM_PS = 2,
321 RT_CID_8187_HW_LED = 3,
322 RT_CID_8187_NETGEAR = 4,
323 RT_CID_WHQL = 5,
324 RT_CID_819x_CAMEO = 6,
325 RT_CID_819x_RUNTOP = 7,
326 RT_CID_819x_Senao = 8,
327 RT_CID_TOSHIBA = 9,
328 RT_CID_819x_Netcore = 10,
329 RT_CID_Nettronix = 11,
330 RT_CID_DLINK = 12,
331 RT_CID_PRONET = 13,
332 RT_CID_COREGA = 14,
333 RT_CID_819x_ALPHA = 15,
334 RT_CID_819x_Sitecom = 16,
335 RT_CID_CCX = 17,
336 RT_CID_819x_Lenovo = 18,
337 RT_CID_819x_QMI = 19,
338 RT_CID_819x_Edimax_Belkin = 20,
339 RT_CID_819x_Sercomm_Belkin = 21,
340 RT_CID_819x_CAMEO1 = 22,
341 RT_CID_819x_MSI = 23,
342 RT_CID_819x_Acer = 24,
343 RT_CID_819x_HP = 27,
344 RT_CID_819x_CLEVO = 28,
345 RT_CID_819x_Arcadyan_Belkin = 29,
346 RT_CID_819x_SAMSUNG = 30,
347 RT_CID_819x_WNC_COREGA = 31,
348 RT_CID_819x_Foxcoon = 32,
349 RT_CID_819x_DELL = 33,
350 };
351
352 enum hw_descs {
353 HW_DESC_OWN,
354 HW_DESC_RXOWN,
355 HW_DESC_TX_NEXTDESC_ADDR,
356 HW_DESC_TXBUFF_ADDR,
357 HW_DESC_RXBUFF_ADDR,
358 HW_DESC_RXPKT_LEN,
359 HW_DESC_RXERO,
360 };
361
362 enum prime_sc {
363 PRIME_CHNL_OFFSET_DONT_CARE = 0,
364 PRIME_CHNL_OFFSET_LOWER = 1,
365 PRIME_CHNL_OFFSET_UPPER = 2,
366 };
367
368 enum rf_type {
369 RF_1T1R = 0,
370 RF_1T2R = 1,
371 RF_2T2R = 2,
372 RF_2T2R_GREEN = 3,
373 };
374
375 enum ht_channel_width {
376 HT_CHANNEL_WIDTH_20 = 0,
377 HT_CHANNEL_WIDTH_20_40 = 1,
378 };
379
380 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
381 Cipher Suites Encryption Algorithms */
382 enum rt_enc_alg {
383 NO_ENCRYPTION = 0,
384 WEP40_ENCRYPTION = 1,
385 TKIP_ENCRYPTION = 2,
386 RSERVED_ENCRYPTION = 3,
387 AESCCMP_ENCRYPTION = 4,
388 WEP104_ENCRYPTION = 5,
389 };
390
391 enum rtl_hal_state {
392 _HAL_STATE_STOP = 0,
393 _HAL_STATE_START = 1,
394 };
395
396 enum rtl_desc92_rate {
397 DESC92_RATE1M = 0x00,
398 DESC92_RATE2M = 0x01,
399 DESC92_RATE5_5M = 0x02,
400 DESC92_RATE11M = 0x03,
401
402 DESC92_RATE6M = 0x04,
403 DESC92_RATE9M = 0x05,
404 DESC92_RATE12M = 0x06,
405 DESC92_RATE18M = 0x07,
406 DESC92_RATE24M = 0x08,
407 DESC92_RATE36M = 0x09,
408 DESC92_RATE48M = 0x0a,
409 DESC92_RATE54M = 0x0b,
410
411 DESC92_RATEMCS0 = 0x0c,
412 DESC92_RATEMCS1 = 0x0d,
413 DESC92_RATEMCS2 = 0x0e,
414 DESC92_RATEMCS3 = 0x0f,
415 DESC92_RATEMCS4 = 0x10,
416 DESC92_RATEMCS5 = 0x11,
417 DESC92_RATEMCS6 = 0x12,
418 DESC92_RATEMCS7 = 0x13,
419 DESC92_RATEMCS8 = 0x14,
420 DESC92_RATEMCS9 = 0x15,
421 DESC92_RATEMCS10 = 0x16,
422 DESC92_RATEMCS11 = 0x17,
423 DESC92_RATEMCS12 = 0x18,
424 DESC92_RATEMCS13 = 0x19,
425 DESC92_RATEMCS14 = 0x1a,
426 DESC92_RATEMCS15 = 0x1b,
427 DESC92_RATEMCS15_SG = 0x1c,
428 DESC92_RATEMCS32 = 0x20,
429 };
430
431 enum rtl_var_map {
432 /*reg map */
433 SYS_ISO_CTRL = 0,
434 SYS_FUNC_EN,
435 SYS_CLK,
436 MAC_RCR_AM,
437 MAC_RCR_AB,
438 MAC_RCR_ACRC32,
439 MAC_RCR_ACF,
440 MAC_RCR_AAP,
441
442 /*efuse map */
443 EFUSE_TEST,
444 EFUSE_CTRL,
445 EFUSE_CLK,
446 EFUSE_CLK_CTRL,
447 EFUSE_PWC_EV12V,
448 EFUSE_FEN_ELDR,
449 EFUSE_LOADER_CLK_EN,
450 EFUSE_ANA8M,
451 EFUSE_HWSET_MAX_SIZE,
452 EFUSE_MAX_SECTION_MAP,
453 EFUSE_REAL_CONTENT_SIZE,
454 EFUSE_OOB_PROTECT_BYTES_LEN,
455
456 /*CAM map */
457 RWCAM,
458 WCAMI,
459 RCAMO,
460 CAMDBG,
461 SECR,
462 SEC_CAM_NONE,
463 SEC_CAM_WEP40,
464 SEC_CAM_TKIP,
465 SEC_CAM_AES,
466 SEC_CAM_WEP104,
467
468 /*IMR map */
469 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
470 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
471 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
472 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
473 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
474 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
475 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
476 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
477 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
478 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
479 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
480 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
481 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
482 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
483 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
484 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
485 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
486 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
487 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
488 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
489 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
490 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
491 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
492 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
493 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
494 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
495 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
496 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
497 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
498 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
499 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
500 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
501 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
502 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
503 * RTL_IMR_TBDER) */
504
505 /*CCK Rates, TxHT = 0 */
506 RTL_RC_CCK_RATE1M,
507 RTL_RC_CCK_RATE2M,
508 RTL_RC_CCK_RATE5_5M,
509 RTL_RC_CCK_RATE11M,
510
511 /*OFDM Rates, TxHT = 0 */
512 RTL_RC_OFDM_RATE6M,
513 RTL_RC_OFDM_RATE9M,
514 RTL_RC_OFDM_RATE12M,
515 RTL_RC_OFDM_RATE18M,
516 RTL_RC_OFDM_RATE24M,
517 RTL_RC_OFDM_RATE36M,
518 RTL_RC_OFDM_RATE48M,
519 RTL_RC_OFDM_RATE54M,
520
521 RTL_RC_HT_RATEMCS7,
522 RTL_RC_HT_RATEMCS15,
523
524 /*keep it last */
525 RTL_VAR_MAP_MAX,
526 };
527
528 /*Firmware PS mode for control LPS.*/
529 enum _fw_ps_mode {
530 FW_PS_ACTIVE_MODE = 0,
531 FW_PS_MIN_MODE = 1,
532 FW_PS_MAX_MODE = 2,
533 FW_PS_DTIM_MODE = 3,
534 FW_PS_VOIP_MODE = 4,
535 FW_PS_UAPSD_WMM_MODE = 5,
536 FW_PS_UAPSD_MODE = 6,
537 FW_PS_IBSS_MODE = 7,
538 FW_PS_WWLAN_MODE = 8,
539 FW_PS_PM_Radio_Off = 9,
540 FW_PS_PM_Card_Disable = 10,
541 };
542
543 enum rt_psmode {
544 EACTIVE, /*Active/Continuous access. */
545 EMAXPS, /*Max power save mode. */
546 EFASTPS, /*Fast power save mode. */
547 EAUTOPS, /*Auto power save mode. */
548 };
549
550 /*LED related.*/
551 enum led_ctl_mode {
552 LED_CTL_POWER_ON = 1,
553 LED_CTL_LINK = 2,
554 LED_CTL_NO_LINK = 3,
555 LED_CTL_TX = 4,
556 LED_CTL_RX = 5,
557 LED_CTL_SITE_SURVEY = 6,
558 LED_CTL_POWER_OFF = 7,
559 LED_CTL_START_TO_LINK = 8,
560 LED_CTL_START_WPS = 9,
561 LED_CTL_STOP_WPS = 10,
562 };
563
564 enum rtl_led_pin {
565 LED_PIN_GPIO0,
566 LED_PIN_LED0,
567 LED_PIN_LED1,
568 LED_PIN_LED2
569 };
570
571 /*QoS related.*/
572 /*acm implementation method.*/
573 enum acm_method {
574 eAcmWay0_SwAndHw = 0,
575 eAcmWay1_HW = 1,
576 eAcmWay2_SW = 2,
577 };
578
579 enum macphy_mode {
580 SINGLEMAC_SINGLEPHY = 0,
581 DUALMAC_DUALPHY,
582 DUALMAC_SINGLEPHY,
583 };
584
585 enum band_type {
586 BAND_ON_2_4G = 0,
587 BAND_ON_5G,
588 BAND_ON_BOTH,
589 BANDMAX
590 };
591
592 /*aci/aifsn Field.
593 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
594 union aci_aifsn {
595 u8 char_data;
596
597 struct {
598 u8 aifsn:4;
599 u8 acm:1;
600 u8 aci:2;
601 u8 reserved:1;
602 } f; /* Field */
603 };
604
605 /*mlme related.*/
606 enum wireless_mode {
607 WIRELESS_MODE_UNKNOWN = 0x00,
608 WIRELESS_MODE_A = 0x01,
609 WIRELESS_MODE_B = 0x02,
610 WIRELESS_MODE_G = 0x04,
611 WIRELESS_MODE_AUTO = 0x08,
612 WIRELESS_MODE_N_24G = 0x10,
613 WIRELESS_MODE_N_5G = 0x20
614 };
615
616 #define IS_WIRELESS_MODE_A(wirelessmode) \
617 (wirelessmode == WIRELESS_MODE_A)
618 #define IS_WIRELESS_MODE_B(wirelessmode) \
619 (wirelessmode == WIRELESS_MODE_B)
620 #define IS_WIRELESS_MODE_G(wirelessmode) \
621 (wirelessmode == WIRELESS_MODE_G)
622 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
623 (wirelessmode == WIRELESS_MODE_N_24G)
624 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
625 (wirelessmode == WIRELESS_MODE_N_5G)
626
627 enum ratr_table_mode {
628 RATR_INX_WIRELESS_NGB = 0,
629 RATR_INX_WIRELESS_NG = 1,
630 RATR_INX_WIRELESS_NB = 2,
631 RATR_INX_WIRELESS_N = 3,
632 RATR_INX_WIRELESS_GB = 4,
633 RATR_INX_WIRELESS_G = 5,
634 RATR_INX_WIRELESS_B = 6,
635 RATR_INX_WIRELESS_MC = 7,
636 RATR_INX_WIRELESS_A = 8,
637 };
638
639 enum rtl_link_state {
640 MAC80211_NOLINK = 0,
641 MAC80211_LINKING = 1,
642 MAC80211_LINKED = 2,
643 MAC80211_LINKED_SCANNING = 3,
644 };
645
646 enum act_category {
647 ACT_CAT_QOS = 1,
648 ACT_CAT_DLS = 2,
649 ACT_CAT_BA = 3,
650 ACT_CAT_HT = 7,
651 ACT_CAT_WMM = 17,
652 };
653
654 enum ba_action {
655 ACT_ADDBAREQ = 0,
656 ACT_ADDBARSP = 1,
657 ACT_DELBA = 2,
658 };
659
660 struct octet_string {
661 u8 *octet;
662 u16 length;
663 };
664
665 struct rtl_hdr_3addr {
666 __le16 frame_ctl;
667 __le16 duration_id;
668 u8 addr1[ETH_ALEN];
669 u8 addr2[ETH_ALEN];
670 u8 addr3[ETH_ALEN];
671 __le16 seq_ctl;
672 u8 payload[0];
673 } __packed;
674
675 struct rtl_info_element {
676 u8 id;
677 u8 len;
678 u8 data[0];
679 } __packed;
680
681 struct rtl_probe_rsp {
682 struct rtl_hdr_3addr header;
683 u32 time_stamp[2];
684 __le16 beacon_interval;
685 __le16 capability;
686 /*SSID, supported rates, FH params, DS params,
687 CF params, IBSS params, TIM (if beacon), RSN */
688 struct rtl_info_element info_element[0];
689 } __packed;
690
691 /*LED related.*/
692 /*ledpin Identify how to implement this SW led.*/
693 struct rtl_led {
694 void *hw;
695 enum rtl_led_pin ledpin;
696 bool ledon;
697 };
698
699 struct rtl_led_ctl {
700 bool led_opendrain;
701 struct rtl_led sw_led0;
702 struct rtl_led sw_led1;
703 };
704
705 struct rtl_qos_parameters {
706 __le16 cw_min;
707 __le16 cw_max;
708 u8 aifs;
709 u8 flag;
710 __le16 tx_op;
711 } __packed;
712
713 struct rt_smooth_data {
714 u32 elements[100]; /*array to store values */
715 u32 index; /*index to current array to store */
716 u32 total_num; /*num of valid elements */
717 u32 total_val; /*sum of valid elements */
718 };
719
720 struct false_alarm_statistics {
721 u32 cnt_parity_fail;
722 u32 cnt_rate_illegal;
723 u32 cnt_crc8_fail;
724 u32 cnt_mcs_fail;
725 u32 cnt_fast_fsync_fail;
726 u32 cnt_sb_search_fail;
727 u32 cnt_ofdm_fail;
728 u32 cnt_cck_fail;
729 u32 cnt_all;
730 };
731
732 struct init_gain {
733 u8 xaagccore1;
734 u8 xbagccore1;
735 u8 xcagccore1;
736 u8 xdagccore1;
737 u8 cca;
738
739 };
740
741 struct wireless_stats {
742 unsigned long txbytesunicast;
743 unsigned long txbytesmulticast;
744 unsigned long txbytesbroadcast;
745 unsigned long rxbytesunicast;
746
747 long rx_snr_db[4];
748 /*Correct smoothed ss in Dbm, only used
749 in driver to report real power now. */
750 long recv_signal_power;
751 long signal_quality;
752 long last_sigstrength_inpercent;
753
754 u32 rssi_calculate_cnt;
755
756 /*Transformed, in dbm. Beautified signal
757 strength for UI, not correct. */
758 long signal_strength;
759
760 u8 rx_rssi_percentage[4];
761 u8 rx_evm_percentage[2];
762
763 struct rt_smooth_data ui_rssi;
764 struct rt_smooth_data ui_link_quality;
765 };
766
767 struct rate_adaptive {
768 u8 rate_adaptive_disabled;
769 u8 ratr_state;
770 u16 reserve;
771
772 u32 high_rssi_thresh_for_ra;
773 u32 high2low_rssi_thresh_for_ra;
774 u8 low2high_rssi_thresh_for_ra40m;
775 u32 low_rssi_thresh_for_ra40M;
776 u8 low2high_rssi_thresh_for_ra20m;
777 u32 low_rssi_thresh_for_ra20M;
778 u32 upper_rssi_threshold_ratr;
779 u32 middleupper_rssi_threshold_ratr;
780 u32 middle_rssi_threshold_ratr;
781 u32 middlelow_rssi_threshold_ratr;
782 u32 low_rssi_threshold_ratr;
783 u32 ultralow_rssi_threshold_ratr;
784 u32 low_rssi_threshold_ratr_40m;
785 u32 low_rssi_threshold_ratr_20m;
786 u8 ping_rssi_enable;
787 u32 ping_rssi_ratr;
788 u32 ping_rssi_thresh_for_ra;
789 u32 last_ratr;
790 u8 pre_ratr_state;
791 };
792
793 struct regd_pair_mapping {
794 u16 reg_dmnenum;
795 u16 reg_5ghz_ctl;
796 u16 reg_2ghz_ctl;
797 };
798
799 struct rtl_regulatory {
800 char alpha2[2];
801 u16 country_code;
802 u16 max_power_level;
803 u32 tp_scale;
804 u16 current_rd;
805 u16 current_rd_ext;
806 int16_t power_limit;
807 struct regd_pair_mapping *regpair;
808 };
809
810 struct rtl_rfkill {
811 bool rfkill_state; /*0 is off, 1 is on */
812 };
813
814 #define IQK_MATRIX_REG_NUM 8
815 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
816 struct iqk_matrix_regs {
817 bool iqk_done;
818 long value[1][IQK_MATRIX_REG_NUM];
819 };
820
821 struct phy_parameters {
822 u16 length;
823 u32 *pdata;
824 };
825
826 enum hw_param_tab_index {
827 PHY_REG_2T,
828 PHY_REG_1T,
829 PHY_REG_PG,
830 RADIOA_2T,
831 RADIOB_2T,
832 RADIOA_1T,
833 RADIOB_1T,
834 MAC_REG,
835 AGCTAB_2T,
836 AGCTAB_1T,
837 MAX_TAB
838 };
839
840 struct rtl_phy {
841 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
842 struct init_gain initgain_backup;
843 enum io_type current_io_type;
844
845 u8 rf_mode;
846 u8 rf_type;
847 u8 current_chan_bw;
848 u8 set_bwmode_inprogress;
849 u8 sw_chnl_inprogress;
850 u8 sw_chnl_stage;
851 u8 sw_chnl_step;
852 u8 current_channel;
853 u8 h2c_box_num;
854 u8 set_io_inprogress;
855 u8 lck_inprogress;
856
857 /* record for power tracking */
858 s32 reg_e94;
859 s32 reg_e9c;
860 s32 reg_ea4;
861 s32 reg_eac;
862 s32 reg_eb4;
863 s32 reg_ebc;
864 s32 reg_ec4;
865 s32 reg_ecc;
866 u8 rfpienable;
867 u8 reserve_0;
868 u16 reserve_1;
869 u32 reg_c04, reg_c08, reg_874;
870 u32 adda_backup[16];
871 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
872 u32 iqk_bb_backup[10];
873
874 /* Dual mac */
875 bool need_iqk;
876 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
877
878 bool rfpi_enable;
879
880 u8 pwrgroup_cnt;
881 u8 cck_high_power;
882 /* MAX_PG_GROUP groups of pwr diff by rates */
883 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
884 u8 default_initialgain[4];
885
886 /* the current Tx power level */
887 u8 cur_cck_txpwridx;
888 u8 cur_ofdm24g_txpwridx;
889
890 u32 rfreg_chnlval[2];
891 bool apk_done;
892 u32 reg_rf3c[2]; /* pathA / pathB */
893
894 /* bfsync */
895 u8 framesync;
896 u32 framesync_c34;
897
898 u8 num_total_rfpath;
899 struct phy_parameters hwparam_tables[MAX_TAB];
900 u16 rf_pathmap;
901 };
902
903 #define MAX_TID_COUNT 9
904 #define RTL_AGG_STOP 0
905 #define RTL_AGG_PROGRESS 1
906 #define RTL_AGG_START 2
907 #define RTL_AGG_OPERATIONAL 3
908 #define RTL_AGG_OFF 0
909 #define RTL_AGG_ON 1
910 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
911 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
912
913 struct rtl_ht_agg {
914 u16 txq_id;
915 u16 wait_for_ba;
916 u16 start_idx;
917 u64 bitmap;
918 u32 rate_n_flags;
919 u8 agg_state;
920 };
921
922 struct rtl_tid_data {
923 u16 seq_number;
924 struct rtl_ht_agg agg;
925 };
926
927 struct rtl_sta_info {
928 u8 ratr_index;
929 u8 wireless_mode;
930 u8 mimo_ps;
931 struct rtl_tid_data tids[MAX_TID_COUNT];
932 } __packed;
933
934 struct rtl_priv;
935 struct rtl_io {
936 struct device *dev;
937 struct mutex bb_mutex;
938
939 /*PCI MEM map */
940 unsigned long pci_mem_end; /*shared mem end */
941 unsigned long pci_mem_start; /*shared mem start */
942
943 /*PCI IO map */
944 unsigned long pci_base_addr; /*device I/O address */
945
946 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
947 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
948 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
949 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
950 u16 len);
951
952 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
953 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
954 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
955
956 };
957
958 struct rtl_mac {
959 u8 mac_addr[ETH_ALEN];
960 u8 mac80211_registered;
961 u8 beacon_enabled;
962
963 u32 tx_ss_num;
964 u32 rx_ss_num;
965
966 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
967 struct ieee80211_hw *hw;
968 struct ieee80211_vif *vif;
969 enum nl80211_iftype opmode;
970
971 /*Probe Beacon management */
972 struct rtl_tid_data tids[MAX_TID_COUNT];
973 enum rtl_link_state link_state;
974
975 int n_channels;
976 int n_bitrates;
977
978 bool offchan_delay;
979
980 /*filters */
981 u32 rx_conf;
982 u16 rx_mgt_filter;
983 u16 rx_ctrl_filter;
984 u16 rx_data_filter;
985
986 bool act_scanning;
987 u8 cnt_after_linked;
988
989 /* early mode */
990 /* skb wait queue */
991 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
992 u8 earlymode_threshold;
993
994 /*RDG*/
995 bool rdg_en;
996
997 /*AP*/
998 u8 bssid[6];
999 u32 vendor;
1000 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1001 u32 basic_rates; /* b/g rates */
1002 u8 ht_enable;
1003 u8 sgi_40;
1004 u8 sgi_20;
1005 u8 bw_40;
1006 u8 mode; /* wireless mode */
1007 u8 slot_time;
1008 u8 short_preamble;
1009 u8 use_cts_protect;
1010 u8 cur_40_prime_sc;
1011 u8 cur_40_prime_sc_bk;
1012 u64 tsf;
1013 u8 retry_short;
1014 u8 retry_long;
1015 u16 assoc_id;
1016
1017 /*IBSS*/
1018 int beacon_interval;
1019
1020 /*AMPDU*/
1021 u8 min_space_cfg; /*For Min spacing configurations */
1022 u8 max_mss_density;
1023 u8 current_ampdu_factor;
1024 u8 current_ampdu_density;
1025
1026 /*QOS & EDCA */
1027 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1028 struct rtl_qos_parameters ac[AC_MAX];
1029 };
1030
1031 struct rtl_hal {
1032 struct ieee80211_hw *hw;
1033
1034 enum intf_type interface;
1035 u16 hw_type; /*92c or 92d or 92s and so on */
1036 u8 ic_class;
1037 u8 oem_id;
1038 u32 version; /*version of chip */
1039 u8 state; /*stop 0, start 1 */
1040
1041 /*firmware */
1042 u32 fwsize;
1043 u8 *pfirmware;
1044 u16 fw_version;
1045 u16 fw_subversion;
1046 bool h2c_setinprogress;
1047 u8 last_hmeboxnum;
1048 bool fw_ready;
1049 /*Reserve page start offset except beacon in TxQ. */
1050 u8 fw_rsvdpage_startoffset;
1051 u8 h2c_txcmd_seq;
1052
1053 /* FW Cmd IO related */
1054 u16 fwcmd_iomap;
1055 u32 fwcmd_ioparam;
1056 bool set_fwcmd_inprogress;
1057 u8 current_fwcmd_io;
1058
1059 /**/
1060 bool driver_going2unload;
1061
1062 /*AMPDU init min space*/
1063 u8 minspace_cfg; /*For Min spacing configurations */
1064
1065 /* Dual mac */
1066 enum macphy_mode macphymode;
1067 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1068 enum band_type current_bandtypebackup;
1069 enum band_type bandset;
1070 /* dual MAC 0--Mac0 1--Mac1 */
1071 u32 interfaceindex;
1072 /* just for DualMac S3S4 */
1073 u8 macphyctl_reg;
1074 bool earlymode_enable;
1075 /* Dual mac*/
1076 bool during_mac0init_radiob;
1077 bool during_mac1init_radioa;
1078 bool reloadtxpowerindex;
1079 /* True if IMR or IQK have done
1080 for 2.4G in scan progress */
1081 bool load_imrandiqk_setting_for2g;
1082
1083 bool disable_amsdu_8k;
1084 };
1085
1086 struct rtl_security {
1087 /*default 0 */
1088 bool use_sw_sec;
1089
1090 bool being_setkey;
1091 bool use_defaultkey;
1092 /*Encryption Algorithm for Unicast Packet */
1093 enum rt_enc_alg pairwise_enc_algorithm;
1094 /*Encryption Algorithm for Brocast/Multicast */
1095 enum rt_enc_alg group_enc_algorithm;
1096 /*Cam Entry Bitmap */
1097 u32 hwsec_cam_bitmap;
1098 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1099 /*local Key buffer, indx 0 is for
1100 pairwise key 1-4 is for agoup key. */
1101 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1102 u8 key_len[KEY_BUF_SIZE];
1103
1104 /*The pointer of Pairwise Key,
1105 it always points to KeyBuf[4] */
1106 u8 *pairwise_key;
1107 };
1108
1109 struct rtl_dm {
1110 /*PHY status for Dynamic Management */
1111 long entry_min_undecoratedsmoothed_pwdb;
1112 long undecorated_smoothed_pwdb; /*out dm */
1113 long entry_max_undecoratedsmoothed_pwdb;
1114 bool dm_initialgain_enable;
1115 bool dynamic_txpower_enable;
1116 bool current_turbo_edca;
1117 bool is_any_nonbepkts; /*out dm */
1118 bool is_cur_rdlstate;
1119 bool txpower_trackinginit;
1120 bool disable_framebursting;
1121 bool cck_inch14;
1122 bool txpower_tracking;
1123 bool useramask;
1124 bool rfpath_rxenable[4];
1125 bool inform_fw_driverctrldm;
1126 bool current_mrc_switch;
1127 u8 txpowercount;
1128
1129 u8 thermalvalue_rxgain;
1130 u8 thermalvalue_iqk;
1131 u8 thermalvalue_lck;
1132 u8 thermalvalue;
1133 u8 last_dtp_lvl;
1134 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1135 u8 thermalvalue_avg_index;
1136 bool done_txpower;
1137 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1138 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1139 u8 dm_type;
1140 u8 txpower_track_control;
1141 bool interrupt_migration;
1142 bool disable_tx_int;
1143 char ofdm_index[2];
1144 char cck_index;
1145 };
1146
1147 #define EFUSE_MAX_LOGICAL_SIZE 256
1148
1149 struct rtl_efuse {
1150 bool autoLoad_ok;
1151 bool bootfromefuse;
1152 u16 max_physical_size;
1153
1154 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1155 u16 efuse_usedbytes;
1156 u8 efuse_usedpercentage;
1157 #ifdef EFUSE_REPG_WORKAROUND
1158 bool efuse_re_pg_sec1flag;
1159 u8 efuse_re_pg_data[8];
1160 #endif
1161
1162 u8 autoload_failflag;
1163 u8 autoload_status;
1164
1165 short epromtype;
1166 u16 eeprom_vid;
1167 u16 eeprom_did;
1168 u16 eeprom_svid;
1169 u16 eeprom_smid;
1170 u8 eeprom_oemid;
1171 u16 eeprom_channelplan;
1172 u8 eeprom_version;
1173 u8 board_type;
1174 u8 external_pa;
1175
1176 u8 dev_addr[6];
1177
1178 bool txpwr_fromeprom;
1179 u8 eeprom_crystalcap;
1180 u8 eeprom_tssi[2];
1181 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1182 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1183 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1184 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1185 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1186 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1187 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1188 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1189 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1190
1191 u8 internal_pa_5g[2]; /* pathA / pathB */
1192 u8 eeprom_c9;
1193 u8 eeprom_cc;
1194
1195 /*For power group */
1196 u8 eeprom_pwrgroup[2][3];
1197 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1198 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1199
1200 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1201 /*For HT<->legacy pwr diff*/
1202 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1203 u8 txpwr_safetyflag; /* Band edge enable flag */
1204 u16 eeprom_txpowerdiff;
1205 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1206 u8 antenna_txpwdiff[3];
1207
1208 u8 eeprom_regulatory;
1209 u8 eeprom_thermalmeter;
1210 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1211 u16 tssi_13dbm;
1212 u8 crystalcap; /* CrystalCap. */
1213 u8 delta_iqk;
1214 u8 delta_lck;
1215
1216 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1217 bool apk_thermalmeterignore;
1218
1219 bool b1x1_recvcombine;
1220 bool b1ss_support;
1221
1222 /*channel plan */
1223 u8 channel_plan;
1224 };
1225
1226 struct rtl_ps_ctl {
1227 bool pwrdomain_protect;
1228 bool in_powersavemode;
1229 bool rfchange_inprogress;
1230 bool swrf_processing;
1231 bool hwradiooff;
1232
1233 /*
1234 * just for PCIE ASPM
1235 * If it supports ASPM, Offset[560h] = 0x40,
1236 * otherwise Offset[560h] = 0x00.
1237 * */
1238 bool support_aspm;
1239
1240 bool support_backdoor;
1241
1242 /*for LPS */
1243 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1244 bool swctrl_lps;
1245 bool leisure_ps;
1246 bool fwctrl_lps;
1247 u8 fwctrl_psmode;
1248 /*For Fw control LPS mode */
1249 u8 reg_fwctrl_lps;
1250 /*Record Fw PS mode status. */
1251 bool fw_current_inpsmode;
1252 u8 reg_max_lps_awakeintvl;
1253 bool report_linked;
1254
1255 /*for IPS */
1256 bool inactiveps;
1257
1258 u32 rfoff_reason;
1259
1260 /*RF OFF Level */
1261 u32 cur_ps_level;
1262 u32 reg_rfps_level;
1263
1264 /*just for PCIE ASPM */
1265 u8 const_amdpci_aspm;
1266 bool pwrdown_mode;
1267
1268 enum rf_pwrstate inactive_pwrstate;
1269 enum rf_pwrstate rfpwr_state; /*cur power state */
1270
1271 /* for SW LPS*/
1272 bool sw_ps_enabled;
1273 bool state;
1274 bool state_inap;
1275 bool multi_buffered;
1276 u16 nullfunc_seq;
1277 unsigned int dtim_counter;
1278 unsigned int sleep_ms;
1279 unsigned long last_sleep_jiffies;
1280 unsigned long last_awake_jiffies;
1281 unsigned long last_delaylps_stamp_jiffies;
1282 unsigned long last_dtim;
1283 unsigned long last_beacon;
1284 unsigned long last_action;
1285 unsigned long last_slept;
1286 };
1287
1288 struct rtl_stats {
1289 u32 mac_time[2];
1290 s8 rssi;
1291 u8 signal;
1292 u8 noise;
1293 u16 rate; /*in 100 kbps */
1294 u8 received_channel;
1295 u8 control;
1296 u8 mask;
1297 u8 freq;
1298 u16 len;
1299 u64 tsf;
1300 u32 beacon_time;
1301 u8 nic_type;
1302 u16 length;
1303 u8 signalquality; /*in 0-100 index. */
1304 /*
1305 * Real power in dBm for this packet,
1306 * no beautification and aggregation.
1307 * */
1308 s32 recvsignalpower;
1309 s8 rxpower; /*in dBm Translate from PWdB */
1310 u8 signalstrength; /*in 0-100 index. */
1311 u16 hwerror:1;
1312 u16 crc:1;
1313 u16 icv:1;
1314 u16 shortpreamble:1;
1315 u16 antenna:1;
1316 u16 decrypted:1;
1317 u16 wakeup:1;
1318 u32 timestamp_low;
1319 u32 timestamp_high;
1320
1321 u8 rx_drvinfo_size;
1322 u8 rx_bufshift;
1323 bool isampdu;
1324 bool isfirst_ampdu;
1325 bool rx_is40Mhzpacket;
1326 u32 rx_pwdb_all;
1327 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1328 s8 rx_mimo_signalquality[2];
1329 bool packet_matchbssid;
1330 bool is_cck;
1331 bool is_ht;
1332 bool packet_toself;
1333 bool packet_beacon; /*for rssi */
1334 char cck_adc_pwdb[4]; /*for rx path selection */
1335 };
1336
1337 struct rt_link_detect {
1338 u32 num_tx_in4period[4];
1339 u32 num_rx_in4period[4];
1340
1341 u32 num_tx_inperiod;
1342 u32 num_rx_inperiod;
1343
1344 bool busytraffic;
1345 bool higher_busytraffic;
1346 bool higher_busyrxtraffic;
1347
1348 u32 tidtx_in4period[MAX_TID_COUNT][4];
1349 u32 tidtx_inperiod[MAX_TID_COUNT];
1350 bool higher_busytxtraffic[MAX_TID_COUNT];
1351 };
1352
1353 struct rtl_tcb_desc {
1354 u8 packet_bw:1;
1355 u8 multicast:1;
1356 u8 broadcast:1;
1357
1358 u8 rts_stbc:1;
1359 u8 rts_enable:1;
1360 u8 cts_enable:1;
1361 u8 rts_use_shortpreamble:1;
1362 u8 rts_use_shortgi:1;
1363 u8 rts_sc:1;
1364 u8 rts_bw:1;
1365 u8 rts_rate;
1366
1367 u8 use_shortgi:1;
1368 u8 use_shortpreamble:1;
1369 u8 use_driver_rate:1;
1370 u8 disable_ratefallback:1;
1371
1372 u8 ratr_index;
1373 u8 mac_id;
1374 u8 hw_rate;
1375
1376 u8 last_inipkt:1;
1377 u8 cmd_or_init:1;
1378 u8 queue_index;
1379
1380 /* early mode */
1381 u8 empkt_num;
1382 /* The max value by HW */
1383 u32 empkt_len[5];
1384 };
1385
1386 struct rtl_hal_ops {
1387 int (*init_sw_vars) (struct ieee80211_hw *hw);
1388 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1389 void (*read_chip_version)(struct ieee80211_hw *hw);
1390 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1391 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1392 u32 *p_inta, u32 *p_intb);
1393 int (*hw_init) (struct ieee80211_hw *hw);
1394 void (*hw_disable) (struct ieee80211_hw *hw);
1395 void (*hw_suspend) (struct ieee80211_hw *hw);
1396 void (*hw_resume) (struct ieee80211_hw *hw);
1397 void (*enable_interrupt) (struct ieee80211_hw *hw);
1398 void (*disable_interrupt) (struct ieee80211_hw *hw);
1399 int (*set_network_type) (struct ieee80211_hw *hw,
1400 enum nl80211_iftype type);
1401 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1402 bool check_bssid);
1403 void (*set_bw_mode) (struct ieee80211_hw *hw,
1404 enum nl80211_channel_type ch_type);
1405 u8(*switch_channel) (struct ieee80211_hw *hw);
1406 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1407 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1408 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1409 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1410 u32 add_msr, u32 rm_msr);
1411 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1412 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1413 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1414 struct ieee80211_sta *sta, u8 rssi_level);
1415 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1416 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1417 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1418 struct ieee80211_tx_info *info,
1419 struct sk_buff *skb, u8 hw_queue,
1420 struct rtl_tcb_desc *ptcb_desc);
1421 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1422 u32 buffer_len, bool bIsPsPoll);
1423 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1424 bool firstseg, bool lastseg,
1425 struct sk_buff *skb);
1426 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1427 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1428 struct rtl_stats *stats,
1429 struct ieee80211_rx_status *rx_status,
1430 u8 *pdesc, struct sk_buff *skb);
1431 void (*set_channel_access) (struct ieee80211_hw *hw);
1432 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1433 void (*dm_watchdog) (struct ieee80211_hw *hw);
1434 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1435 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1436 enum rf_pwrstate rfpwr_state);
1437 void (*led_control) (struct ieee80211_hw *hw,
1438 enum led_ctl_mode ledaction);
1439 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1440 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1441 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1442 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1443 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1444 u8 *macaddr, bool is_group, u8 enc_algo,
1445 bool is_wepkey, bool clear_all);
1446 void (*init_sw_leds) (struct ieee80211_hw *hw);
1447 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1448 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1449 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1450 u32 data);
1451 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1452 u32 regaddr, u32 bitmask);
1453 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1454 u32 regaddr, u32 bitmask, u32 data);
1455 void (*linked_set_reg) (struct ieee80211_hw *hw);
1456 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1457 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1458 u8 *powerlevel);
1459 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1460 u8 *ppowerlevel, u8 channel);
1461 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1462 u8 configtype);
1463 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1464 u8 configtype);
1465 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1466 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1467 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1468 };
1469
1470 struct rtl_intf_ops {
1471 /*com */
1472 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1473 int (*adapter_start) (struct ieee80211_hw *hw);
1474 void (*adapter_stop) (struct ieee80211_hw *hw);
1475
1476 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1477 struct rtl_tcb_desc *ptcb_desc);
1478 void (*flush)(struct ieee80211_hw *hw, bool drop);
1479 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1480 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1481
1482 /*pci */
1483 void (*disable_aspm) (struct ieee80211_hw *hw);
1484 void (*enable_aspm) (struct ieee80211_hw *hw);
1485
1486 /*usb */
1487 };
1488
1489 struct rtl_mod_params {
1490 /* default: 0 = using hardware encryption */
1491 bool sw_crypto;
1492
1493 /* default: 0 = DBG_EMERG (0)*/
1494 int debug;
1495
1496 /* default: 1 = using no linked power save */
1497 bool inactiveps;
1498
1499 /* default: 1 = using linked sw power save */
1500 bool swctrl_lps;
1501
1502 /* default: 1 = using linked fw power save */
1503 bool fwctrl_lps;
1504 };
1505
1506 struct rtl_hal_usbint_cfg {
1507 /* data - rx */
1508 u32 in_ep_num;
1509 u32 rx_urb_num;
1510 u32 rx_max_size;
1511
1512 /* op - rx */
1513 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1514 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1515 struct sk_buff_head *);
1516
1517 /* tx */
1518 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1519 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1520 struct sk_buff *);
1521 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1522 struct sk_buff_head *);
1523
1524 /* endpoint mapping */
1525 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1526 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1527 };
1528
1529 struct rtl_hal_cfg {
1530 u8 bar_id;
1531 bool write_readback;
1532 char *name;
1533 char *fw_name;
1534 struct rtl_hal_ops *ops;
1535 struct rtl_mod_params *mod_params;
1536 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1537
1538 /*this map used for some registers or vars
1539 defined int HAL but used in MAIN */
1540 u32 maps[RTL_VAR_MAP_MAX];
1541
1542 };
1543
1544 struct rtl_locks {
1545 /* mutex */
1546 struct mutex conf_mutex;
1547 struct mutex ps_mutex;
1548
1549 /*spin lock */
1550 spinlock_t ips_lock;
1551 spinlock_t irq_th_lock;
1552 spinlock_t h2c_lock;
1553 spinlock_t rf_ps_lock;
1554 spinlock_t rf_lock;
1555 spinlock_t waitq_lock;
1556
1557 /*Dual mac*/
1558 spinlock_t cck_and_rw_pagea_lock;
1559 };
1560
1561 struct rtl_works {
1562 struct ieee80211_hw *hw;
1563
1564 /*timer */
1565 struct timer_list watchdog_timer;
1566
1567 /*task */
1568 struct tasklet_struct irq_tasklet;
1569 struct tasklet_struct irq_prepare_bcn_tasklet;
1570
1571 /*work queue */
1572 struct workqueue_struct *rtl_wq;
1573 struct delayed_work watchdog_wq;
1574 struct delayed_work ips_nic_off_wq;
1575
1576 /* For SW LPS */
1577 struct delayed_work ps_work;
1578 struct delayed_work ps_rfon_wq;
1579
1580 struct work_struct lps_leave_work;
1581 };
1582
1583 struct rtl_debug {
1584 u32 dbgp_type[DBGP_TYPE_MAX];
1585 u32 global_debuglevel;
1586 u64 global_debugcomponents;
1587
1588 /* add for proc debug */
1589 struct proc_dir_entry *proc_dir;
1590 char proc_name[20];
1591 };
1592
1593 struct rtl_priv {
1594 struct rtl_locks locks;
1595 struct rtl_works works;
1596 struct rtl_mac mac80211;
1597 struct rtl_hal rtlhal;
1598 struct rtl_regulatory regd;
1599 struct rtl_rfkill rfkill;
1600 struct rtl_io io;
1601 struct rtl_phy phy;
1602 struct rtl_dm dm;
1603 struct rtl_security sec;
1604 struct rtl_efuse efuse;
1605
1606 struct rtl_ps_ctl psc;
1607 struct rate_adaptive ra;
1608 struct wireless_stats stats;
1609 struct rt_link_detect link_info;
1610 struct false_alarm_statistics falsealm_cnt;
1611
1612 struct rtl_rate_priv *rate_priv;
1613
1614 struct rtl_debug dbg;
1615
1616 /*
1617 *hal_cfg : for diff cards
1618 *intf_ops : for diff interrface usb/pcie
1619 */
1620 struct rtl_hal_cfg *cfg;
1621 struct rtl_intf_ops *intf_ops;
1622
1623 /*this var will be set by set_bit,
1624 and was used to indicate status of
1625 interface or hardware */
1626 unsigned long status;
1627
1628 /*This must be the last item so
1629 that it points to the data allocated
1630 beyond this structure like:
1631 rtl_pci_priv or rtl_usb_priv */
1632 u8 priv[0];
1633 };
1634
1635 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1636 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1637 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1638 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1639 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1640
1641
1642 /***************************************
1643 Bluetooth Co-existence Related
1644 ****************************************/
1645
1646 enum bt_ant_num {
1647 ANT_X2 = 0,
1648 ANT_X1 = 1,
1649 };
1650
1651 enum bt_co_type {
1652 BT_2WIRE = 0,
1653 BT_ISSC_3WIRE = 1,
1654 BT_ACCEL = 2,
1655 BT_CSR_BC4 = 3,
1656 BT_CSR_BC8 = 4,
1657 BT_RTL8756 = 5,
1658 };
1659
1660 enum bt_cur_state {
1661 BT_OFF = 0,
1662 BT_ON = 1,
1663 };
1664
1665 enum bt_service_type {
1666 BT_SCO = 0,
1667 BT_A2DP = 1,
1668 BT_HID = 2,
1669 BT_HID_IDLE = 3,
1670 BT_SCAN = 4,
1671 BT_IDLE = 5,
1672 BT_OTHER_ACTION = 6,
1673 BT_BUSY = 7,
1674 BT_OTHERBUSY = 8,
1675 BT_PAN = 9,
1676 };
1677
1678 enum bt_radio_shared {
1679 BT_RADIO_SHARED = 0,
1680 BT_RADIO_INDIVIDUAL = 1,
1681 };
1682
1683 struct bt_coexist_info {
1684
1685 /* EEPROM BT info. */
1686 u8 eeprom_bt_coexist;
1687 u8 eeprom_bt_type;
1688 u8 eeprom_bt_ant_num;
1689 u8 eeprom_bt_ant_isolation;
1690 u8 eeprom_bt_radio_shared;
1691
1692 u8 bt_coexistence;
1693 u8 bt_ant_num;
1694 u8 bt_coexist_type;
1695 u8 bt_state;
1696 u8 bt_cur_state; /* 0:on, 1:off */
1697 u8 bt_ant_isolation; /* 0:good, 1:bad */
1698 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1699 u8 bt_service;
1700 u8 bt_radio_shared_type;
1701 u8 bt_rfreg_origin_1e;
1702 u8 bt_rfreg_origin_1f;
1703 u8 bt_rssi_state;
1704 u32 ratio_tx;
1705 u32 ratio_pri;
1706 u32 bt_edca_ul;
1707 u32 bt_edca_dl;
1708
1709 bool init_set;
1710 bool bt_busy_traffic;
1711 bool bt_traffic_mode_set;
1712 bool bt_non_traffic_mode_set;
1713
1714 bool fw_coexist_all_off;
1715 bool sw_coexist_all_off;
1716 u32 current_state;
1717 u32 previous_state;
1718 u8 bt_pre_rssi_state;
1719
1720 u8 reg_bt_iso;
1721 u8 reg_bt_sco;
1722
1723 };
1724
1725
1726 /****************************************
1727 mem access macro define start
1728 Call endian free function when
1729 1. Read/write packet content.
1730 2. Before write integer to IO.
1731 3. After read integer from IO.
1732 ****************************************/
1733 /* Convert little data endian to host ordering */
1734 #define EF1BYTE(_val) \
1735 ((u8)(_val))
1736 #define EF2BYTE(_val) \
1737 (le16_to_cpu(_val))
1738 #define EF4BYTE(_val) \
1739 (le32_to_cpu(_val))
1740
1741 /* Read data from memory */
1742 #define READEF1BYTE(_ptr) \
1743 EF1BYTE(*((u8 *)(_ptr)))
1744 /* Read le16 data from memory and convert to host ordering */
1745 #define READEF2BYTE(_ptr) \
1746 EF2BYTE(*((u16 *)(_ptr)))
1747 #define READEF4BYTE(_ptr) \
1748 EF4BYTE(*((u32 *)(_ptr)))
1749
1750 /* Write data to memory */
1751 #define WRITEEF1BYTE(_ptr, _val) \
1752 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1753 /* Write le16 data to memory in host ordering */
1754 #define WRITEEF2BYTE(_ptr, _val) \
1755 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1756 #define WRITEEF4BYTE(_ptr, _val) \
1757 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1758
1759 /* Create a bit mask
1760 * Examples:
1761 * BIT_LEN_MASK_32(0) => 0x00000000
1762 * BIT_LEN_MASK_32(1) => 0x00000001
1763 * BIT_LEN_MASK_32(2) => 0x00000003
1764 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1765 */
1766 #define BIT_LEN_MASK_32(__bitlen) \
1767 (0xFFFFFFFF >> (32 - (__bitlen)))
1768 #define BIT_LEN_MASK_16(__bitlen) \
1769 (0xFFFF >> (16 - (__bitlen)))
1770 #define BIT_LEN_MASK_8(__bitlen) \
1771 (0xFF >> (8 - (__bitlen)))
1772
1773 /* Create an offset bit mask
1774 * Examples:
1775 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1776 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1777 */
1778 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1779 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1780 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1781 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1782 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1783 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1784
1785 /*Description:
1786 * Return 4-byte value in host byte ordering from
1787 * 4-byte pointer in little-endian system.
1788 */
1789 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1790 (EF4BYTE(*((u32 *)(__pstart))))
1791 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1792 (EF2BYTE(*((u16 *)(__pstart))))
1793 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1794 (EF1BYTE(*((u8 *)(__pstart))))
1795
1796 /*Description:
1797 Translate subfield (continuous bits in little-endian) of 4-byte
1798 value to host byte ordering.*/
1799 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1800 ( \
1801 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1802 BIT_LEN_MASK_32(__bitlen) \
1803 )
1804 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1805 ( \
1806 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1807 BIT_LEN_MASK_16(__bitlen) \
1808 )
1809 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1810 ( \
1811 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1812 BIT_LEN_MASK_8(__bitlen) \
1813 )
1814
1815 /* Description:
1816 * Mask subfield (continuous bits in little-endian) of 4-byte value
1817 * and return the result in 4-byte value in host byte ordering.
1818 */
1819 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1820 ( \
1821 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1822 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1823 )
1824 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1825 ( \
1826 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1827 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1828 )
1829 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1830 ( \
1831 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1832 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1833 )
1834
1835 /* Description:
1836 * Set subfield of little-endian 4-byte value to specified value.
1837 */
1838 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1839 *((u32 *)(__pstart)) = EF4BYTE \
1840 ( \
1841 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1842 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1843 );
1844 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1845 *((u16 *)(__pstart)) = EF2BYTE \
1846 ( \
1847 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1848 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1849 );
1850 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1851 *((u8 *)(__pstart)) = EF1BYTE \
1852 ( \
1853 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1854 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1855 );
1856
1857 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1858 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1859
1860 /****************************************
1861 mem access macro define end
1862 ****************************************/
1863
1864 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1865
1866 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1867 #define RTL_WATCH_DOG_TIME 2000
1868 #define MSECS(t) msecs_to_jiffies(t)
1869 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1870 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1871 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1872 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1873 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1874 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1875 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1876
1877 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1878 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1879 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1880 /*NIC halt, re-initialize hw parameters*/
1881 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1882 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1883 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1884 /*Always enable ASPM and Clock Req in initialization.*/
1885 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1886 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1887 #define RT_PS_LEVEL_ASPM BIT(7)
1888 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1889 #define RT_RF_LPS_DISALBE_2R BIT(30)
1890 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1891 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1892 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1893 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1894 (ppsc->cur_ps_level &= (~(_ps_flg)))
1895 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1896 (ppsc->cur_ps_level |= _ps_flg)
1897
1898 #define container_of_dwork_rtl(x, y, z) \
1899 container_of(container_of(x, struct delayed_work, work), y, z)
1900
1901 #define FILL_OCTET_STRING(_os, _octet, _len) \
1902 (_os).octet = (u8 *)(_octet); \
1903 (_os).length = (_len);
1904
1905 #define CP_MACADDR(des, src) \
1906 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1907 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1908 (des)[4] = (src)[4], (des)[5] = (src)[5])
1909
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)1910 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1911 {
1912 return rtlpriv->io.read8_sync(rtlpriv, addr);
1913 }
1914
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)1915 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1916 {
1917 return rtlpriv->io.read16_sync(rtlpriv, addr);
1918 }
1919
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)1920 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1921 {
1922 return rtlpriv->io.read32_sync(rtlpriv, addr);
1923 }
1924
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)1925 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1926 {
1927 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1928
1929 if (rtlpriv->cfg->write_readback)
1930 rtlpriv->io.read8_sync(rtlpriv, addr);
1931 }
1932
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)1933 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1934 {
1935 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1936
1937 if (rtlpriv->cfg->write_readback)
1938 rtlpriv->io.read16_sync(rtlpriv, addr);
1939 }
1940
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)1941 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1942 u32 addr, u32 val32)
1943 {
1944 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1945
1946 if (rtlpriv->cfg->write_readback)
1947 rtlpriv->io.read32_sync(rtlpriv, addr);
1948 }
1949
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)1950 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1951 u32 regaddr, u32 bitmask)
1952 {
1953 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1954 regaddr,
1955 bitmask);
1956 }
1957
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)1958 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1959 u32 bitmask, u32 data)
1960 {
1961 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1962 regaddr, bitmask,
1963 data);
1964
1965 }
1966
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)1967 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1968 enum radio_path rfpath, u32 regaddr,
1969 u32 bitmask)
1970 {
1971 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1972 rfpath,
1973 regaddr,
1974 bitmask);
1975 }
1976
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)1977 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1978 enum radio_path rfpath, u32 regaddr,
1979 u32 bitmask, u32 data)
1980 {
1981 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1982 rfpath, regaddr,
1983 bitmask, data);
1984 }
1985
is_hal_stop(struct rtl_hal * rtlhal)1986 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1987 {
1988 return (_HAL_STATE_STOP == rtlhal->state);
1989 }
1990
set_hal_start(struct rtl_hal * rtlhal)1991 static inline void set_hal_start(struct rtl_hal *rtlhal)
1992 {
1993 rtlhal->state = _HAL_STATE_START;
1994 }
1995
set_hal_stop(struct rtl_hal * rtlhal)1996 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1997 {
1998 rtlhal->state = _HAL_STATE_STOP;
1999 }
2000
get_rf_type(struct rtl_phy * rtlphy)2001 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2002 {
2003 return rtlphy->rf_type;
2004 }
2005
rtl_get_hdr(struct sk_buff * skb)2006 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2007 {
2008 return (struct ieee80211_hdr *)(skb->data);
2009 }
2010
rtl_get_fc(struct sk_buff * skb)2011 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2012 {
2013 return rtl_get_hdr(skb)->frame_control;
2014 }
2015
rtl_get_tid_h(struct ieee80211_hdr * hdr)2016 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2017 {
2018 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2019 }
2020
rtl_get_tid(struct sk_buff * skb)2021 static inline u16 rtl_get_tid(struct sk_buff *skb)
2022 {
2023 return rtl_get_tid_h(rtl_get_hdr(skb));
2024 }
2025
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)2026 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2027 struct ieee80211_vif *vif,
2028 const u8 *bssid)
2029 {
2030 return ieee80211_find_sta(vif, bssid);
2031 }
2032
2033 #endif
2034