1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/vmalloc.h>
33 #include <linux/module.h>
34
35 #include "../wifi.h"
36 #include "../core.h"
37 #include "../pci.h"
38 #include "reg.h"
39 #include "def.h"
40 #include "phy.h"
41 #include "dm.h"
42 #include "fw.h"
43 #include "hw.h"
44 #include "sw.h"
45 #include "trx.h"
46 #include "led.h"
47
rtl92s_init_aspm_vars(struct ieee80211_hw * hw)48 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
49 {
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51
52 /*close ASPM for AMD defaultly */
53 rtlpci->const_amdpci_aspm = 0;
54
55 /*
56 * ASPM PS mode.
57 * 0 - Disable ASPM,
58 * 1 - Enable ASPM without Clock Req,
59 * 2 - Enable ASPM with Clock Req,
60 * 3 - Alwyas Enable ASPM with Clock Req,
61 * 4 - Always Enable ASPM without Clock Req.
62 * set defult to RTL8192CE:3 RTL8192E:2
63 * */
64 rtlpci->const_pci_aspm = 2;
65
66 /*Setting for PCI-E device */
67 rtlpci->const_devicepci_aspm_setting = 0x03;
68
69 /*Setting for PCI-E bridge */
70 rtlpci->const_hostpci_aspm_setting = 0x02;
71
72 /*
73 * In Hw/Sw Radio Off situation.
74 * 0 - Default,
75 * 1 - From ASPM setting without low Mac Pwr,
76 * 2 - From ASPM setting with low Mac Pwr,
77 * 3 - Bus D3
78 * set default to RTL8192CE:0 RTL8192SE:2
79 */
80 rtlpci->const_hwsw_rfoff_d3 = 2;
81
82 /*
83 * This setting works for those device with
84 * backdoor ASPM setting such as EPHY setting.
85 * 0 - Not support ASPM,
86 * 1 - Support ASPM,
87 * 2 - According to chipset.
88 */
89 rtlpci->const_support_pciaspm = 2;
90 }
91
rtl92s_init_sw_vars(struct ieee80211_hw * hw)92 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
93 {
94 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96 const struct firmware *firmware;
97 struct rt_firmware *pfirmware = NULL;
98 int err = 0;
99 u16 earlyrxthreshold = 7;
100
101 rtlpriv->dm.dm_initialgain_enable = true;
102 rtlpriv->dm.dm_flag = 0;
103 rtlpriv->dm.disable_framebursting = false;
104 rtlpriv->dm.thermalvalue = 0;
105 rtlpriv->dm.useramask = true;
106
107 /* compatible 5G band 91se just 2.4G band & smsp */
108 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
109 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
110 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
111
112 rtlpci->transmit_config = 0;
113
114 rtlpci->receive_config =
115 RCR_APPFCS |
116 RCR_APWRMGT |
117 /*RCR_ADD3 |*/
118 RCR_AMF |
119 RCR_ADF |
120 RCR_APP_MIC |
121 RCR_APP_ICV |
122 RCR_AICV |
123 /* Accept ICV error, CRC32 Error */
124 RCR_ACRC32 |
125 RCR_AB |
126 /* Accept Broadcast, Multicast */
127 RCR_AM |
128 /* Accept Physical match */
129 RCR_APM |
130 /* Accept Destination Address packets */
131 /*RCR_AAP |*/
132 RCR_APP_PHYST_STAFF |
133 /* Accept PHY status */
134 RCR_APP_PHYST_RXFF |
135 (earlyrxthreshold << RCR_FIFO_OFFSET);
136
137 rtlpci->irq_mask[0] = (u32)
138 (IMR_ROK |
139 IMR_VODOK |
140 IMR_VIDOK |
141 IMR_BEDOK |
142 IMR_BKDOK |
143 IMR_HCCADOK |
144 IMR_MGNTDOK |
145 IMR_COMDOK |
146 IMR_HIGHDOK |
147 IMR_BDOK |
148 IMR_RXCMDOK |
149 /*IMR_TIMEOUT0 |*/
150 IMR_RDU |
151 IMR_RXFOVW |
152 IMR_BCNINT
153 /*| IMR_TXFOVW*/
154 /*| IMR_TBDOK |
155 IMR_TBDER*/);
156
157 rtlpci->irq_mask[1] = (u32) 0;
158
159 rtlpci->shortretry_limit = 0x30;
160 rtlpci->longretry_limit = 0x30;
161
162 rtlpci->first_init = true;
163
164 /* for debug level */
165 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
166 /* for LPS & IPS */
167 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
168 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
169 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
170 if (!rtlpriv->psc.inactiveps)
171 pr_info("rtl8192ce: Power Save off (module option)\n");
172 if (!rtlpriv->psc.fwctrl_lps)
173 pr_info("rtl8192ce: FW Power Save off (module option)\n");
174 rtlpriv->psc.reg_fwctrl_lps = 3;
175 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
176 /* for ASPM, you can close aspm through
177 * set const_support_pciaspm = 0 */
178 rtl92s_init_aspm_vars(hw);
179
180 if (rtlpriv->psc.reg_fwctrl_lps == 1)
181 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
182 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
183 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
184 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
185 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
186
187 /* for firmware buf */
188 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
189 if (!rtlpriv->rtlhal.pfirmware) {
190 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
191 ("Can't alloc buffer for fw.\n"));
192 return 1;
193 }
194
195 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
196 "Loading firmware %s\n", rtlpriv->cfg->fw_name);
197 /* request fw */
198 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
199 rtlpriv->io.dev);
200 if (err) {
201 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
202 ("Failed to request firmware!\n"));
203 return 1;
204 }
205 if (firmware->size > sizeof(struct rt_firmware)) {
206 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
207 ("Firmware is too big!\n"));
208 release_firmware(firmware);
209 return 1;
210 }
211
212 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
213 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
214 pfirmware->sz_fw_tmpbufferlen = firmware->size;
215 release_firmware(firmware);
216
217 return err;
218 }
219
rtl92s_deinit_sw_vars(struct ieee80211_hw * hw)220 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
221 {
222 struct rtl_priv *rtlpriv = rtl_priv(hw);
223
224 if (rtlpriv->rtlhal.pfirmware) {
225 vfree(rtlpriv->rtlhal.pfirmware);
226 rtlpriv->rtlhal.pfirmware = NULL;
227 }
228 }
229
230 static struct rtl_hal_ops rtl8192se_hal_ops = {
231 .init_sw_vars = rtl92s_init_sw_vars,
232 .deinit_sw_vars = rtl92s_deinit_sw_vars,
233 .read_eeprom_info = rtl92se_read_eeprom_info,
234 .interrupt_recognized = rtl92se_interrupt_recognized,
235 .hw_init = rtl92se_hw_init,
236 .hw_disable = rtl92se_card_disable,
237 .hw_suspend = rtl92se_suspend,
238 .hw_resume = rtl92se_resume,
239 .enable_interrupt = rtl92se_enable_interrupt,
240 .disable_interrupt = rtl92se_disable_interrupt,
241 .set_network_type = rtl92se_set_network_type,
242 .set_chk_bssid = rtl92se_set_check_bssid,
243 .set_qos = rtl92se_set_qos,
244 .set_bcn_reg = rtl92se_set_beacon_related_registers,
245 .set_bcn_intv = rtl92se_set_beacon_interval,
246 .update_interrupt_mask = rtl92se_update_interrupt_mask,
247 .get_hw_reg = rtl92se_get_hw_reg,
248 .set_hw_reg = rtl92se_set_hw_reg,
249 .update_rate_tbl = rtl92se_update_hal_rate_tbl,
250 .fill_tx_desc = rtl92se_tx_fill_desc,
251 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
252 .query_rx_desc = rtl92se_rx_query_desc,
253 .set_channel_access = rtl92se_update_channel_access_setting,
254 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
255 .set_bw_mode = rtl92s_phy_set_bw_mode,
256 .switch_channel = rtl92s_phy_sw_chnl,
257 .dm_watchdog = rtl92s_dm_watchdog,
258 .scan_operation_backup = rtl92s_phy_scan_operation_backup,
259 .set_rf_power_state = rtl92s_phy_set_rf_power_state,
260 .led_control = rtl92se_led_control,
261 .set_desc = rtl92se_set_desc,
262 .get_desc = rtl92se_get_desc,
263 .tx_polling = rtl92se_tx_polling,
264 .enable_hw_sec = rtl92se_enable_hw_security_config,
265 .set_key = rtl92se_set_key,
266 .init_sw_leds = rtl92se_init_sw_leds,
267 .get_bbreg = rtl92s_phy_query_bb_reg,
268 .set_bbreg = rtl92s_phy_set_bb_reg,
269 .get_rfreg = rtl92s_phy_query_rf_reg,
270 .set_rfreg = rtl92s_phy_set_rf_reg,
271 };
272
273 static struct rtl_mod_params rtl92se_mod_params = {
274 .sw_crypto = false,
275 .inactiveps = true,
276 .swctrl_lps = true,
277 .fwctrl_lps = false,
278 .debug = DBG_EMERG,
279 };
280
281 /* Because memory R/W bursting will cause system hang/crash
282 * for 92se, so we don't read back after every write action */
283 static struct rtl_hal_cfg rtl92se_hal_cfg = {
284 .bar_id = 1,
285 .write_readback = false,
286 .name = "rtl92s_pci",
287 .fw_name = "rtlwifi/rtl8192sefw.bin",
288 .ops = &rtl8192se_hal_ops,
289 .mod_params = &rtl92se_mod_params,
290
291 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
292 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
293 .maps[SYS_CLK] = SYS_CLKR,
294 .maps[MAC_RCR_AM] = RCR_AM,
295 .maps[MAC_RCR_AB] = RCR_AB,
296 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
297 .maps[MAC_RCR_ACF] = RCR_ACF,
298 .maps[MAC_RCR_AAP] = RCR_AAP,
299
300 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
301 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
302 .maps[EFUSE_CLK] = REG_EFUSE_CLK,
303 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
304 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
305 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
306 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
307 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
308 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
309 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
310 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
311 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
312
313 .maps[RWCAM] = REG_RWCAM,
314 .maps[WCAMI] = REG_WCAMI,
315 .maps[RCAMO] = REG_RCAMO,
316 .maps[CAMDBG] = REG_CAMDBG,
317 .maps[SECR] = REG_SECR,
318 .maps[SEC_CAM_NONE] = CAM_NONE,
319 .maps[SEC_CAM_WEP40] = CAM_WEP40,
320 .maps[SEC_CAM_TKIP] = CAM_TKIP,
321 .maps[SEC_CAM_AES] = CAM_AES,
322 .maps[SEC_CAM_WEP104] = CAM_WEP104,
323
324 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
325 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
326 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
327 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
328 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
329 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
330 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
331 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
332 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
333 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
334 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
335 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
336 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
337 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
338 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
339 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
340
341 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
342 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
343 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
344 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
345 .maps[RTL_IMR_RDU] = IMR_RDU,
346 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
347 .maps[RTL_IMR_BDOK] = IMR_BDOK,
348 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
349 .maps[RTL_IMR_TBDER] = IMR_TBDER,
350 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
351 .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
352 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
353 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
354 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
355 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
356 .maps[RTL_IMR_VODOK] = IMR_VODOK,
357 .maps[RTL_IMR_ROK] = IMR_ROK,
358 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
359
360 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
361 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
362 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
363 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
364 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
365 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
366 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
367 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
368 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
369 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
370 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
371 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
372
373 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
374 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
375 };
376
377 static struct pci_device_id rtl92se_pci_ids[] __devinitdata = {
378 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
379 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
380 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
381 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
382 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
383 {},
384 };
385
386 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
387
388 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
389 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
390 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
391 MODULE_LICENSE("GPL");
392 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
393 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
394
395 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
396 module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
397 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
398 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
399 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
400 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
401 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
402 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
403 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
404 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
405
406 static const struct dev_pm_ops rtlwifi_pm_ops = {
407 .suspend = rtl_pci_suspend,
408 .resume = rtl_pci_resume,
409 .freeze = rtl_pci_suspend,
410 .thaw = rtl_pci_resume,
411 .poweroff = rtl_pci_suspend,
412 .restore = rtl_pci_resume,
413 };
414
415 static struct pci_driver rtl92se_driver = {
416 .name = KBUILD_MODNAME,
417 .id_table = rtl92se_pci_ids,
418 .probe = rtl_pci_probe,
419 .remove = rtl_pci_disconnect,
420 .driver.pm = &rtlwifi_pm_ops,
421 };
422
rtl92se_module_init(void)423 static int __init rtl92se_module_init(void)
424 {
425 int ret = 0;
426
427 ret = pci_register_driver(&rtl92se_driver);
428 if (ret)
429 RT_ASSERT(false, (": No device found\n"));
430
431 return ret;
432 }
433
rtl92se_module_exit(void)434 static void __exit rtl92se_module_exit(void)
435 {
436 pci_unregister_driver(&rtl92se_driver);
437 }
438
439 module_init(rtl92se_module_init);
440 module_exit(rtl92se_module_exit);
441