1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 #ifndef __REALTEK_92S_DEF_H__ 30 #define __REALTEK_92S_DEF_H__ 31 32 #define RX_MPDU_QUEUE 0 33 #define RX_CMD_QUEUE 1 34 #define RX_MAX_QUEUE 2 35 36 #define SHORT_SLOT_TIME 9 37 #define NON_SHORT_SLOT_TIME 20 38 39 /* Rx smooth factor */ 40 #define RX_SMOOTH_FACTOR 20 41 42 /* Queue Select Value in TxDesc */ 43 #define QSLT_BK 0x2 44 #define QSLT_BE 0x0 45 #define QSLT_VI 0x5 46 #define QSLT_VO 0x6 47 #define QSLT_BEACON 0x10 48 #define QSLT_HIGH 0x11 49 #define QSLT_MGNT 0x12 50 #define QSLT_CMD 0x13 51 52 #define PHY_RSSI_SLID_WIN_MAX 100 53 #define PHY_LINKQUALITY_SLID_WIN_MAX 20 54 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10 55 56 /* Tx Desc */ 57 #define TX_DESC_SIZE_RTL8192S (16 * 4) 58 #define TX_CMDDESC_SIZE_RTL8192S (16 * 4) 59 60 /* Define a macro that takes a le32 word, converts it to host ordering, 61 * right shifts by a specified count, creates a mask of the specified 62 * bit count, and extracts that number of bits. 63 */ 64 65 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \ 66 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \ 67 BIT_LEN_MASK_32(__mask)) 68 69 /* Define a macro that clears a bit field in an le32 word and 70 * sets the specified value into that bit field. The resulting 71 * value remains in le32 ordering; however, it is properly converted 72 * to host ordering for the clear and set operations before conversion 73 * back to le32. 74 */ 75 76 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \ 77 (*(__le32 *)(__pdesc) = \ 78 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \ 79 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \ 80 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift))))); 81 82 /* macros to read/write various fields in RX or TX descriptors */ 83 84 /* Dword 0 */ 85 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ 86 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) 87 #define SET_TX_DESC_OFFSET(__pdesc, __val) \ 88 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) 89 #define SET_TX_DESC_TYPE(__pdesc, __val) \ 90 SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) 91 #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ 92 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) 93 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ 94 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) 95 #define SET_TX_DESC_LINIP(__pdesc, __val) \ 96 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) 97 #define SET_TX_DESC_AMSDU(__pdesc, __val) \ 98 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) 99 #define SET_TX_DESC_GREEN_FIELD(__pdesc, __val) \ 100 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) 101 #define SET_TX_DESC_OWN(__pdesc, __val) \ 102 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) 103 104 #define GET_TX_DESC_OWN(__pdesc) \ 105 SHIFT_AND_MASK_LE(__pdesc, 31, 1) 106 107 /* Dword 1 */ 108 #define SET_TX_DESC_MACID(__pdesc, __val) \ 109 SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) 110 #define SET_TX_DESC_MORE_DATA(__pdesc, __val) \ 111 SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val) 112 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ 113 SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val) 114 #define SET_TX_DESC_PIFS(__pdesc, __val) \ 115 SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val) 116 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ 117 SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val) 118 #define SET_TX_DESC_ACK_POLICY(__pdesc, __val) \ 119 SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val) 120 #define SET_TX_DESC_NO_ACM(__pdesc, __val) \ 121 SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) 122 #define SET_TX_DESC_NON_QOS(__pdesc, __val) \ 123 SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val) 124 #define SET_TX_DESC_KEY_ID(__pdesc, __val) \ 125 SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val) 126 #define SET_TX_DESC_OUI(__pdesc, __val) \ 127 SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val) 128 #define SET_TX_DESC_PKT_TYPE(__pdesc, __val) \ 129 SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val) 130 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ 131 SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val) 132 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ 133 SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val) 134 #define SET_TX_DESC_WDS(__pdesc, __val) \ 135 SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) 136 #define SET_TX_DESC_HTC(__pdesc, __val) \ 137 SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) 138 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ 139 SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val) 140 #define SET_TX_DESC_HWPC(__pdesc, __val) \ 141 SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) 142 143 /* Dword 2 */ 144 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ 145 SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val) 146 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ 147 SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val) 148 #define SET_TX_DESC_TSFL(__pdesc, __val) \ 149 SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val) 150 #define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val) \ 151 SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val) 152 #define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val) \ 153 SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val) 154 #define SET_TX_DESC_RSVD_MACID(__pdesc, __val) \ 155 SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val) 156 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ 157 SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val) 158 #define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ 159 SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) 160 #define SET_TX_DESC_OWN_MAC(__pdesc, __val) \ 161 SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val) 162 163 /* Dword 3 */ 164 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ 165 SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val) 166 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ 167 SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val) 168 #define SET_TX_DESC_SEQ(__pdesc, __val) \ 169 SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val) 170 #define SET_TX_DESC_FRAG(__pdesc, __val) \ 171 SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val) 172 173 /* Dword 4 */ 174 #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ 175 SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val) 176 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ 177 SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val) 178 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ 179 SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val) 180 #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val) \ 181 SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val) 182 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ 183 SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val) 184 #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) \ 185 SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val) 186 #define SET_TX_DESC_TXHT(__pdesc, __val) \ 187 SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val) 188 #define SET_TX_DESC_TX_SHORT(__pdesc, __val) \ 189 SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val) 190 #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) \ 191 SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val) 192 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ 193 SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val) 194 #define SET_TX_DESC_TX_STBC(__pdesc, __val) \ 195 SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val) 196 #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) \ 197 SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val) 198 #define SET_TX_DESC_RTS_HT(__pdesc, __val) \ 199 SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val) 200 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ 201 SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val) 202 #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) \ 203 SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val) 204 #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) \ 205 SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val) 206 #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ 207 SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val) 208 #define SET_TX_DESC_USER_RATE(__pdesc, __val) \ 209 SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val) 210 211 /* Dword 5 */ 212 #define SET_TX_DESC_PACKET_ID(__pdesc, __val) \ 213 SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val) 214 #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ 215 SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val) 216 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ 217 SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val) 218 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ 219 SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val) 220 #define SET_TX_DESC_TX_AGC(__pdesc, __val) \ 221 SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val) 222 223 /* Dword 6 */ 224 #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) \ 225 SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val) 226 #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) \ 227 SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val) 228 229 /* Dword 7 */ 230 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ 231 SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val) 232 #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) \ 233 SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val) 234 #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val) \ 235 SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val) 236 237 /* Dword 8 */ 238 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ 239 SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val) 240 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ 241 SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32) 242 243 /* Dword 9 */ 244 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ 245 SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val) 246 247 /* Because the PCI Tx descriptors are chaied at the 248 * initialization and all the NextDescAddresses in 249 * these descriptors cannot not be cleared (,or 250 * driver/HW cannot find the next descriptor), the 251 * offset 36 (NextDescAddresses) is reserved when 252 * the desc is cleared. */ 253 #define TX_DESC_NEXT_DESC_OFFSET 36 254 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ 255 do { \ 256 if (_size > TX_DESC_NEXT_DESC_OFFSET) \ 257 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \ 258 else \ 259 memset(__pdesc, 0, _size); \ 260 } while (0); 261 262 /* Rx Desc */ 263 #define RX_STATUS_DESC_SIZE 24 264 #define RX_DRV_INFO_SIZE_UNIT 8 265 266 /* DWORD 0 */ 267 #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) \ 268 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) 269 #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val) \ 270 SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val) 271 #define SET_RX_STATUS_DESC_ICV(__pdesc, __val) \ 272 SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val) 273 #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) \ 274 SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val) 275 #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) \ 276 SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val) 277 #define SET_RX_STATUS_DESC_QOS(__pdesc, __val) \ 278 SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val) 279 #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) \ 280 SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) 281 #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) \ 282 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) 283 #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) \ 284 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) 285 #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) \ 286 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) 287 #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) \ 288 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) 289 #define SET_RX_STATUS_DESC_EOR(__pdesc, __val) \ 290 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) 291 #define SET_RX_STATUS_DESC_OWN(__pdesc, __val) \ 292 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) 293 294 #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc) \ 295 SHIFT_AND_MASK_LE(__pdesc, 0, 14) 296 #define GET_RX_STATUS_DESC_CRC32(__pdesc) \ 297 SHIFT_AND_MASK_LE(__pdesc, 14, 1) 298 #define GET_RX_STATUS_DESC_ICV(__pdesc) \ 299 SHIFT_AND_MASK_LE(__pdesc, 15, 1) 300 #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) \ 301 SHIFT_AND_MASK_LE(__pdesc, 16, 4) 302 #define GET_RX_STATUS_DESC_SECURITY(__pdesc) \ 303 SHIFT_AND_MASK_LE(__pdesc, 20, 3) 304 #define GET_RX_STATUS_DESC_QOS(__pdesc) \ 305 SHIFT_AND_MASK_LE(__pdesc, 23, 1) 306 #define GET_RX_STATUS_DESC_SHIFT(__pdesc) \ 307 SHIFT_AND_MASK_LE(__pdesc, 24, 2) 308 #define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc) \ 309 SHIFT_AND_MASK_LE(__pdesc, 26, 1) 310 #define GET_RX_STATUS_DESC_SWDEC(__pdesc) \ 311 SHIFT_AND_MASK_LE(__pdesc, 27, 1) 312 #define GET_RX_STATUS_DESC_LAST_SEG(__pdesc) \ 313 SHIFT_AND_MASK_LE(__pdesc, 28, 1) 314 #define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc) \ 315 SHIFT_AND_MASK_LE(__pdesc, 29, 1) 316 #define GET_RX_STATUS_DESC_EOR(__pdesc) \ 317 SHIFT_AND_MASK_LE(__pdesc, 30, 1) 318 #define GET_RX_STATUS_DESC_OWN(__pdesc) \ 319 SHIFT_AND_MASK_LE(__pdesc, 31, 1) 320 321 /* DWORD 1 */ 322 #define SET_RX_STATUS_DESC_MACID(__pdesc, __val) \ 323 SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) 324 #define SET_RX_STATUS_DESC_TID(__pdesc, __val) \ 325 SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val) 326 #define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val) \ 327 SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val) 328 #define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val) \ 329 SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) 330 #define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val) \ 331 SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val) 332 #define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val) \ 333 SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val) 334 #define SET_RX_STATUS_DESC_PAM(__pdesc, __val) \ 335 SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) 336 #define SET_RX_STATUS_DESC_PWR(__pdesc, __val) \ 337 SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) 338 #define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val) \ 339 SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val) 340 #define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val) \ 341 SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) 342 #define SET_RX_STATUS_DESC_TYPE(__pdesc, __val) \ 343 SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val) 344 #define SET_RX_STATUS_DESC_MC(__pdesc, __val) \ 345 SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val) 346 #define SET_RX_STATUS_DESC_BC(__pdesc, __val) \ 347 SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val) 348 349 #define GET_RX_STATUS_DEC_MACID(__pdesc) \ 350 SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5) 351 #define GET_RX_STATUS_DESC_TID(__pdesc) \ 352 SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4) 353 #define GET_RX_STATUS_DESC_PAGGR(__pdesc) \ 354 SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1) 355 #define GET_RX_STATUS_DESC_FAGGR(__pdesc) \ 356 SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1) 357 #define GET_RX_STATUS_DESC_A1_FIT(__pdesc) \ 358 SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4) 359 #define GET_RX_STATUS_DESC_A2_FIT(__pdesc) \ 360 SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4) 361 #define GET_RX_STATUS_DESC_PAM(__pdesc) \ 362 SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1) 363 #define GET_RX_STATUS_DESC_PWR(__pdesc) \ 364 SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1) 365 #define GET_RX_STATUS_DESC_MORE_DATA(__pdesc) \ 366 SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1) 367 #define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc) \ 368 SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1) 369 #define GET_RX_STATUS_DESC_TYPE(__pdesc) \ 370 SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2) 371 #define GET_RX_STATUS_DESC_MC(__pdesc) \ 372 SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1) 373 #define GET_RX_STATUS_DESC_BC(__pdesc) \ 374 SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1) 375 376 /* DWORD 2 */ 377 #define SET_RX_STATUS_DESC_SEQ(__pdesc, __val) \ 378 SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val) 379 #define SET_RX_STATUS_DESC_FRAG(__pdesc, __val) \ 380 SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val) 381 #define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val) \ 382 SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val) 383 #define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val) \ 384 SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) 385 386 #define GET_RX_STATUS_DESC_SEQ(__pdesc) \ 387 SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12) 388 #define GET_RX_STATUS_DESC_FRAG(__pdesc) \ 389 SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4) 390 #define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc) \ 391 SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8) 392 #define GET_RX_STATUS_DESC_NEXT_IND(__pdesc) \ 393 SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1) 394 395 /* DWORD 3 */ 396 #define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val) \ 397 SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val) 398 #define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val) \ 399 SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val) 400 #define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val) \ 401 SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val) 402 #define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val) \ 403 SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val) 404 #define SET_RX_STATUS_DESC_BW(__pdesc, __val) \ 405 SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val) 406 #define SET_RX_STATUS_DESC_HTC(__pdesc, __val) \ 407 SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val) 408 #define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val) \ 409 SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val) 410 #define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val) \ 411 SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val) 412 #define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val) \ 413 SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val) 414 #define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val) \ 415 SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val) 416 #define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val) \ 417 SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val) 418 #define SET_RX_STATUS_DESC_IV0(__pdesc, __val) \ 419 SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val) 420 421 #define GET_RX_STATUS_DESC_RX_MCS(__pdesc) \ 422 SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6) 423 #define GET_RX_STATUS_DESC_RX_HT(__pdesc) \ 424 SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1) 425 #define GET_RX_STATUS_DESC_AMSDU(__pdesc) \ 426 SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1) 427 #define GET_RX_STATUS_DESC_SPLCP(__pdesc) \ 428 SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1) 429 #define GET_RX_STATUS_DESC_BW(__pdesc) \ 430 SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1) 431 #define GET_RX_STATUS_DESC_HTC(__pdesc) \ 432 SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1) 433 #define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc) \ 434 SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1) 435 #define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc) \ 436 SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1) 437 #define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc) \ 438 SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1) 439 #define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc) \ 440 SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1) 441 #define GET_RX_STATUS_DESC_HWPC_IND(__pdesc) \ 442 SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1) 443 #define GET_RX_STATUS_DESC_IV0(__pdesc) \ 444 SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16) 445 446 /* DWORD 4 */ 447 #define SET_RX_STATUS_DESC_IV1(__pdesc, __val) \ 448 SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val) 449 #define GET_RX_STATUS_DESC_IV1(__pdesc) \ 450 SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32) 451 452 /* DWORD 5 */ 453 #define SET_RX_STATUS_DESC_TSFL(__pdesc, __val) \ 454 SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val) 455 #define GET_RX_STATUS_DESC_TSFL(__pdesc) \ 456 SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32) 457 458 /* DWORD 6 */ 459 #define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val) \ 460 SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val) 461 462 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\ 463 (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE1M || \ 464 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE2M || \ 465 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE5_5M ||\ 466 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE11M) 467 468 enum rf_optype { 469 RF_OP_BY_SW_3WIRE = 0, 470 RF_OP_BY_FW, 471 RF_OP_MAX 472 }; 473 474 enum ic_inferiority { 475 IC_INFERIORITY_A = 0, 476 IC_INFERIORITY_B = 1, 477 }; 478 479 enum fwcmd_iotype { 480 /* For DIG DM */ 481 FW_CMD_DIG_ENABLE = 0, 482 FW_CMD_DIG_DISABLE = 1, 483 FW_CMD_DIG_HALT = 2, 484 FW_CMD_DIG_RESUME = 3, 485 /* For High Power DM */ 486 FW_CMD_HIGH_PWR_ENABLE = 4, 487 FW_CMD_HIGH_PWR_DISABLE = 5, 488 /* For Rate adaptive DM */ 489 FW_CMD_RA_RESET = 6, 490 FW_CMD_RA_ACTIVE = 7, 491 FW_CMD_RA_REFRESH_N = 8, 492 FW_CMD_RA_REFRESH_BG = 9, 493 FW_CMD_RA_INIT = 10, 494 /* For FW supported IQK */ 495 FW_CMD_IQK_INIT = 11, 496 /* Tx power tracking switch, 497 * MP driver only */ 498 FW_CMD_TXPWR_TRACK_ENABLE = 12, 499 /* Tx power tracking switch, 500 * MP driver only */ 501 FW_CMD_TXPWR_TRACK_DISABLE = 13, 502 /* Tx power tracking with thermal 503 * indication, for Normal driver */ 504 FW_CMD_TXPWR_TRACK_THERMAL = 14, 505 FW_CMD_PAUSE_DM_BY_SCAN = 15, 506 FW_CMD_RESUME_DM_BY_SCAN = 16, 507 FW_CMD_RA_REFRESH_N_COMB = 17, 508 FW_CMD_RA_REFRESH_BG_COMB = 18, 509 FW_CMD_ANTENNA_SW_ENABLE = 19, 510 FW_CMD_ANTENNA_SW_DISABLE = 20, 511 /* Tx Status report for CCX from FW */ 512 FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21, 513 /* Indifate firmware that driver 514 * enters LPS, For PS-Poll issue */ 515 FW_CMD_LPS_ENTER = 22, 516 /* Indicate firmware that driver 517 * leave LPS*/ 518 FW_CMD_LPS_LEAVE = 23, 519 /* Set DIG mode to signal strength */ 520 FW_CMD_DIG_MODE_SS = 24, 521 /* Set DIG mode to false alarm. */ 522 FW_CMD_DIG_MODE_FA = 25, 523 FW_CMD_ADD_A2_ENTRY = 26, 524 FW_CMD_CTRL_DM_BY_DRIVER = 27, 525 FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28, 526 FW_CMD_PAPE_CONTROL = 29, 527 FW_CMD_IQK_ENABLE = 30, 528 }; 529 530 /* 531 * Driver info contain PHY status 532 * and other variabel size info 533 * PHY Status content as below 534 */ 535 struct rx_fwinfo { 536 /* DWORD 0 */ 537 u8 gain_trsw[4]; 538 /* DWORD 1 */ 539 u8 pwdb_all; 540 u8 cfosho[4]; 541 /* DWORD 2 */ 542 u8 cfotail[4]; 543 /* DWORD 3 */ 544 s8 rxevm[2]; 545 s8 rxsnr[4]; 546 /* DWORD 4 */ 547 u8 pdsnr[2]; 548 /* DWORD 5 */ 549 u8 csi_current[2]; 550 u8 csi_target[2]; 551 /* DWORD 6 */ 552 u8 sigevm; 553 u8 max_ex_pwr; 554 u8 ex_intf_flag:1; 555 u8 sgi_en:1; 556 u8 rxsc:2; 557 u8 reserve:4; 558 }; 559 560 struct phy_sts_cck_8192s_t { 561 u8 adc_pwdb_x[4]; 562 u8 sq_rpt; 563 u8 cck_agc_rpt; 564 }; 565 566 #endif 567 568