1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/vmalloc.h>
33 #include <linux/module.h>
34
35 #include "../wifi.h"
36 #include "../core.h"
37 #include "../pci.h"
38 #include "reg.h"
39 #include "def.h"
40 #include "phy.h"
41 #include "dm.h"
42 #include "hw.h"
43 #include "sw.h"
44 #include "trx.h"
45 #include "led.h"
46
rtl92d_init_aspm_vars(struct ieee80211_hw * hw)47 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
48 {
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 /*close ASPM for AMD defaultly */
52 rtlpci->const_amdpci_aspm = 0;
53
54 /*
55 * ASPM PS mode.
56 * 0 - Disable ASPM,
57 * 1 - Enable ASPM without Clock Req,
58 * 2 - Enable ASPM with Clock Req,
59 * 3 - Alwyas Enable ASPM with Clock Req,
60 * 4 - Always Enable ASPM without Clock Req.
61 * set defult to RTL8192CE:3 RTL8192E:2
62 * */
63 rtlpci->const_pci_aspm = 3;
64
65 /*Setting for PCI-E device */
66 rtlpci->const_devicepci_aspm_setting = 0x03;
67
68 /*Setting for PCI-E bridge */
69 rtlpci->const_hostpci_aspm_setting = 0x02;
70
71 /*
72 * In Hw/Sw Radio Off situation.
73 * 0 - Default,
74 * 1 - From ASPM setting without low Mac Pwr,
75 * 2 - From ASPM setting with low Mac Pwr,
76 * 3 - Bus D3
77 * set default to RTL8192CE:0 RTL8192SE:2
78 */
79 rtlpci->const_hwsw_rfoff_d3 = 0;
80
81 /*
82 * This setting works for those device with
83 * backdoor ASPM setting such as EPHY setting.
84 * 0 - Not support ASPM,
85 * 1 - Support ASPM,
86 * 2 - According to chipset.
87 */
88 rtlpci->const_support_pciaspm = 1;
89 }
90
rtl92d_init_sw_vars(struct ieee80211_hw * hw)91 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
92 {
93 int err;
94 u8 tid;
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
97 const struct firmware *firmware;
98 static int header_print;
99
100 rtlpriv->dm.dm_initialgain_enable = true;
101 rtlpriv->dm.dm_flag = 0;
102 rtlpriv->dm.disable_framebursting = false;
103 rtlpriv->dm.thermalvalue = 0;
104 rtlpriv->dm.useramask = true;
105
106 /* dual mac */
107 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
108 rtlpriv->phy.current_channel = 36;
109 else
110 rtlpriv->phy.current_channel = 1;
111
112 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
113 rtlpriv->rtlhal.disable_amsdu_8k = true;
114 /* No long RX - reduce fragmentation */
115 rtlpci->rxbuffersize = 4096;
116 }
117
118 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
119
120 rtlpci->receive_config = (
121 RCR_APPFCS
122 | RCR_AMF
123 | RCR_ADF
124 | RCR_APP_MIC
125 | RCR_APP_ICV
126 | RCR_AICV
127 | RCR_ACRC32
128 | RCR_AB
129 | RCR_AM
130 | RCR_APM
131 | RCR_APP_PHYST_RXFF
132 | RCR_HTC_LOC_CTRL
133 );
134
135 rtlpci->irq_mask[0] = (u32) (
136 IMR_ROK
137 | IMR_VODOK
138 | IMR_VIDOK
139 | IMR_BEDOK
140 | IMR_BKDOK
141 | IMR_MGNTDOK
142 | IMR_HIGHDOK
143 | IMR_BDOK
144 | IMR_RDU
145 | IMR_RXFOVW
146 );
147
148 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
149
150 /* for debug level */
151 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
152 /* for LPS & IPS */
153 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
154 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
155 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
156 if (!rtlpriv->psc.inactiveps)
157 pr_info("rtl8192ce: Power Save off (module option)\n");
158 if (!rtlpriv->psc.fwctrl_lps)
159 pr_info("rtl8192ce: FW Power Save off (module option)\n");
160 rtlpriv->psc.reg_fwctrl_lps = 3;
161 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
162 /* for ASPM, you can close aspm through
163 * set const_support_pciaspm = 0 */
164 rtl92d_init_aspm_vars(hw);
165
166 if (rtlpriv->psc.reg_fwctrl_lps == 1)
167 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
168 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
169 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
170 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
171 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
172
173 /* for firmware buf */
174 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
175 if (!rtlpriv->rtlhal.pfirmware) {
176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
177 ("Can't alloc buffer for fw.\n"));
178 return 1;
179 }
180
181 if (!header_print) {
182 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
183 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
184 header_print++;
185 }
186 /* request fw */
187 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
188 rtlpriv->io.dev);
189 if (err) {
190 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
191 ("Failed to request firmware!\n"));
192 return 1;
193 }
194 if (firmware->size > 0x8000) {
195 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
196 ("Firmware is too big!\n"));
197 release_firmware(firmware);
198 return 1;
199 }
200 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
201 rtlpriv->rtlhal.fwsize = firmware->size;
202 release_firmware(firmware);
203
204 /* for early mode */
205 rtlpriv->rtlhal.earlymode_enable = true;
206 for (tid = 0; tid < 8; tid++)
207 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
208 return 0;
209 }
210
rtl92d_deinit_sw_vars(struct ieee80211_hw * hw)211 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
212 {
213 struct rtl_priv *rtlpriv = rtl_priv(hw);
214 u8 tid;
215
216 if (rtlpriv->rtlhal.pfirmware) {
217 vfree(rtlpriv->rtlhal.pfirmware);
218 rtlpriv->rtlhal.pfirmware = NULL;
219 }
220 for (tid = 0; tid < 8; tid++)
221 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
222 }
223
224 static struct rtl_hal_ops rtl8192de_hal_ops = {
225 .init_sw_vars = rtl92d_init_sw_vars,
226 .deinit_sw_vars = rtl92d_deinit_sw_vars,
227 .read_eeprom_info = rtl92de_read_eeprom_info,
228 .interrupt_recognized = rtl92de_interrupt_recognized,
229 .hw_init = rtl92de_hw_init,
230 .hw_disable = rtl92de_card_disable,
231 .hw_suspend = rtl92de_suspend,
232 .hw_resume = rtl92de_resume,
233 .enable_interrupt = rtl92de_enable_interrupt,
234 .disable_interrupt = rtl92de_disable_interrupt,
235 .set_network_type = rtl92de_set_network_type,
236 .set_chk_bssid = rtl92de_set_check_bssid,
237 .set_qos = rtl92de_set_qos,
238 .set_bcn_reg = rtl92de_set_beacon_related_registers,
239 .set_bcn_intv = rtl92de_set_beacon_interval,
240 .update_interrupt_mask = rtl92de_update_interrupt_mask,
241 .get_hw_reg = rtl92de_get_hw_reg,
242 .set_hw_reg = rtl92de_set_hw_reg,
243 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
244 .fill_tx_desc = rtl92de_tx_fill_desc,
245 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
246 .query_rx_desc = rtl92de_rx_query_desc,
247 .set_channel_access = rtl92de_update_channel_access_setting,
248 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
249 .set_bw_mode = rtl92d_phy_set_bw_mode,
250 .switch_channel = rtl92d_phy_sw_chnl,
251 .dm_watchdog = rtl92d_dm_watchdog,
252 .scan_operation_backup = rtl92d_phy_scan_operation_backup,
253 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
254 .led_control = rtl92de_led_control,
255 .set_desc = rtl92de_set_desc,
256 .get_desc = rtl92de_get_desc,
257 .tx_polling = rtl92de_tx_polling,
258 .enable_hw_sec = rtl92de_enable_hw_security_config,
259 .set_key = rtl92de_set_key,
260 .init_sw_leds = rtl92de_init_sw_leds,
261 .get_bbreg = rtl92d_phy_query_bb_reg,
262 .set_bbreg = rtl92d_phy_set_bb_reg,
263 .get_rfreg = rtl92d_phy_query_rf_reg,
264 .set_rfreg = rtl92d_phy_set_rf_reg,
265 .linked_set_reg = rtl92d_linked_set_reg,
266 };
267
268 static struct rtl_mod_params rtl92de_mod_params = {
269 .sw_crypto = false,
270 .inactiveps = true,
271 .swctrl_lps = true,
272 .fwctrl_lps = false,
273 .debug = DBG_EMERG,
274 };
275
276 static struct rtl_hal_cfg rtl92de_hal_cfg = {
277 .bar_id = 2,
278 .write_readback = true,
279 .name = "rtl8192de",
280 .fw_name = "rtlwifi/rtl8192defw.bin",
281 .ops = &rtl8192de_hal_ops,
282 .mod_params = &rtl92de_mod_params,
283
284 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
285 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
286 .maps[SYS_CLK] = REG_SYS_CLKR,
287 .maps[MAC_RCR_AM] = RCR_AM,
288 .maps[MAC_RCR_AB] = RCR_AB,
289 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
290 .maps[MAC_RCR_ACF] = RCR_ACF,
291 .maps[MAC_RCR_AAP] = RCR_AAP,
292
293 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
294 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
295 .maps[EFUSE_CLK] = 0, /* just for 92se */
296 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
297 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
298 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
299 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
300 .maps[EFUSE_ANA8M] = 0, /* just for 92se */
301 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
302 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
303 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
304
305 .maps[RWCAM] = REG_CAMCMD,
306 .maps[WCAMI] = REG_CAMWRITE,
307 .maps[RCAMO] = REG_CAMREAD,
308 .maps[CAMDBG] = REG_CAMDBG,
309 .maps[SECR] = REG_SECCFG,
310 .maps[SEC_CAM_NONE] = CAM_NONE,
311 .maps[SEC_CAM_WEP40] = CAM_WEP40,
312 .maps[SEC_CAM_TKIP] = CAM_TKIP,
313 .maps[SEC_CAM_AES] = CAM_AES,
314 .maps[SEC_CAM_WEP104] = CAM_WEP104,
315
316 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
317 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
318 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
319 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
320 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
321 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
322 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
323 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
324 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
325 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
326 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
327 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
328 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
329 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
330 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
331 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
332
333 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
334 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
335 .maps[RTL_IMR_BcnInt] = IMR_BcnInt,
336 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
337 .maps[RTL_IMR_RDU] = IMR_RDU,
338 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
339 .maps[RTL_IMR_BDOK] = IMR_BDOK,
340 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
341 .maps[RTL_IMR_TBDER] = IMR_TBDER,
342 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
343 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
344 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
345 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
346 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
347 .maps[RTL_IMR_VODOK] = IMR_VODOK,
348 .maps[RTL_IMR_ROK] = IMR_ROK,
349 .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER),
350
351 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
352 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
353 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
354 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
355 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
356 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
357 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
358 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
359 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
360 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
361 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
362 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
363
364 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
365 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
366 };
367
368 static struct pci_device_id rtl92de_pci_ids[] __devinitdata = {
369 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
370 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
371 {},
372 };
373
374 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
375
376 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
377 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
378 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
379 MODULE_LICENSE("GPL");
380 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
381 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
382
383 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
384 module_param_named(debug, rtl92de_mod_params.debug, int, 0444);
385 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
386 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
387 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
388 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
389 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
390 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
391 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
392 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
393
394 static const struct dev_pm_ops rtlwifi_pm_ops = {
395 .suspend = rtl_pci_suspend,
396 .resume = rtl_pci_resume,
397 .freeze = rtl_pci_suspend,
398 .thaw = rtl_pci_resume,
399 .poweroff = rtl_pci_suspend,
400 .restore = rtl_pci_resume,
401 };
402
403 static struct pci_driver rtl92de_driver = {
404 .name = KBUILD_MODNAME,
405 .id_table = rtl92de_pci_ids,
406 .probe = rtl_pci_probe,
407 .remove = rtl_pci_disconnect,
408 .driver.pm = &rtlwifi_pm_ops,
409 };
410
411 /* add global spin lock to solve the problem that
412 * Dul mac register operation on the same time */
413 spinlock_t globalmutex_power;
414 spinlock_t globalmutex_for_fwdownload;
415 spinlock_t globalmutex_for_power_and_efuse;
416
rtl92de_module_init(void)417 static int __init rtl92de_module_init(void)
418 {
419 int ret = 0;
420
421 spin_lock_init(&globalmutex_power);
422 spin_lock_init(&globalmutex_for_fwdownload);
423 spin_lock_init(&globalmutex_for_power_and_efuse);
424
425 ret = pci_register_driver(&rtl92de_driver);
426 if (ret)
427 RT_ASSERT(false, (": No device found\n"));
428 return ret;
429 }
430
rtl92de_module_exit(void)431 static void __exit rtl92de_module_exit(void)
432 {
433 pci_unregister_driver(&rtl92de_driver);
434 }
435
436 module_init(rtl92de_module_init);
437 module_exit(rtl92de_module_exit);
438