1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #ifndef __RTL92C_DM_H__ 31 #define __RTL92C_DM_H__ 32 33 #define HAL_DM_DIG_DISABLE BIT(0) 34 #define HAL_DM_HIPWR_DISABLE BIT(1) 35 36 #define OFDM_TABLE_LENGTH 37 37 #define CCK_TABLE_LENGTH 33 38 39 #define OFDM_TABLE_SIZE 37 40 #define CCK_TABLE_SIZE 33 41 42 #define BW_AUTO_SWITCH_HIGH_LOW 25 43 #define BW_AUTO_SWITCH_LOW_HIGH 30 44 45 #define DM_DIG_THRESH_HIGH 40 46 #define DM_DIG_THRESH_LOW 35 47 48 #define DM_FALSEALARM_THRESH_LOW 400 49 #define DM_FALSEALARM_THRESH_HIGH 1000 50 51 #define DM_DIG_MAX 0x3e 52 #define DM_DIG_MIN 0x1e 53 54 #define DM_DIG_FA_UPPER 0x32 55 #define DM_DIG_FA_LOWER 0x20 56 #define DM_DIG_FA_TH0 0x20 57 #define DM_DIG_FA_TH1 0x100 58 #define DM_DIG_FA_TH2 0x200 59 60 #define DM_DIG_BACKOFF_MAX 12 61 #define DM_DIG_BACKOFF_MIN -4 62 #define DM_DIG_BACKOFF_DEFAULT 10 63 64 #define RXPATHSELECTION_SS_TH_lOW 30 65 #define RXPATHSELECTION_DIFF_TH 18 66 67 #define DM_RATR_STA_INIT 0 68 #define DM_RATR_STA_HIGH 1 69 #define DM_RATR_STA_MIDDLE 2 70 #define DM_RATR_STA_LOW 3 71 72 #define CTS2SELF_THVAL 30 73 #define REGC38_TH 20 74 75 #define WAIOTTHVal 25 76 77 #define TXHIGHPWRLEVEL_NORMAL 0 78 #define TXHIGHPWRLEVEL_LEVEL1 1 79 #define TXHIGHPWRLEVEL_LEVEL2 2 80 #define TXHIGHPWRLEVEL_BT1 3 81 #define TXHIGHPWRLEVEL_BT2 4 82 83 #define DM_TYPE_BYFW 0 84 #define DM_TYPE_BYDRIVER 1 85 86 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 87 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 88 89 struct ps_t { 90 u8 pre_ccastate; 91 u8 cur_ccasate; 92 u8 pre_rfstate; 93 u8 cur_rfstate; 94 long rssi_val_min; 95 }; 96 97 struct dig_t { 98 u8 dig_enable_flag; 99 u8 dig_ext_port_stage; 100 u32 rssi_lowthresh; 101 u32 rssi_highthresh; 102 u32 fa_lowthresh; 103 u32 fa_highthresh; 104 u8 cursta_connectctate; 105 u8 presta_connectstate; 106 u8 curmultista_connectstate; 107 u8 pre_igvalue; 108 u8 cur_igvalue; 109 char backoff_val; 110 char backoff_val_range_max; 111 char backoff_val_range_min; 112 u8 rx_gain_range_max; 113 u8 rx_gain_range_min; 114 u8 rssi_val_min; 115 u8 pre_cck_pd_state; 116 u8 cur_cck_pd_state; 117 u8 pre_cck_fa_state; 118 u8 cur_cck_fa_state; 119 u8 pre_ccastate; 120 u8 cur_ccasate; 121 }; 122 123 struct swat_t { 124 u8 failure_cnt; 125 u8 try_flag; 126 u8 stop_trying; 127 long pre_rssi; 128 long trying_threshold; 129 u8 cur_antenna; 130 u8 pre_antenna; 131 }; 132 133 enum tag_dynamic_init_gain_operation_type_definition { 134 DIG_TYPE_THRESH_HIGH = 0, 135 DIG_TYPE_THRESH_LOW = 1, 136 DIG_TYPE_BACKOFF = 2, 137 DIG_TYPE_RX_GAIN_MIN = 3, 138 DIG_TYPE_RX_GAIN_MAX = 4, 139 DIG_TYPE_ENABLE = 5, 140 DIG_TYPE_DISABLE = 6, 141 DIG_OP_TYPE_MAX 142 }; 143 144 enum tag_cck_packet_detection_threshold_type_definition { 145 CCK_PD_STAGE_LowRssi = 0, 146 CCK_PD_STAGE_HighRssi = 1, 147 CCK_FA_STAGE_Low = 2, 148 CCK_FA_STAGE_High = 3, 149 CCK_PD_STAGE_MAX = 4, 150 }; 151 152 enum dm_1r_cca_e { 153 CCA_1R = 0, 154 CCA_2R = 1, 155 CCA_MAX = 2, 156 }; 157 158 enum dm_rf_e { 159 RF_SAVE = 0, 160 RF_NORMAL = 1, 161 RF_MAX = 2, 162 }; 163 164 enum dm_sw_ant_switch_e { 165 ANS_ANTENNA_B = 1, 166 ANS_ANTENNA_A = 2, 167 ANS_ANTENNA_MAX = 3, 168 }; 169 170 enum dm_dig_ext_port_alg_e { 171 DIG_EXT_PORT_STAGE_0 = 0, 172 DIG_EXT_PORT_STAGE_1 = 1, 173 DIG_EXT_PORT_STAGE_2 = 2, 174 DIG_EXT_PORT_STAGE_3 = 3, 175 DIG_EXT_PORT_STAGE_MAX = 4, 176 }; 177 178 enum dm_dig_connect_e { 179 DIG_STA_DISCONNECT = 0, 180 DIG_STA_CONNECT = 1, 181 DIG_STA_BEFORE_CONNECT = 2, 182 DIG_MULTISTA_DISCONNECT = 3, 183 DIG_MULTISTA_CONNECT = 4, 184 DIG_CONNECT_MAX 185 }; 186 187 extern struct dig_t dm_digtable; 188 void rtl92c_dm_init(struct ieee80211_hw *hw); 189 void rtl92c_dm_watchdog(struct ieee80211_hw *hw); 190 void rtl92c_dm_write_dig(struct ieee80211_hw *hw); 191 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw); 192 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw); 193 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 194 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 195 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw); 196 void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw); 197 198 #endif 199