1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #ifndef __RTL92COMMON_DM_H__ 31 #define __RTL92COMMON_DM_H__ 32 33 #include "../wifi.h" 34 #include "../rtl8192ce/def.h" 35 #include "../rtl8192ce/reg.h" 36 #include "fw_common.h" 37 38 #define HAL_DM_DIG_DISABLE BIT(0) 39 #define HAL_DM_HIPWR_DISABLE BIT(1) 40 41 #define OFDM_TABLE_LENGTH 37 42 #define CCK_TABLE_LENGTH 33 43 44 #define OFDM_TABLE_SIZE 37 45 #define CCK_TABLE_SIZE 33 46 47 #define BW_AUTO_SWITCH_HIGH_LOW 25 48 #define BW_AUTO_SWITCH_LOW_HIGH 30 49 50 #define DM_DIG_THRESH_HIGH 40 51 #define DM_DIG_THRESH_LOW 35 52 53 #define DM_FALSEALARM_THRESH_LOW 400 54 #define DM_FALSEALARM_THRESH_HIGH 1000 55 56 #define DM_DIG_MAX 0x3e 57 #define DM_DIG_MIN 0x1e 58 59 #define DM_DIG_FA_UPPER 0x32 60 #define DM_DIG_FA_LOWER 0x20 61 #define DM_DIG_FA_TH0 0x20 62 #define DM_DIG_FA_TH1 0x100 63 #define DM_DIG_FA_TH2 0x200 64 65 #define DM_DIG_BACKOFF_MAX 12 66 #define DM_DIG_BACKOFF_MIN -4 67 #define DM_DIG_BACKOFF_DEFAULT 10 68 69 #define RXPATHSELECTION_SS_TH_lOW 30 70 #define RXPATHSELECTION_DIFF_TH 18 71 72 #define DM_RATR_STA_INIT 0 73 #define DM_RATR_STA_HIGH 1 74 #define DM_RATR_STA_MIDDLE 2 75 #define DM_RATR_STA_LOW 3 76 77 #define CTS2SELF_THVAL 30 78 #define REGC38_TH 20 79 80 #define WAIOTTHVal 25 81 82 #define TXHIGHPWRLEVEL_NORMAL 0 83 #define TXHIGHPWRLEVEL_LEVEL1 1 84 #define TXHIGHPWRLEVEL_LEVEL2 2 85 #define TXHIGHPWRLEVEL_BT1 3 86 #define TXHIGHPWRLEVEL_BT2 4 87 88 #define DM_TYPE_BYFW 0 89 #define DM_TYPE_BYDRIVER 1 90 91 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 92 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 93 94 struct ps_t { 95 u8 pre_ccastate; 96 u8 cur_ccasate; 97 u8 pre_rfstate; 98 u8 cur_rfstate; 99 long rssi_val_min; 100 }; 101 102 struct dig_t { 103 u8 dig_enable_flag; 104 u8 dig_ext_port_stage; 105 u32 rssi_lowthresh; 106 u32 rssi_highthresh; 107 u32 fa_lowthresh; 108 u32 fa_highthresh; 109 u8 cursta_connectctate; 110 u8 presta_connectstate; 111 u8 curmultista_connectstate; 112 u8 pre_igvalue; 113 u8 cur_igvalue; 114 char backoff_val; 115 char backoff_val_range_max; 116 char backoff_val_range_min; 117 u8 rx_gain_range_max; 118 u8 rx_gain_range_min; 119 u8 rssi_val_min; 120 u8 pre_cck_pd_state; 121 u8 cur_cck_pd_state; 122 u8 pre_cck_fa_state; 123 u8 cur_cck_fa_state; 124 u8 pre_ccastate; 125 u8 cur_ccasate; 126 }; 127 128 struct swat_t { 129 u8 failure_cnt; 130 u8 try_flag; 131 u8 stop_trying; 132 long pre_rssi; 133 long trying_threshold; 134 u8 cur_antenna; 135 u8 pre_antenna; 136 }; 137 138 enum tag_dynamic_init_gain_operation_type_definition { 139 DIG_TYPE_THRESH_HIGH = 0, 140 DIG_TYPE_THRESH_LOW = 1, 141 DIG_TYPE_BACKOFF = 2, 142 DIG_TYPE_RX_GAIN_MIN = 3, 143 DIG_TYPE_RX_GAIN_MAX = 4, 144 DIG_TYPE_ENABLE = 5, 145 DIG_TYPE_DISABLE = 6, 146 DIG_OP_TYPE_MAX 147 }; 148 149 enum tag_cck_packet_detection_threshold_type_definition { 150 CCK_PD_STAGE_LowRssi = 0, 151 CCK_PD_STAGE_HighRssi = 1, 152 CCK_FA_STAGE_Low = 2, 153 CCK_FA_STAGE_High = 3, 154 CCK_PD_STAGE_MAX = 4, 155 }; 156 157 enum dm_1r_cca_e { 158 CCA_1R = 0, 159 CCA_2R = 1, 160 CCA_MAX = 2, 161 }; 162 163 enum dm_rf_e { 164 RF_SAVE = 0, 165 RF_NORMAL = 1, 166 RF_MAX = 2, 167 }; 168 169 enum dm_sw_ant_switch_e { 170 ANS_ANTENNA_B = 1, 171 ANS_ANTENNA_A = 2, 172 ANS_ANTENNA_MAX = 3, 173 }; 174 175 enum dm_dig_ext_port_alg_e { 176 DIG_EXT_PORT_STAGE_0 = 0, 177 DIG_EXT_PORT_STAGE_1 = 1, 178 DIG_EXT_PORT_STAGE_2 = 2, 179 DIG_EXT_PORT_STAGE_3 = 3, 180 DIG_EXT_PORT_STAGE_MAX = 4, 181 }; 182 183 enum dm_dig_connect_e { 184 DIG_STA_DISCONNECT = 0, 185 DIG_STA_CONNECT = 1, 186 DIG_STA_BEFORE_CONNECT = 2, 187 DIG_MULTISTA_DISCONNECT = 3, 188 DIG_MULTISTA_CONNECT = 4, 189 DIG_CONNECT_MAX 190 }; 191 192 extern struct dig_t dm_digtable; 193 void rtl92c_dm_init(struct ieee80211_hw *hw); 194 void rtl92c_dm_watchdog(struct ieee80211_hw *hw); 195 void rtl92c_dm_write_dig(struct ieee80211_hw *hw); 196 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw); 197 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw); 198 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 199 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 200 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta); 201 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw); 202 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery); 203 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw); 204 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw); 205 206 #endif 207