1 /*
2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28 /*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
47 #include "rt2800.h"
48 #include "rt2800pci.h"
49
50 /*
51 * Allow hardware encryption to be disabled.
52 */
53 static bool modparam_nohwcrypt = false;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
rt2800pci_mcu_status(struct rt2x00_dev * rt2x00dev,const u8 token)57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58 {
59 unsigned int i;
60 u32 reg;
61
62 /*
63 * SOC devices don't support MCU requests.
64 */
65 if (rt2x00_is_soc(rt2x00dev))
66 return;
67
68 for (i = 0; i < 200; i++) {
69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
70
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75 break;
76
77 udelay(REGISTER_BUSY_DELAY);
78 }
79
80 if (i == 200)
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85 }
86
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
rt2800pci_read_eeprom_soc(struct rt2x00_dev * rt2x00dev)88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89 {
90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94 iounmap(base_addr);
95 }
96 #else
rt2800pci_read_eeprom_soc(struct rt2x00_dev * rt2x00dev)97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98 {
99 }
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
101
102 #ifdef CONFIG_PCI
rt2800pci_eepromregister_read(struct eeprom_93cx6 * eeprom)103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104 {
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
106 u32 reg;
107
108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
109
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116 }
117
rt2800pci_eepromregister_write(struct eeprom_93cx6 * eeprom)118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119 {
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
121 u32 reg = 0;
122
123 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
129
130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
131 }
132
rt2800pci_read_eeprom_pci(struct rt2x00_dev * rt2x00dev)133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134 {
135 struct eeprom_93cx6 eeprom;
136 u32 reg;
137
138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
139
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144 {
145 case 0:
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147 break;
148 case 1:
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150 break;
151 default:
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153 break;
154 }
155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
159
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
162 }
163
rt2800pci_efuse_detect(struct rt2x00_dev * rt2x00dev)164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165 {
166 return rt2800_efuse_detect(rt2x00dev);
167 }
168
rt2800pci_read_eeprom_efuse(struct rt2x00_dev * rt2x00dev)169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
170 {
171 rt2800_read_eeprom_efuse(rt2x00dev);
172 }
173 #else
rt2800pci_read_eeprom_pci(struct rt2x00_dev * rt2x00dev)174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177
rt2800pci_efuse_detect(struct rt2x00_dev * rt2x00dev)178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 {
180 return 0;
181 }
182
rt2800pci_read_eeprom_efuse(struct rt2x00_dev * rt2x00dev)183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 {
185 }
186 #endif /* CONFIG_PCI */
187
188 /*
189 * Queue handlers.
190 */
rt2800pci_start_queue(struct data_queue * queue)191 static void rt2800pci_start_queue(struct data_queue *queue)
192 {
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194 u32 reg;
195
196 switch (queue->qid) {
197 case QID_RX:
198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
199 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break;
202 case QID_BEACON:
203 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
204 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
207 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
208
209 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
210 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
211 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
212 break;
213 default:
214 break;
215 }
216 }
217
rt2800pci_kick_queue(struct data_queue * queue)218 static void rt2800pci_kick_queue(struct data_queue *queue)
219 {
220 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221 struct queue_entry *entry;
222
223 switch (queue->qid) {
224 case QID_AC_VO:
225 case QID_AC_VI:
226 case QID_AC_BE:
227 case QID_AC_BK:
228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
230 entry->entry_idx);
231 break;
232 case QID_MGMT:
233 entry = rt2x00queue_get_entry(queue, Q_INDEX);
234 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
235 entry->entry_idx);
236 break;
237 default:
238 break;
239 }
240 }
241
rt2800pci_stop_queue(struct data_queue * queue)242 static void rt2800pci_stop_queue(struct data_queue *queue)
243 {
244 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
245 u32 reg;
246
247 switch (queue->qid) {
248 case QID_RX:
249 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
250 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
251 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
252 break;
253 case QID_BEACON:
254 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
255 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
256 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
257 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
258 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
259
260 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
261 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
262 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
263
264 /*
265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
268 */
269 tasklet_kill(&rt2x00dev->tbtt_tasklet);
270 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
271
272 break;
273 default:
274 break;
275 }
276 }
277
278 /*
279 * Firmware functions
280 */
rt2800pci_get_firmware_name(struct rt2x00_dev * rt2x00dev)281 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
282 {
283 return FIRMWARE_RT2860;
284 }
285
rt2800pci_write_firmware(struct rt2x00_dev * rt2x00dev,const u8 * data,const size_t len)286 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
287 const u8 *data, const size_t len)
288 {
289 u32 reg;
290
291 /*
292 * enable Host program ram write selection
293 */
294 reg = 0;
295 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
296 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
297
298 /*
299 * Write firmware to device.
300 */
301 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
302 data, len);
303
304 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
305 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
306
307 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
308 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
309
310 return 0;
311 }
312
313 /*
314 * Initialization functions.
315 */
rt2800pci_get_entry_state(struct queue_entry * entry)316 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
317 {
318 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
319 u32 word;
320
321 if (entry->queue->qid == QID_RX) {
322 rt2x00_desc_read(entry_priv->desc, 1, &word);
323
324 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
325 } else {
326 rt2x00_desc_read(entry_priv->desc, 1, &word);
327
328 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
329 }
330 }
331
rt2800pci_clear_entry(struct queue_entry * entry)332 static void rt2800pci_clear_entry(struct queue_entry *entry)
333 {
334 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
335 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
336 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
337 u32 word;
338
339 if (entry->queue->qid == QID_RX) {
340 rt2x00_desc_read(entry_priv->desc, 0, &word);
341 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
342 rt2x00_desc_write(entry_priv->desc, 0, word);
343
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
346 rt2x00_desc_write(entry_priv->desc, 1, word);
347
348 /*
349 * Set RX IDX in register to inform hardware that we have
350 * handled this entry and it is available for reuse again.
351 */
352 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
353 entry->entry_idx);
354 } else {
355 rt2x00_desc_read(entry_priv->desc, 1, &word);
356 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
357 rt2x00_desc_write(entry_priv->desc, 1, word);
358 }
359 }
360
rt2800pci_init_queues(struct rt2x00_dev * rt2x00dev)361 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
362 {
363 struct queue_entry_priv_pci *entry_priv;
364 u32 reg;
365
366 /*
367 * Initialize registers.
368 */
369 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
370 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
371 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
372 rt2x00dev->tx[0].limit);
373 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
374 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
375
376 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
377 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
378 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
379 rt2x00dev->tx[1].limit);
380 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
381 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
382
383 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
384 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
385 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
386 rt2x00dev->tx[2].limit);
387 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
388 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
389
390 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
391 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
392 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
393 rt2x00dev->tx[3].limit);
394 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
395 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
396
397 entry_priv = rt2x00dev->rx->entries[0].priv_data;
398 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
399 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
400 rt2x00dev->rx[0].limit);
401 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
402 rt2x00dev->rx[0].limit - 1);
403 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
404
405 /*
406 * Enable global DMA configuration
407 */
408 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
409 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
410 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
411 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
415
416 return 0;
417 }
418
419 /*
420 * Device state switch handlers.
421 */
rt2800pci_toggle_irq(struct rt2x00_dev * rt2x00dev,enum dev_state state)422 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
423 enum dev_state state)
424 {
425 u32 reg;
426 unsigned long flags;
427
428 /*
429 * When interrupts are being enabled, the interrupt registers
430 * should clear the register to assure a clean state.
431 */
432 if (state == STATE_RADIO_IRQ_ON) {
433 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
434 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
435 }
436
437 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
438 reg = 0;
439 if (state == STATE_RADIO_IRQ_ON) {
440 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
441 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
442 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
443 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
444 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
445 }
446 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
447 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
448
449 if (state == STATE_RADIO_IRQ_OFF) {
450 /*
451 * Wait for possibly running tasklets to finish.
452 */
453 tasklet_kill(&rt2x00dev->txstatus_tasklet);
454 tasklet_kill(&rt2x00dev->rxdone_tasklet);
455 tasklet_kill(&rt2x00dev->autowake_tasklet);
456 tasklet_kill(&rt2x00dev->tbtt_tasklet);
457 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
458 }
459 }
460
rt2800pci_init_registers(struct rt2x00_dev * rt2x00dev)461 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
462 {
463 u32 reg;
464
465 /*
466 * Reset DMA indexes
467 */
468 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
469 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
470 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
471 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
472 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
473 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
474 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
475 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
476 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
477
478 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
479 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
480
481 if (rt2x00_is_pcie(rt2x00dev) &&
482 (rt2x00_rt(rt2x00dev, RT3572) ||
483 rt2x00_rt(rt2x00dev, RT5390))) {
484 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
485 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
486 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
487 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
488 }
489
490 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
491
492 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
493 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
494 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
495 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
496
497 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
498
499 return 0;
500 }
501
rt2800pci_enable_radio(struct rt2x00_dev * rt2x00dev)502 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
503 {
504 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
505 rt2800pci_init_queues(rt2x00dev)))
506 return -EIO;
507
508 return rt2800_enable_radio(rt2x00dev);
509 }
510
rt2800pci_disable_radio(struct rt2x00_dev * rt2x00dev)511 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
512 {
513 if (rt2x00_is_soc(rt2x00dev)) {
514 rt2800_disable_radio(rt2x00dev);
515 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
516 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
517 }
518 }
519
rt2800pci_set_state(struct rt2x00_dev * rt2x00dev,enum dev_state state)520 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
521 enum dev_state state)
522 {
523 if (state == STATE_AWAKE) {
524 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
525 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
526 } else if (state == STATE_SLEEP) {
527 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
528 0xffffffff);
529 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
530 0xffffffff);
531 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
532 }
533
534 return 0;
535 }
536
rt2800pci_set_device_state(struct rt2x00_dev * rt2x00dev,enum dev_state state)537 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
538 enum dev_state state)
539 {
540 int retval = 0;
541
542 switch (state) {
543 case STATE_RADIO_ON:
544 /*
545 * Before the radio can be enabled, the device first has
546 * to be woken up. After that it needs a bit of time
547 * to be fully awake and then the radio can be enabled.
548 */
549 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
550 msleep(1);
551 retval = rt2800pci_enable_radio(rt2x00dev);
552 break;
553 case STATE_RADIO_OFF:
554 /*
555 * After the radio has been disabled, the device should
556 * be put to sleep for powersaving.
557 */
558 rt2800pci_disable_radio(rt2x00dev);
559 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
560 break;
561 case STATE_RADIO_IRQ_ON:
562 case STATE_RADIO_IRQ_OFF:
563 rt2800pci_toggle_irq(rt2x00dev, state);
564 break;
565 case STATE_DEEP_SLEEP:
566 case STATE_SLEEP:
567 case STATE_STANDBY:
568 case STATE_AWAKE:
569 retval = rt2800pci_set_state(rt2x00dev, state);
570 break;
571 default:
572 retval = -ENOTSUPP;
573 break;
574 }
575
576 if (unlikely(retval))
577 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
578 state, retval);
579
580 return retval;
581 }
582
583 /*
584 * TX descriptor initialization
585 */
rt2800pci_get_txwi(struct queue_entry * entry)586 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
587 {
588 return (__le32 *) entry->skb->data;
589 }
590
rt2800pci_write_tx_desc(struct queue_entry * entry,struct txentry_desc * txdesc)591 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
592 struct txentry_desc *txdesc)
593 {
594 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
595 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
596 __le32 *txd = entry_priv->desc;
597 u32 word;
598
599 /*
600 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
601 * must contains a TXWI structure + 802.11 header + padding + 802.11
602 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
603 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
604 * data. It means that LAST_SEC0 is always 0.
605 */
606
607 /*
608 * Initialize TX descriptor
609 */
610 word = 0;
611 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
612 rt2x00_desc_write(txd, 0, word);
613
614 word = 0;
615 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
616 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
617 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
618 rt2x00_set_field32(&word, TXD_W1_BURST,
619 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
620 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
621 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
622 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
623 rt2x00_desc_write(txd, 1, word);
624
625 word = 0;
626 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
627 skbdesc->skb_dma + TXWI_DESC_SIZE);
628 rt2x00_desc_write(txd, 2, word);
629
630 word = 0;
631 rt2x00_set_field32(&word, TXD_W3_WIV,
632 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
633 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
634 rt2x00_desc_write(txd, 3, word);
635
636 /*
637 * Register descriptor details in skb frame descriptor.
638 */
639 skbdesc->desc = txd;
640 skbdesc->desc_len = TXD_DESC_SIZE;
641 }
642
643 /*
644 * RX control handlers
645 */
rt2800pci_fill_rxdone(struct queue_entry * entry,struct rxdone_entry_desc * rxdesc)646 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
647 struct rxdone_entry_desc *rxdesc)
648 {
649 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
650 __le32 *rxd = entry_priv->desc;
651 u32 word;
652
653 rt2x00_desc_read(rxd, 3, &word);
654
655 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
656 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
657
658 /*
659 * Unfortunately we don't know the cipher type used during
660 * decryption. This prevents us from correct providing
661 * correct statistics through debugfs.
662 */
663 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
664
665 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
666 /*
667 * Hardware has stripped IV/EIV data from 802.11 frame during
668 * decryption. Unfortunately the descriptor doesn't contain
669 * any fields with the EIV/IV data either, so they can't
670 * be restored by rt2x00lib.
671 */
672 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
673
674 /*
675 * The hardware has already checked the Michael Mic and has
676 * stripped it from the frame. Signal this to mac80211.
677 */
678 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
679
680 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
681 rxdesc->flags |= RX_FLAG_DECRYPTED;
682 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
683 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
684 }
685
686 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
687 rxdesc->dev_flags |= RXDONE_MY_BSS;
688
689 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
690 rxdesc->dev_flags |= RXDONE_L2PAD;
691
692 /*
693 * Process the RXWI structure that is at the start of the buffer.
694 */
695 rt2800_process_rxwi(entry, rxdesc);
696 }
697
698 /*
699 * Interrupt functions.
700 */
rt2800pci_wakeup(struct rt2x00_dev * rt2x00dev)701 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
702 {
703 struct ieee80211_conf conf = { .flags = 0 };
704 struct rt2x00lib_conf libconf = { .conf = &conf };
705
706 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
707 }
708
rt2800pci_txdone(struct rt2x00_dev * rt2x00dev)709 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
710 {
711 struct data_queue *queue;
712 struct queue_entry *entry;
713 u32 status;
714 u8 qid;
715 int max_tx_done = 16;
716
717 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
718 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
719 if (unlikely(qid >= QID_RX)) {
720 /*
721 * Unknown queue, this shouldn't happen. Just drop
722 * this tx status.
723 */
724 WARNING(rt2x00dev, "Got TX status report with "
725 "unexpected pid %u, dropping\n", qid);
726 break;
727 }
728
729 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
730 if (unlikely(queue == NULL)) {
731 /*
732 * The queue is NULL, this shouldn't happen. Stop
733 * processing here and drop the tx status
734 */
735 WARNING(rt2x00dev, "Got TX status for an unavailable "
736 "queue %u, dropping\n", qid);
737 break;
738 }
739
740 if (unlikely(rt2x00queue_empty(queue))) {
741 /*
742 * The queue is empty. Stop processing here
743 * and drop the tx status.
744 */
745 WARNING(rt2x00dev, "Got TX status for an empty "
746 "queue %u, dropping\n", qid);
747 break;
748 }
749
750 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
751 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
752
753 if (--max_tx_done == 0)
754 break;
755 }
756
757 return !max_tx_done;
758 }
759
rt2800pci_enable_interrupt(struct rt2x00_dev * rt2x00dev,struct rt2x00_field32 irq_field)760 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
761 struct rt2x00_field32 irq_field)
762 {
763 u32 reg;
764
765 /*
766 * Enable a single interrupt. The interrupt mask register
767 * access needs locking.
768 */
769 spin_lock_irq(&rt2x00dev->irqmask_lock);
770 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
771 rt2x00_set_field32(®, irq_field, 1);
772 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
773 spin_unlock_irq(&rt2x00dev->irqmask_lock);
774 }
775
rt2800pci_txstatus_tasklet(unsigned long data)776 static void rt2800pci_txstatus_tasklet(unsigned long data)
777 {
778 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
779 if (rt2800pci_txdone(rt2x00dev))
780 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
781
782 /*
783 * No need to enable the tx status interrupt here as we always
784 * leave it enabled to minimize the possibility of a tx status
785 * register overflow. See comment in interrupt handler.
786 */
787 }
788
rt2800pci_pretbtt_tasklet(unsigned long data)789 static void rt2800pci_pretbtt_tasklet(unsigned long data)
790 {
791 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
792 rt2x00lib_pretbtt(rt2x00dev);
793 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
794 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
795 }
796
rt2800pci_tbtt_tasklet(unsigned long data)797 static void rt2800pci_tbtt_tasklet(unsigned long data)
798 {
799 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
800 rt2x00lib_beacondone(rt2x00dev);
801 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
802 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
803 }
804
rt2800pci_rxdone_tasklet(unsigned long data)805 static void rt2800pci_rxdone_tasklet(unsigned long data)
806 {
807 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
808 if (rt2x00pci_rxdone(rt2x00dev))
809 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
810 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
811 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
812 }
813
rt2800pci_autowake_tasklet(unsigned long data)814 static void rt2800pci_autowake_tasklet(unsigned long data)
815 {
816 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
817 rt2800pci_wakeup(rt2x00dev);
818 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
819 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
820 }
821
rt2800pci_txstatus_interrupt(struct rt2x00_dev * rt2x00dev)822 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
823 {
824 u32 status;
825 int i;
826
827 /*
828 * The TX_FIFO_STATUS interrupt needs special care. We should
829 * read TX_STA_FIFO but we should do it immediately as otherwise
830 * the register can overflow and we would lose status reports.
831 *
832 * Hence, read the TX_STA_FIFO register and copy all tx status
833 * reports into a kernel FIFO which is handled in the txstatus
834 * tasklet. We use a tasklet to process the tx status reports
835 * because we can schedule the tasklet multiple times (when the
836 * interrupt fires again during tx status processing).
837 *
838 * Furthermore we don't disable the TX_FIFO_STATUS
839 * interrupt here but leave it enabled so that the TX_STA_FIFO
840 * can also be read while the tx status tasklet gets executed.
841 *
842 * Since we have only one producer and one consumer we don't
843 * need to lock the kfifo.
844 */
845 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
846 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
847
848 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
849 break;
850
851 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
852 WARNING(rt2x00dev, "TX status FIFO overrun,"
853 "drop tx status report.\n");
854 break;
855 }
856 }
857
858 /* Schedule the tasklet for processing the tx status. */
859 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
860 }
861
rt2800pci_interrupt(int irq,void * dev_instance)862 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
863 {
864 struct rt2x00_dev *rt2x00dev = dev_instance;
865 u32 reg, mask;
866
867 /* Read status and ACK all interrupts */
868 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
869 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
870
871 if (!reg)
872 return IRQ_NONE;
873
874 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
875 return IRQ_HANDLED;
876
877 /*
878 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
879 * for interrupts and interrupt masks we can just use the value of
880 * INT_SOURCE_CSR to create the interrupt mask.
881 */
882 mask = ~reg;
883
884 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
885 rt2800pci_txstatus_interrupt(rt2x00dev);
886 /*
887 * Never disable the TX_FIFO_STATUS interrupt.
888 */
889 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
890 }
891
892 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
893 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
894
895 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
896 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
897
898 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
899 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
900
901 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
902 tasklet_schedule(&rt2x00dev->autowake_tasklet);
903
904 /*
905 * Disable all interrupts for which a tasklet was scheduled right now,
906 * the tasklet will reenable the appropriate interrupts.
907 */
908 spin_lock(&rt2x00dev->irqmask_lock);
909 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
910 reg &= mask;
911 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
912 spin_unlock(&rt2x00dev->irqmask_lock);
913
914 return IRQ_HANDLED;
915 }
916
917 /*
918 * Device probe functions.
919 */
rt2800pci_validate_eeprom(struct rt2x00_dev * rt2x00dev)920 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
921 {
922 /*
923 * Read EEPROM into buffer
924 */
925 if (rt2x00_is_soc(rt2x00dev))
926 rt2800pci_read_eeprom_soc(rt2x00dev);
927 else if (rt2800pci_efuse_detect(rt2x00dev))
928 rt2800pci_read_eeprom_efuse(rt2x00dev);
929 else
930 rt2800pci_read_eeprom_pci(rt2x00dev);
931
932 return rt2800_validate_eeprom(rt2x00dev);
933 }
934
rt2800pci_probe_hw(struct rt2x00_dev * rt2x00dev)935 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
936 {
937 int retval;
938
939 /*
940 * Allocate eeprom data.
941 */
942 retval = rt2800pci_validate_eeprom(rt2x00dev);
943 if (retval)
944 return retval;
945
946 retval = rt2800_init_eeprom(rt2x00dev);
947 if (retval)
948 return retval;
949
950 /*
951 * Initialize hw specifications.
952 */
953 retval = rt2800_probe_hw_mode(rt2x00dev);
954 if (retval)
955 return retval;
956
957 /*
958 * This device has multiple filters for control frames
959 * and has a separate filter for PS Poll frames.
960 */
961 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
962 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
963
964 /*
965 * This device has a pre tbtt interrupt and thus fetches
966 * a new beacon directly prior to transmission.
967 */
968 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
969
970 /*
971 * This device requires firmware.
972 */
973 if (!rt2x00_is_soc(rt2x00dev))
974 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
975 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
976 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
977 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
978 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
979 if (!modparam_nohwcrypt)
980 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
981 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
982 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
983
984 /*
985 * Set the rssi offset.
986 */
987 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
988
989 return 0;
990 }
991
992 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
993 .tx = rt2x00mac_tx,
994 .start = rt2x00mac_start,
995 .stop = rt2x00mac_stop,
996 .add_interface = rt2x00mac_add_interface,
997 .remove_interface = rt2x00mac_remove_interface,
998 .config = rt2x00mac_config,
999 .configure_filter = rt2x00mac_configure_filter,
1000 .set_key = rt2x00mac_set_key,
1001 .sw_scan_start = rt2x00mac_sw_scan_start,
1002 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1003 .get_stats = rt2x00mac_get_stats,
1004 .get_tkip_seq = rt2800_get_tkip_seq,
1005 .set_rts_threshold = rt2800_set_rts_threshold,
1006 .sta_add = rt2x00mac_sta_add,
1007 .sta_remove = rt2x00mac_sta_remove,
1008 .bss_info_changed = rt2x00mac_bss_info_changed,
1009 .conf_tx = rt2800_conf_tx,
1010 .get_tsf = rt2800_get_tsf,
1011 .rfkill_poll = rt2x00mac_rfkill_poll,
1012 .ampdu_action = rt2800_ampdu_action,
1013 .flush = rt2x00mac_flush,
1014 .get_survey = rt2800_get_survey,
1015 .get_ringparam = rt2x00mac_get_ringparam,
1016 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1017 };
1018
1019 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1020 .register_read = rt2x00pci_register_read,
1021 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1022 .register_write = rt2x00pci_register_write,
1023 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1024 .register_multiread = rt2x00pci_register_multiread,
1025 .register_multiwrite = rt2x00pci_register_multiwrite,
1026 .regbusy_read = rt2x00pci_regbusy_read,
1027 .drv_write_firmware = rt2800pci_write_firmware,
1028 .drv_init_registers = rt2800pci_init_registers,
1029 .drv_get_txwi = rt2800pci_get_txwi,
1030 };
1031
1032 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1033 .irq_handler = rt2800pci_interrupt,
1034 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1035 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1036 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1037 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1038 .autowake_tasklet = rt2800pci_autowake_tasklet,
1039 .probe_hw = rt2800pci_probe_hw,
1040 .get_firmware_name = rt2800pci_get_firmware_name,
1041 .check_firmware = rt2800_check_firmware,
1042 .load_firmware = rt2800_load_firmware,
1043 .initialize = rt2x00pci_initialize,
1044 .uninitialize = rt2x00pci_uninitialize,
1045 .get_entry_state = rt2800pci_get_entry_state,
1046 .clear_entry = rt2800pci_clear_entry,
1047 .set_device_state = rt2800pci_set_device_state,
1048 .rfkill_poll = rt2800_rfkill_poll,
1049 .link_stats = rt2800_link_stats,
1050 .reset_tuner = rt2800_reset_tuner,
1051 .link_tuner = rt2800_link_tuner,
1052 .gain_calibration = rt2800_gain_calibration,
1053 .start_queue = rt2800pci_start_queue,
1054 .kick_queue = rt2800pci_kick_queue,
1055 .stop_queue = rt2800pci_stop_queue,
1056 .flush_queue = rt2x00pci_flush_queue,
1057 .write_tx_desc = rt2800pci_write_tx_desc,
1058 .write_tx_data = rt2800_write_tx_data,
1059 .write_beacon = rt2800_write_beacon,
1060 .clear_beacon = rt2800_clear_beacon,
1061 .fill_rxdone = rt2800pci_fill_rxdone,
1062 .config_shared_key = rt2800_config_shared_key,
1063 .config_pairwise_key = rt2800_config_pairwise_key,
1064 .config_filter = rt2800_config_filter,
1065 .config_intf = rt2800_config_intf,
1066 .config_erp = rt2800_config_erp,
1067 .config_ant = rt2800_config_ant,
1068 .config = rt2800_config,
1069 .sta_add = rt2800_sta_add,
1070 .sta_remove = rt2800_sta_remove,
1071 };
1072
1073 static const struct data_queue_desc rt2800pci_queue_rx = {
1074 .entry_num = 128,
1075 .data_size = AGGREGATION_SIZE,
1076 .desc_size = RXD_DESC_SIZE,
1077 .priv_size = sizeof(struct queue_entry_priv_pci),
1078 };
1079
1080 static const struct data_queue_desc rt2800pci_queue_tx = {
1081 .entry_num = 64,
1082 .data_size = AGGREGATION_SIZE,
1083 .desc_size = TXD_DESC_SIZE,
1084 .priv_size = sizeof(struct queue_entry_priv_pci),
1085 };
1086
1087 static const struct data_queue_desc rt2800pci_queue_bcn = {
1088 .entry_num = 8,
1089 .data_size = 0, /* No DMA required for beacons */
1090 .desc_size = TXWI_DESC_SIZE,
1091 .priv_size = sizeof(struct queue_entry_priv_pci),
1092 };
1093
1094 static const struct rt2x00_ops rt2800pci_ops = {
1095 .name = KBUILD_MODNAME,
1096 .max_sta_intf = 1,
1097 .max_ap_intf = 8,
1098 .eeprom_size = EEPROM_SIZE,
1099 .rf_size = RF_SIZE,
1100 .tx_queues = NUM_TX_QUEUES,
1101 .extra_tx_headroom = TXWI_DESC_SIZE,
1102 .rx = &rt2800pci_queue_rx,
1103 .tx = &rt2800pci_queue_tx,
1104 .bcn = &rt2800pci_queue_bcn,
1105 .lib = &rt2800pci_rt2x00_ops,
1106 .drv = &rt2800pci_rt2800_ops,
1107 .hw = &rt2800pci_mac80211_ops,
1108 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1109 .debugfs = &rt2800_rt2x00debug,
1110 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1111 };
1112
1113 /*
1114 * RT2800pci module information.
1115 */
1116 #ifdef CONFIG_PCI
1117 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1118 { PCI_DEVICE(0x1814, 0x0601) },
1119 { PCI_DEVICE(0x1814, 0x0681) },
1120 { PCI_DEVICE(0x1814, 0x0701) },
1121 { PCI_DEVICE(0x1814, 0x0781) },
1122 { PCI_DEVICE(0x1814, 0x3090) },
1123 { PCI_DEVICE(0x1814, 0x3091) },
1124 { PCI_DEVICE(0x1814, 0x3092) },
1125 { PCI_DEVICE(0x1432, 0x7708) },
1126 { PCI_DEVICE(0x1432, 0x7727) },
1127 { PCI_DEVICE(0x1432, 0x7728) },
1128 { PCI_DEVICE(0x1432, 0x7738) },
1129 { PCI_DEVICE(0x1432, 0x7748) },
1130 { PCI_DEVICE(0x1432, 0x7758) },
1131 { PCI_DEVICE(0x1432, 0x7768) },
1132 { PCI_DEVICE(0x1462, 0x891a) },
1133 { PCI_DEVICE(0x1a3b, 0x1059) },
1134 #ifdef CONFIG_RT2800PCI_RT33XX
1135 { PCI_DEVICE(0x1814, 0x3390) },
1136 #endif
1137 #ifdef CONFIG_RT2800PCI_RT35XX
1138 { PCI_DEVICE(0x1432, 0x7711) },
1139 { PCI_DEVICE(0x1432, 0x7722) },
1140 { PCI_DEVICE(0x1814, 0x3060) },
1141 { PCI_DEVICE(0x1814, 0x3062) },
1142 { PCI_DEVICE(0x1814, 0x3562) },
1143 { PCI_DEVICE(0x1814, 0x3592) },
1144 { PCI_DEVICE(0x1814, 0x3593) },
1145 #endif
1146 #ifdef CONFIG_RT2800PCI_RT53XX
1147 { PCI_DEVICE(0x1814, 0x5390) },
1148 { PCI_DEVICE(0x1814, 0x539a) },
1149 { PCI_DEVICE(0x1814, 0x539f) },
1150 #endif
1151 { 0, }
1152 };
1153 #endif /* CONFIG_PCI */
1154
1155 MODULE_AUTHOR(DRV_PROJECT);
1156 MODULE_VERSION(DRV_VERSION);
1157 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1158 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1159 #ifdef CONFIG_PCI
1160 MODULE_FIRMWARE(FIRMWARE_RT2860);
1161 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1162 #endif /* CONFIG_PCI */
1163 MODULE_LICENSE("GPL");
1164
1165 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
rt2800soc_probe(struct platform_device * pdev)1166 static int rt2800soc_probe(struct platform_device *pdev)
1167 {
1168 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1169 }
1170
1171 static struct platform_driver rt2800soc_driver = {
1172 .driver = {
1173 .name = "rt2800_wmac",
1174 .owner = THIS_MODULE,
1175 .mod_name = KBUILD_MODNAME,
1176 },
1177 .probe = rt2800soc_probe,
1178 .remove = __devexit_p(rt2x00soc_remove),
1179 .suspend = rt2x00soc_suspend,
1180 .resume = rt2x00soc_resume,
1181 };
1182 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1183
1184 #ifdef CONFIG_PCI
rt2800pci_probe(struct pci_dev * pci_dev,const struct pci_device_id * id)1185 static int rt2800pci_probe(struct pci_dev *pci_dev,
1186 const struct pci_device_id *id)
1187 {
1188 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1189 }
1190
1191 static struct pci_driver rt2800pci_driver = {
1192 .name = KBUILD_MODNAME,
1193 .id_table = rt2800pci_device_table,
1194 .probe = rt2800pci_probe,
1195 .remove = __devexit_p(rt2x00pci_remove),
1196 .suspend = rt2x00pci_suspend,
1197 .resume = rt2x00pci_resume,
1198 };
1199 #endif /* CONFIG_PCI */
1200
rt2800pci_init(void)1201 static int __init rt2800pci_init(void)
1202 {
1203 int ret = 0;
1204
1205 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1206 ret = platform_driver_register(&rt2800soc_driver);
1207 if (ret)
1208 return ret;
1209 #endif
1210 #ifdef CONFIG_PCI
1211 ret = pci_register_driver(&rt2800pci_driver);
1212 if (ret) {
1213 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1214 platform_driver_unregister(&rt2800soc_driver);
1215 #endif
1216 return ret;
1217 }
1218 #endif
1219
1220 return ret;
1221 }
1222
rt2800pci_exit(void)1223 static void __exit rt2800pci_exit(void)
1224 {
1225 #ifdef CONFIG_PCI
1226 pci_unregister_driver(&rt2800pci_driver);
1227 #endif
1228 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1229 platform_driver_unregister(&rt2800soc_driver);
1230 #endif
1231 }
1232
1233 module_init(rt2800pci_init);
1234 module_exit(rt2800pci_exit);
1235