1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62
63
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
68
69 #include <net/mac80211.h>
70
71 #include "iwl-commands.h"
72 #include "iwl-dev.h"
73 #include "iwl-core.h"
74 #include "iwl-debug.h"
75 #include "iwl-agn.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-io.h"
78
79 /************************** EEPROM BANDS ****************************
80 *
81 * The iwl_eeprom_band definitions below provide the mapping from the
82 * EEPROM contents to the specific channel number supported for each
83 * band.
84 *
85 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
86 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
87 * The specific geography and calibration information for that channel
88 * is contained in the eeprom map itself.
89 *
90 * During init, we copy the eeprom information and channel map
91 * information into priv->channel_info_24/52 and priv->channel_map_24/52
92 *
93 * channel_map_24/52 provides the index in the channel_info array for a
94 * given channel. We have to have two separate maps as there is channel
95 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
96 * band_2
97 *
98 * A value of 0xff stored in the channel_map indicates that the channel
99 * is not supported by the hardware at all.
100 *
101 * A value of 0xfe in the channel_map indicates that the channel is not
102 * valid for Tx with the current hardware. This means that
103 * while the system can tune and receive on a given channel, it may not
104 * be able to associate or transmit any frames on that
105 * channel. There is no corresponding channel information for that
106 * entry.
107 *
108 *********************************************************************/
109
110 /* 2.4 GHz */
111 const u8 iwl_eeprom_band_1[14] = {
112 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
113 };
114
115 /* 5.2 GHz bands */
116 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
117 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
118 };
119
120 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
121 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
122 };
123
124 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
125 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
126 };
127
128 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
129 145, 149, 153, 157, 161, 165
130 };
131
132 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
133 1, 2, 3, 4, 5, 6, 7
134 };
135
136 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
137 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
138 };
139
140 /******************************************************************************
141 *
142 * generic NVM functions
143 *
144 ******************************************************************************/
145
146 /*
147 * The device's EEPROM semaphore prevents conflicts between driver and uCode
148 * when accessing the EEPROM; each access is a series of pulses to/from the
149 * EEPROM chip, not a single event, so even reads could conflict if they
150 * weren't arbitrated by the semaphore.
151 */
iwl_eeprom_acquire_semaphore(struct iwl_bus * bus)152 static int iwl_eeprom_acquire_semaphore(struct iwl_bus *bus)
153 {
154 u16 count;
155 int ret;
156
157 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
158 /* Request semaphore */
159 iwl_set_bit(bus, CSR_HW_IF_CONFIG_REG,
160 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
161
162 /* See if we got it */
163 ret = iwl_poll_bit(bus, CSR_HW_IF_CONFIG_REG,
164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
165 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
166 EEPROM_SEM_TIMEOUT);
167 if (ret >= 0) {
168 IWL_DEBUG_EEPROM(bus,
169 "Acquired semaphore after %d tries.\n",
170 count+1);
171 return ret;
172 }
173 }
174
175 return ret;
176 }
177
iwl_eeprom_release_semaphore(struct iwl_bus * bus)178 static void iwl_eeprom_release_semaphore(struct iwl_bus *bus)
179 {
180 iwl_clear_bit(bus, CSR_HW_IF_CONFIG_REG,
181 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
182
183 }
184
iwl_eeprom_verify_signature(struct iwl_trans * trans)185 static int iwl_eeprom_verify_signature(struct iwl_trans *trans)
186 {
187 u32 gp = iwl_read32(bus(trans), CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
188 int ret = 0;
189
190 IWL_DEBUG_EEPROM(trans, "EEPROM signature=0x%08x\n", gp);
191 switch (gp) {
192 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
193 if (trans->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
194 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
195 gp);
196 ret = -ENOENT;
197 }
198 break;
199 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
200 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
201 if (trans->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
202 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
203 ret = -ENOENT;
204 }
205 break;
206 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
207 default:
208 IWL_ERR(trans, "bad EEPROM/OTP signature, type=%s, "
209 "EEPROM_GP=0x%08x\n",
210 (trans->nvm_device_type == NVM_DEVICE_TYPE_OTP)
211 ? "OTP" : "EEPROM", gp);
212 ret = -ENOENT;
213 break;
214 }
215 return ret;
216 }
217
iwl_eeprom_query16(const struct iwl_shared * shrd,size_t offset)218 u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset)
219 {
220 if (!shrd->eeprom)
221 return 0;
222 return (u16)shrd->eeprom[offset] | ((u16)shrd->eeprom[offset + 1] << 8);
223 }
224
iwl_eeprom_check_version(struct iwl_priv * priv)225 int iwl_eeprom_check_version(struct iwl_priv *priv)
226 {
227 u16 eeprom_ver;
228 u16 calib_ver;
229
230 eeprom_ver = iwl_eeprom_query16(priv->shrd, EEPROM_VERSION);
231 calib_ver = iwl_eeprom_calib_version(priv->shrd);
232
233 if (eeprom_ver < cfg(priv)->eeprom_ver ||
234 calib_ver < cfg(priv)->eeprom_calib_ver)
235 goto err;
236
237 IWL_INFO(priv, "device EEPROM VER=0x%x, CALIB=0x%x\n",
238 eeprom_ver, calib_ver);
239
240 return 0;
241 err:
242 IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x "
243 "CALIB=0x%x < 0x%x\n",
244 eeprom_ver, cfg(priv)->eeprom_ver,
245 calib_ver, cfg(priv)->eeprom_calib_ver);
246 return -EINVAL;
247
248 }
249
iwl_eeprom_check_sku(struct iwl_priv * priv)250 int iwl_eeprom_check_sku(struct iwl_priv *priv)
251 {
252 struct iwl_shared *shrd = priv->shrd;
253 u16 radio_cfg;
254
255 if (!cfg(priv)->sku) {
256 /* not using sku overwrite */
257 cfg(priv)->sku = iwl_eeprom_query16(shrd, EEPROM_SKU_CAP);
258 if (cfg(priv)->sku & EEPROM_SKU_CAP_11N_ENABLE &&
259 !cfg(priv)->ht_params) {
260 IWL_ERR(priv, "Invalid 11n configuration\n");
261 return -EINVAL;
262 }
263 }
264 if (!cfg(priv)->sku) {
265 IWL_ERR(priv, "Invalid device sku\n");
266 return -EINVAL;
267 }
268
269 IWL_INFO(priv, "Device SKU: 0x%X\n", cfg(priv)->sku);
270
271 if (!cfg(priv)->valid_tx_ant && !cfg(priv)->valid_rx_ant) {
272 /* not using .cfg overwrite */
273 radio_cfg = iwl_eeprom_query16(shrd, EEPROM_RADIO_CONFIG);
274 cfg(priv)->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
275 cfg(priv)->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
276 if (!cfg(priv)->valid_tx_ant || !cfg(priv)->valid_rx_ant) {
277 IWL_ERR(priv, "Invalid chain (0x%X, 0x%X)\n",
278 cfg(priv)->valid_tx_ant,
279 cfg(priv)->valid_rx_ant);
280 return -EINVAL;
281 }
282 IWL_INFO(priv, "Valid Tx ant: 0x%X, Valid Rx ant: 0x%X\n",
283 cfg(priv)->valid_tx_ant, cfg(priv)->valid_rx_ant);
284 }
285 /*
286 * for some special cases,
287 * EEPROM did not reflect the correct antenna setting
288 * so overwrite the valid tx/rx antenna from .cfg
289 */
290 return 0;
291 }
292
iwl_eeprom_get_mac(const struct iwl_shared * shrd,u8 * mac)293 void iwl_eeprom_get_mac(const struct iwl_shared *shrd, u8 *mac)
294 {
295 const u8 *addr = iwl_eeprom_query_addr(shrd,
296 EEPROM_MAC_ADDRESS);
297 memcpy(mac, addr, ETH_ALEN);
298 }
299
300 /******************************************************************************
301 *
302 * OTP related functions
303 *
304 ******************************************************************************/
305
iwl_set_otp_access(struct iwl_bus * bus,enum iwl_access_mode mode)306 static void iwl_set_otp_access(struct iwl_bus *bus, enum iwl_access_mode mode)
307 {
308 iwl_read32(bus, CSR_OTP_GP_REG);
309
310 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
311 iwl_clear_bit(bus, CSR_OTP_GP_REG,
312 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
313 else
314 iwl_set_bit(bus, CSR_OTP_GP_REG,
315 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
316 }
317
iwl_get_nvm_type(struct iwl_bus * bus,u32 hw_rev)318 static int iwl_get_nvm_type(struct iwl_bus *bus, u32 hw_rev)
319 {
320 u32 otpgp;
321 int nvm_type;
322
323 /* OTP only valid for CP/PP and after */
324 switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
325 case CSR_HW_REV_TYPE_NONE:
326 IWL_ERR(bus, "Unknown hardware type\n");
327 return -ENOENT;
328 case CSR_HW_REV_TYPE_5300:
329 case CSR_HW_REV_TYPE_5350:
330 case CSR_HW_REV_TYPE_5100:
331 case CSR_HW_REV_TYPE_5150:
332 nvm_type = NVM_DEVICE_TYPE_EEPROM;
333 break;
334 default:
335 otpgp = iwl_read32(bus, CSR_OTP_GP_REG);
336 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
337 nvm_type = NVM_DEVICE_TYPE_OTP;
338 else
339 nvm_type = NVM_DEVICE_TYPE_EEPROM;
340 break;
341 }
342 return nvm_type;
343 }
344
iwl_init_otp_access(struct iwl_bus * bus)345 static int iwl_init_otp_access(struct iwl_bus *bus)
346 {
347 int ret;
348
349 /* Enable 40MHz radio clock */
350 iwl_write32(bus, CSR_GP_CNTRL,
351 iwl_read32(bus, CSR_GP_CNTRL) |
352 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
353
354 /* wait for clock to be ready */
355 ret = iwl_poll_bit(bus, CSR_GP_CNTRL,
356 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
357 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
358 25000);
359 if (ret < 0)
360 IWL_ERR(bus, "Time out access OTP\n");
361 else {
362 iwl_set_bits_prph(bus, APMG_PS_CTRL_REG,
363 APMG_PS_CTRL_VAL_RESET_REQ);
364 udelay(5);
365 iwl_clear_bits_prph(bus, APMG_PS_CTRL_REG,
366 APMG_PS_CTRL_VAL_RESET_REQ);
367
368 /*
369 * CSR auto clock gate disable bit -
370 * this is only applicable for HW with OTP shadow RAM
371 */
372 if (cfg(bus)->base_params->shadow_ram_support)
373 iwl_set_bit(bus, CSR_DBG_LINK_PWR_MGMT_REG,
374 CSR_RESET_LINK_PWR_MGMT_DISABLED);
375 }
376 return ret;
377 }
378
iwl_read_otp_word(struct iwl_bus * bus,u16 addr,__le16 * eeprom_data)379 static int iwl_read_otp_word(struct iwl_bus *bus, u16 addr, __le16 *eeprom_data)
380 {
381 int ret = 0;
382 u32 r;
383 u32 otpgp;
384
385 iwl_write32(bus, CSR_EEPROM_REG,
386 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
387 ret = iwl_poll_bit(bus, CSR_EEPROM_REG,
388 CSR_EEPROM_REG_READ_VALID_MSK,
389 CSR_EEPROM_REG_READ_VALID_MSK,
390 IWL_EEPROM_ACCESS_TIMEOUT);
391 if (ret < 0) {
392 IWL_ERR(bus, "Time out reading OTP[%d]\n", addr);
393 return ret;
394 }
395 r = iwl_read32(bus, CSR_EEPROM_REG);
396 /* check for ECC errors: */
397 otpgp = iwl_read32(bus, CSR_OTP_GP_REG);
398 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
399 /* stop in this case */
400 /* set the uncorrectable OTP ECC bit for acknowledgement */
401 iwl_set_bit(bus, CSR_OTP_GP_REG,
402 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
403 IWL_ERR(bus, "Uncorrectable OTP ECC error, abort OTP read\n");
404 return -EINVAL;
405 }
406 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
407 /* continue in this case */
408 /* set the correctable OTP ECC bit for acknowledgement */
409 iwl_set_bit(bus, CSR_OTP_GP_REG,
410 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
411 IWL_ERR(bus, "Correctable OTP ECC error, continue read\n");
412 }
413 *eeprom_data = cpu_to_le16(r >> 16);
414 return 0;
415 }
416
417 /*
418 * iwl_is_otp_empty: check for empty OTP
419 */
iwl_is_otp_empty(struct iwl_bus * bus)420 static bool iwl_is_otp_empty(struct iwl_bus *bus)
421 {
422 u16 next_link_addr = 0;
423 __le16 link_value;
424 bool is_empty = false;
425
426 /* locate the beginning of OTP link list */
427 if (!iwl_read_otp_word(bus, next_link_addr, &link_value)) {
428 if (!link_value) {
429 IWL_ERR(bus, "OTP is empty\n");
430 is_empty = true;
431 }
432 } else {
433 IWL_ERR(bus, "Unable to read first block of OTP list.\n");
434 is_empty = true;
435 }
436
437 return is_empty;
438 }
439
440
441 /*
442 * iwl_find_otp_image: find EEPROM image in OTP
443 * finding the OTP block that contains the EEPROM image.
444 * the last valid block on the link list (the block _before_ the last block)
445 * is the block we should read and used to configure the device.
446 * If all the available OTP blocks are full, the last block will be the block
447 * we should read and used to configure the device.
448 * only perform this operation if shadow RAM is disabled
449 */
iwl_find_otp_image(struct iwl_bus * bus,u16 * validblockaddr)450 static int iwl_find_otp_image(struct iwl_bus *bus,
451 u16 *validblockaddr)
452 {
453 u16 next_link_addr = 0, valid_addr;
454 __le16 link_value = 0;
455 int usedblocks = 0;
456
457 /* set addressing mode to absolute to traverse the link list */
458 iwl_set_otp_access(bus, IWL_OTP_ACCESS_ABSOLUTE);
459
460 /* checking for empty OTP or error */
461 if (iwl_is_otp_empty(bus))
462 return -EINVAL;
463
464 /*
465 * start traverse link list
466 * until reach the max number of OTP blocks
467 * different devices have different number of OTP blocks
468 */
469 do {
470 /* save current valid block address
471 * check for more block on the link list
472 */
473 valid_addr = next_link_addr;
474 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
475 IWL_DEBUG_EEPROM(bus, "OTP blocks %d addr 0x%x\n",
476 usedblocks, next_link_addr);
477 if (iwl_read_otp_word(bus, next_link_addr, &link_value))
478 return -EINVAL;
479 if (!link_value) {
480 /*
481 * reach the end of link list, return success and
482 * set address point to the starting address
483 * of the image
484 */
485 *validblockaddr = valid_addr;
486 /* skip first 2 bytes (link list pointer) */
487 *validblockaddr += 2;
488 return 0;
489 }
490 /* more in the link list, continue */
491 usedblocks++;
492 } while (usedblocks <= cfg(bus)->base_params->max_ll_items);
493
494 /* OTP has no valid blocks */
495 IWL_DEBUG_EEPROM(bus, "OTP has no valid blocks\n");
496 return -EINVAL;
497 }
498
499 /******************************************************************************
500 *
501 * Tx Power related functions
502 *
503 ******************************************************************************/
504 /**
505 * iwl_get_max_txpower_avg - get the highest tx power from all chains.
506 * find the highest tx power from all chains for the channel
507 */
iwl_get_max_txpower_avg(struct iwl_cfg * cfg,struct iwl_eeprom_enhanced_txpwr * enhanced_txpower,int element,s8 * max_txpower_in_half_dbm)508 static s8 iwl_get_max_txpower_avg(struct iwl_cfg *cfg,
509 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
510 int element, s8 *max_txpower_in_half_dbm)
511 {
512 s8 max_txpower_avg = 0; /* (dBm) */
513
514 /* Take the highest tx power from any valid chains */
515 if ((cfg->valid_tx_ant & ANT_A) &&
516 (enhanced_txpower[element].chain_a_max > max_txpower_avg))
517 max_txpower_avg = enhanced_txpower[element].chain_a_max;
518 if ((cfg->valid_tx_ant & ANT_B) &&
519 (enhanced_txpower[element].chain_b_max > max_txpower_avg))
520 max_txpower_avg = enhanced_txpower[element].chain_b_max;
521 if ((cfg->valid_tx_ant & ANT_C) &&
522 (enhanced_txpower[element].chain_c_max > max_txpower_avg))
523 max_txpower_avg = enhanced_txpower[element].chain_c_max;
524 if (((cfg->valid_tx_ant == ANT_AB) |
525 (cfg->valid_tx_ant == ANT_BC) |
526 (cfg->valid_tx_ant == ANT_AC)) &&
527 (enhanced_txpower[element].mimo2_max > max_txpower_avg))
528 max_txpower_avg = enhanced_txpower[element].mimo2_max;
529 if ((cfg->valid_tx_ant == ANT_ABC) &&
530 (enhanced_txpower[element].mimo3_max > max_txpower_avg))
531 max_txpower_avg = enhanced_txpower[element].mimo3_max;
532
533 /*
534 * max. tx power in EEPROM is in 1/2 dBm format
535 * convert from 1/2 dBm to dBm (round-up convert)
536 * but we also do not want to loss 1/2 dBm resolution which
537 * will impact performance
538 */
539 *max_txpower_in_half_dbm = max_txpower_avg;
540 return (max_txpower_avg & 0x01) + (max_txpower_avg >> 1);
541 }
542
543 static void
iwl_eeprom_enh_txp_read_element(struct iwl_priv * priv,struct iwl_eeprom_enhanced_txpwr * txp,s8 max_txpower_avg)544 iwl_eeprom_enh_txp_read_element(struct iwl_priv *priv,
545 struct iwl_eeprom_enhanced_txpwr *txp,
546 s8 max_txpower_avg)
547 {
548 int ch_idx;
549 bool is_ht40 = txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ;
550 enum ieee80211_band band;
551
552 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
553 IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
554
555 for (ch_idx = 0; ch_idx < priv->channel_count; ch_idx++) {
556 struct iwl_channel_info *ch_info = &priv->channel_info[ch_idx];
557
558 /* update matching channel or from common data only */
559 if (txp->channel != 0 && ch_info->channel != txp->channel)
560 continue;
561
562 /* update matching band only */
563 if (band != ch_info->band)
564 continue;
565
566 if (ch_info->max_power_avg < max_txpower_avg && !is_ht40) {
567 ch_info->max_power_avg = max_txpower_avg;
568 ch_info->curr_txpow = max_txpower_avg;
569 ch_info->scan_power = max_txpower_avg;
570 }
571
572 if (is_ht40 && ch_info->ht40_max_power_avg < max_txpower_avg)
573 ch_info->ht40_max_power_avg = max_txpower_avg;
574 }
575 }
576
577 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
578 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
579 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
580
581 #define TXP_CHECK_AND_PRINT(x) ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) \
582 ? # x " " : "")
583
iwl_eeprom_enhanced_txpower(struct iwl_priv * priv)584 void iwl_eeprom_enhanced_txpower(struct iwl_priv *priv)
585 {
586 struct iwl_shared *shrd = priv->shrd;
587 struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
588 int idx, entries;
589 __le16 *txp_len;
590 s8 max_txp_avg, max_txp_avg_halfdbm;
591
592 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
593
594 /* the length is in 16-bit words, but we want entries */
595 txp_len = (__le16 *) iwl_eeprom_query_addr(shrd, EEPROM_TXP_SZ_OFFS);
596 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
597
598 txp_array = (void *) iwl_eeprom_query_addr(shrd, EEPROM_TXP_OFFS);
599
600 for (idx = 0; idx < entries; idx++) {
601 txp = &txp_array[idx];
602 /* skip invalid entries */
603 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
604 continue;
605
606 IWL_DEBUG_EEPROM(priv, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
607 (txp->channel && (txp->flags &
608 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
609 "Common " : (txp->channel) ?
610 "Channel" : "Common",
611 (txp->channel),
612 TXP_CHECK_AND_PRINT(VALID),
613 TXP_CHECK_AND_PRINT(BAND_52G),
614 TXP_CHECK_AND_PRINT(OFDM),
615 TXP_CHECK_AND_PRINT(40MHZ),
616 TXP_CHECK_AND_PRINT(HT_AP),
617 TXP_CHECK_AND_PRINT(RES1),
618 TXP_CHECK_AND_PRINT(RES2),
619 TXP_CHECK_AND_PRINT(COMMON_TYPE),
620 txp->flags);
621 IWL_DEBUG_EEPROM(priv, "\t\t chain_A: 0x%02x "
622 "chain_B: 0X%02x chain_C: 0X%02x\n",
623 txp->chain_a_max, txp->chain_b_max,
624 txp->chain_c_max);
625 IWL_DEBUG_EEPROM(priv, "\t\t MIMO2: 0x%02x "
626 "MIMO3: 0x%02x High 20_on_40: 0x%02x "
627 "Low 20_on_40: 0x%02x\n",
628 txp->mimo2_max, txp->mimo3_max,
629 ((txp->delta_20_in_40 & 0xf0) >> 4),
630 (txp->delta_20_in_40 & 0x0f));
631
632 max_txp_avg = iwl_get_max_txpower_avg(cfg(priv), txp_array, idx,
633 &max_txp_avg_halfdbm);
634
635 /*
636 * Update the user limit values values to the highest
637 * power supported by any channel
638 */
639 if (max_txp_avg > priv->tx_power_user_lmt)
640 priv->tx_power_user_lmt = max_txp_avg;
641 if (max_txp_avg_halfdbm > priv->tx_power_lmt_in_half_dbm)
642 priv->tx_power_lmt_in_half_dbm = max_txp_avg_halfdbm;
643
644 iwl_eeprom_enh_txp_read_element(priv, txp, max_txp_avg);
645 }
646 }
647
648 /**
649 * iwl_eeprom_init - read EEPROM contents
650 *
651 * Load the EEPROM contents from adapter into shrd->eeprom
652 *
653 * NOTE: This routine uses the non-debug IO access functions.
654 */
iwl_eeprom_init(struct iwl_priv * priv,u32 hw_rev)655 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
656 {
657 struct iwl_shared *shrd = priv->shrd;
658 __le16 *e;
659 u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP);
660 int sz;
661 int ret;
662 u16 addr;
663 u16 validblockaddr = 0;
664 u16 cache_addr = 0;
665
666 trans(priv)->nvm_device_type = iwl_get_nvm_type(bus(priv), hw_rev);
667 if (trans(priv)->nvm_device_type == -ENOENT)
668 return -ENOENT;
669 /* allocate eeprom */
670 sz = cfg(priv)->base_params->eeprom_size;
671 IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
672 shrd->eeprom = kzalloc(sz, GFP_KERNEL);
673 if (!shrd->eeprom) {
674 ret = -ENOMEM;
675 goto alloc_err;
676 }
677 e = (__le16 *)shrd->eeprom;
678
679 iwl_apm_init(priv);
680
681 ret = iwl_eeprom_verify_signature(trans(priv));
682 if (ret < 0) {
683 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
684 ret = -ENOENT;
685 goto err;
686 }
687
688 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
689 ret = iwl_eeprom_acquire_semaphore(bus(priv));
690 if (ret < 0) {
691 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
692 ret = -ENOENT;
693 goto err;
694 }
695
696 if (trans(priv)->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
697
698 ret = iwl_init_otp_access(bus(priv));
699 if (ret) {
700 IWL_ERR(priv, "Failed to initialize OTP access.\n");
701 ret = -ENOENT;
702 goto done;
703 }
704 iwl_write32(bus(priv), CSR_EEPROM_GP,
705 iwl_read32(bus(priv), CSR_EEPROM_GP) &
706 ~CSR_EEPROM_GP_IF_OWNER_MSK);
707
708 iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
709 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
710 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
711 /* traversing the linked list if no shadow ram supported */
712 if (!cfg(priv)->base_params->shadow_ram_support) {
713 if (iwl_find_otp_image(bus(priv), &validblockaddr)) {
714 ret = -ENOENT;
715 goto done;
716 }
717 }
718 for (addr = validblockaddr; addr < validblockaddr + sz;
719 addr += sizeof(u16)) {
720 __le16 eeprom_data;
721
722 ret = iwl_read_otp_word(bus(priv), addr, &eeprom_data);
723 if (ret)
724 goto done;
725 e[cache_addr / 2] = eeprom_data;
726 cache_addr += sizeof(u16);
727 }
728 } else {
729 /* eeprom is an array of 16bit values */
730 for (addr = 0; addr < sz; addr += sizeof(u16)) {
731 u32 r;
732
733 iwl_write32(bus(priv), CSR_EEPROM_REG,
734 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
735
736 ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
737 CSR_EEPROM_REG_READ_VALID_MSK,
738 CSR_EEPROM_REG_READ_VALID_MSK,
739 IWL_EEPROM_ACCESS_TIMEOUT);
740 if (ret < 0) {
741 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
742 goto done;
743 }
744 r = iwl_read32(bus(priv), CSR_EEPROM_REG);
745 e[addr / 2] = cpu_to_le16(r >> 16);
746 }
747 }
748
749 IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
750 (trans(priv)->nvm_device_type == NVM_DEVICE_TYPE_OTP)
751 ? "OTP" : "EEPROM",
752 iwl_eeprom_query16(shrd, EEPROM_VERSION));
753
754 ret = 0;
755 done:
756 iwl_eeprom_release_semaphore(bus(priv));
757
758 err:
759 if (ret)
760 iwl_eeprom_free(priv->shrd);
761 /* Reset chip to save power until we load uCode during "up". */
762 iwl_apm_stop(priv);
763 alloc_err:
764 return ret;
765 }
766
iwl_eeprom_free(struct iwl_shared * shrd)767 void iwl_eeprom_free(struct iwl_shared *shrd)
768 {
769 kfree(shrd->eeprom);
770 shrd->eeprom = NULL;
771 }
772
iwl_init_band_reference(const struct iwl_priv * priv,int eep_band,int * eeprom_ch_count,const struct iwl_eeprom_channel ** eeprom_ch_info,const u8 ** eeprom_ch_index)773 static void iwl_init_band_reference(const struct iwl_priv *priv,
774 int eep_band, int *eeprom_ch_count,
775 const struct iwl_eeprom_channel **eeprom_ch_info,
776 const u8 **eeprom_ch_index)
777 {
778 struct iwl_shared *shrd = priv->shrd;
779 u32 offset = cfg(priv)->lib->
780 eeprom_ops.regulatory_bands[eep_band - 1];
781 switch (eep_band) {
782 case 1: /* 2.4GHz band */
783 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
784 *eeprom_ch_info = (struct iwl_eeprom_channel *)
785 iwl_eeprom_query_addr(shrd, offset);
786 *eeprom_ch_index = iwl_eeprom_band_1;
787 break;
788 case 2: /* 4.9GHz band */
789 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
790 *eeprom_ch_info = (struct iwl_eeprom_channel *)
791 iwl_eeprom_query_addr(shrd, offset);
792 *eeprom_ch_index = iwl_eeprom_band_2;
793 break;
794 case 3: /* 5.2GHz band */
795 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
796 *eeprom_ch_info = (struct iwl_eeprom_channel *)
797 iwl_eeprom_query_addr(shrd, offset);
798 *eeprom_ch_index = iwl_eeprom_band_3;
799 break;
800 case 4: /* 5.5GHz band */
801 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
802 *eeprom_ch_info = (struct iwl_eeprom_channel *)
803 iwl_eeprom_query_addr(shrd, offset);
804 *eeprom_ch_index = iwl_eeprom_band_4;
805 break;
806 case 5: /* 5.7GHz band */
807 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
808 *eeprom_ch_info = (struct iwl_eeprom_channel *)
809 iwl_eeprom_query_addr(shrd, offset);
810 *eeprom_ch_index = iwl_eeprom_band_5;
811 break;
812 case 6: /* 2.4GHz ht40 channels */
813 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
814 *eeprom_ch_info = (struct iwl_eeprom_channel *)
815 iwl_eeprom_query_addr(shrd, offset);
816 *eeprom_ch_index = iwl_eeprom_band_6;
817 break;
818 case 7: /* 5 GHz ht40 channels */
819 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
820 *eeprom_ch_info = (struct iwl_eeprom_channel *)
821 iwl_eeprom_query_addr(shrd, offset);
822 *eeprom_ch_index = iwl_eeprom_band_7;
823 break;
824 default:
825 BUG();
826 return;
827 }
828 }
829
830 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
831 ? # x " " : "")
832 /**
833 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
834 *
835 * Does not set up a command, or touch hardware.
836 */
iwl_mod_ht40_chan_info(struct iwl_priv * priv,enum ieee80211_band band,u16 channel,const struct iwl_eeprom_channel * eeprom_ch,u8 clear_ht40_extension_channel)837 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
838 enum ieee80211_band band, u16 channel,
839 const struct iwl_eeprom_channel *eeprom_ch,
840 u8 clear_ht40_extension_channel)
841 {
842 struct iwl_channel_info *ch_info;
843
844 ch_info = (struct iwl_channel_info *)
845 iwl_get_channel_info(priv, band, channel);
846
847 if (!is_channel_valid(ch_info))
848 return -1;
849
850 IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
851 " Ad-Hoc %ssupported\n",
852 ch_info->channel,
853 is_channel_a_band(ch_info) ?
854 "5.2" : "2.4",
855 CHECK_AND_PRINT(IBSS),
856 CHECK_AND_PRINT(ACTIVE),
857 CHECK_AND_PRINT(RADAR),
858 CHECK_AND_PRINT(WIDE),
859 CHECK_AND_PRINT(DFS),
860 eeprom_ch->flags,
861 eeprom_ch->max_power_avg,
862 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
863 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
864 "" : "not ");
865
866 ch_info->ht40_eeprom = *eeprom_ch;
867 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
868 ch_info->ht40_flags = eeprom_ch->flags;
869 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
870 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
871
872 return 0;
873 }
874
875 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
876 ? # x " " : "")
877
878 /**
879 * iwl_init_channel_map - Set up driver's info for all possible channels
880 */
iwl_init_channel_map(struct iwl_priv * priv)881 int iwl_init_channel_map(struct iwl_priv *priv)
882 {
883 int eeprom_ch_count = 0;
884 const u8 *eeprom_ch_index = NULL;
885 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
886 int band, ch;
887 struct iwl_channel_info *ch_info;
888
889 if (priv->channel_count) {
890 IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
891 return 0;
892 }
893
894 IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
895
896 priv->channel_count =
897 ARRAY_SIZE(iwl_eeprom_band_1) +
898 ARRAY_SIZE(iwl_eeprom_band_2) +
899 ARRAY_SIZE(iwl_eeprom_band_3) +
900 ARRAY_SIZE(iwl_eeprom_band_4) +
901 ARRAY_SIZE(iwl_eeprom_band_5);
902
903 IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
904 priv->channel_count);
905
906 priv->channel_info = kcalloc(priv->channel_count,
907 sizeof(struct iwl_channel_info),
908 GFP_KERNEL);
909 if (!priv->channel_info) {
910 IWL_ERR(priv, "Could not allocate channel_info\n");
911 priv->channel_count = 0;
912 return -ENOMEM;
913 }
914
915 ch_info = priv->channel_info;
916
917 /* Loop through the 5 EEPROM bands adding them in order to the
918 * channel map we maintain (that contains additional information than
919 * what just in the EEPROM) */
920 for (band = 1; band <= 5; band++) {
921
922 iwl_init_band_reference(priv, band, &eeprom_ch_count,
923 &eeprom_ch_info, &eeprom_ch_index);
924
925 /* Loop through each band adding each of the channels */
926 for (ch = 0; ch < eeprom_ch_count; ch++) {
927 ch_info->channel = eeprom_ch_index[ch];
928 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
929 IEEE80211_BAND_5GHZ;
930
931 /* permanently store EEPROM's channel regulatory flags
932 * and max power in channel info database. */
933 ch_info->eeprom = eeprom_ch_info[ch];
934
935 /* Copy the run-time flags so they are there even on
936 * invalid channels */
937 ch_info->flags = eeprom_ch_info[ch].flags;
938 /* First write that ht40 is not enabled, and then enable
939 * one by one */
940 ch_info->ht40_extension_channel =
941 IEEE80211_CHAN_NO_HT40;
942
943 if (!(is_channel_valid(ch_info))) {
944 IWL_DEBUG_EEPROM(priv,
945 "Ch. %d Flags %x [%sGHz] - "
946 "No traffic\n",
947 ch_info->channel,
948 ch_info->flags,
949 is_channel_a_band(ch_info) ?
950 "5.2" : "2.4");
951 ch_info++;
952 continue;
953 }
954
955 /* Initialize regulatory-based run-time data */
956 ch_info->max_power_avg = ch_info->curr_txpow =
957 eeprom_ch_info[ch].max_power_avg;
958 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
959 ch_info->min_power = 0;
960
961 IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
962 "%s%s%s%s%s%s(0x%02x %ddBm):"
963 " Ad-Hoc %ssupported\n",
964 ch_info->channel,
965 is_channel_a_band(ch_info) ?
966 "5.2" : "2.4",
967 CHECK_AND_PRINT_I(VALID),
968 CHECK_AND_PRINT_I(IBSS),
969 CHECK_AND_PRINT_I(ACTIVE),
970 CHECK_AND_PRINT_I(RADAR),
971 CHECK_AND_PRINT_I(WIDE),
972 CHECK_AND_PRINT_I(DFS),
973 eeprom_ch_info[ch].flags,
974 eeprom_ch_info[ch].max_power_avg,
975 ((eeprom_ch_info[ch].
976 flags & EEPROM_CHANNEL_IBSS)
977 && !(eeprom_ch_info[ch].
978 flags & EEPROM_CHANNEL_RADAR))
979 ? "" : "not ");
980
981 ch_info++;
982 }
983 }
984
985 /* Check if we do have HT40 channels */
986 if (cfg(priv)->lib->eeprom_ops.regulatory_bands[5] ==
987 EEPROM_REGULATORY_BAND_NO_HT40 &&
988 cfg(priv)->lib->eeprom_ops.regulatory_bands[6] ==
989 EEPROM_REGULATORY_BAND_NO_HT40)
990 return 0;
991
992 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
993 for (band = 6; band <= 7; band++) {
994 enum ieee80211_band ieeeband;
995
996 iwl_init_band_reference(priv, band, &eeprom_ch_count,
997 &eeprom_ch_info, &eeprom_ch_index);
998
999 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1000 ieeeband =
1001 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1002
1003 /* Loop through each band adding each of the channels */
1004 for (ch = 0; ch < eeprom_ch_count; ch++) {
1005 /* Set up driver's info for lower half */
1006 iwl_mod_ht40_chan_info(priv, ieeeband,
1007 eeprom_ch_index[ch],
1008 &eeprom_ch_info[ch],
1009 IEEE80211_CHAN_NO_HT40PLUS);
1010
1011 /* Set up driver's info for upper half */
1012 iwl_mod_ht40_chan_info(priv, ieeeband,
1013 eeprom_ch_index[ch] + 4,
1014 &eeprom_ch_info[ch],
1015 IEEE80211_CHAN_NO_HT40MINUS);
1016 }
1017 }
1018
1019 /* for newer device (6000 series and up)
1020 * EEPROM contain enhanced tx power information
1021 * driver need to process addition information
1022 * to determine the max channel tx power limits
1023 */
1024 if (cfg(priv)->lib->eeprom_ops.update_enhanced_txpower)
1025 cfg(priv)->lib->eeprom_ops.update_enhanced_txpower(priv);
1026
1027 return 0;
1028 }
1029
1030 /*
1031 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
1032 */
iwl_free_channel_map(struct iwl_priv * priv)1033 void iwl_free_channel_map(struct iwl_priv *priv)
1034 {
1035 kfree(priv->channel_info);
1036 priv->channel_count = 0;
1037 }
1038
1039 /**
1040 * iwl_get_channel_info - Find driver's private channel info
1041 *
1042 * Based on band and channel number.
1043 */
iwl_get_channel_info(const struct iwl_priv * priv,enum ieee80211_band band,u16 channel)1044 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
1045 enum ieee80211_band band, u16 channel)
1046 {
1047 int i;
1048
1049 switch (band) {
1050 case IEEE80211_BAND_5GHZ:
1051 for (i = 14; i < priv->channel_count; i++) {
1052 if (priv->channel_info[i].channel == channel)
1053 return &priv->channel_info[i];
1054 }
1055 break;
1056 case IEEE80211_BAND_2GHZ:
1057 if (channel >= 1 && channel <= 14)
1058 return &priv->channel_info[channel - 1];
1059 break;
1060 default:
1061 BUG();
1062 }
1063
1064 return NULL;
1065 }
1066
iwl_rf_config(struct iwl_priv * priv)1067 void iwl_rf_config(struct iwl_priv *priv)
1068 {
1069 u16 radio_cfg;
1070
1071 radio_cfg = iwl_eeprom_query16(priv->shrd, EEPROM_RADIO_CONFIG);
1072
1073 /* write radio config values to register */
1074 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
1075 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
1076 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
1077 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
1078 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1079 IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
1080 EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
1081 EEPROM_RF_CFG_STEP_MSK(radio_cfg),
1082 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1083 } else
1084 WARN_ON(1);
1085
1086 /* set CSR_HW_CONFIG_REG for uCode use */
1087 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
1088 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
1089 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
1090 }
1091