1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26 #ifndef __il_core_h__
27 #define __il_core_h__
28
29 #include <linux/interrupt.h>
30 #include <linux/pci.h> /* for struct pci_device_id */
31 #include <linux/kernel.h>
32 #include <linux/leds.h>
33 #include <linux/wait.h>
34 #include <linux/io.h>
35 #include <net/mac80211.h>
36 #include <net/ieee80211_radiotap.h>
37
38 #include "commands.h"
39 #include "csr.h"
40 #include "prph.h"
41
42 struct il_host_cmd;
43 struct il_cmd;
44 struct il_tx_queue;
45
46 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
50 #define RX_QUEUE_SIZE 256
51 #define RX_QUEUE_MASK 255
52 #define RX_QUEUE_SIZE_LOG 8
53
54 /*
55 * RX related structures and functions
56 */
57 #define RX_FREE_BUFFERS 64
58 #define RX_LOW_WATERMARK 8
59
60 #define U32_PAD(n) ((4-(n))&0x3)
61
62 /* CT-KILL constants */
63 #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
64
65 /* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon stats being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78 /*
79 * RTS threshold here is total size [2347] minus 4 FCS bytes
80 * Per spec:
81 * a value of 0 means RTS on all data/management packets
82 * a value > max MSDU size means no RTS
83 * else RTS for data/management frames where MPDU is larger
84 * than RTS value.
85 */
86 #define DEFAULT_RTS_THRESHOLD 2347U
87 #define MIN_RTS_THRESHOLD 0U
88 #define MAX_RTS_THRESHOLD 2347U
89 #define MAX_MSDU_SIZE 2304U
90 #define MAX_MPDU_SIZE 2346U
91 #define DEFAULT_BEACON_INTERVAL 100U
92 #define DEFAULT_SHORT_RETRY_LIMIT 7U
93 #define DEFAULT_LONG_RETRY_LIMIT 4U
94
95 struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99 };
100
101 #define rxb_addr(r) page_address(r->page)
102
103 /* defined below */
104 struct il_device_cmd;
105
106 struct il_cmd_meta {
107 /* only for SYNC commands, iff the reply skb is wanted */
108 struct il_host_cmd *source;
109 /*
110 * only for ASYNC commands
111 * (which is somewhat stupid -- look at common.c for instance
112 * which duplicates a bunch of code because the callback isn't
113 * invoked for SYNC commands, if it were and its result passed
114 * through it would be simpler...)
115 */
116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
118
119 /* The CMD_SIZE_HUGE flag bit indicates that the command
120 * structure is stored at the end of the shared queue memory. */
121 u32 flags;
122
123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
125 };
126
127 /*
128 * Generic queue structure
129 *
130 * Contains common data for Rx and Tx queues
131 */
132 struct il_queue {
133 int n_bd; /* number of BDs in this queue */
134 int write_ptr; /* 1-st empty entry (idx) host_w */
135 int read_ptr; /* last used entry (idx) host_r */
136 /* use for monitoring and recovering the stuck queue */
137 dma_addr_t dma_addr; /* physical addr for BD's */
138 int n_win; /* safe queue win */
139 u32 id;
140 int low_mark; /* low watermark, resume queue if free
141 * space more than this */
142 int high_mark; /* high watermark, stop queue if free
143 * space less than this */
144 };
145
146 /* One for each TFD */
147 struct il_tx_info {
148 struct sk_buff *skb;
149 struct il_rxon_context *ctx;
150 };
151
152 /**
153 * struct il_tx_queue - Tx Queue for DMA
154 * @q: generic Rx/Tx queue descriptor
155 * @bd: base of circular buffer of TFDs
156 * @cmd: array of command/TX buffer pointers
157 * @meta: array of meta data for each command/tx buffer
158 * @dma_addr_cmd: physical address of cmd/tx buffer array
159 * @txb: array of per-TFD driver data
160 * @time_stamp: time (in jiffies) of last read_ptr change
161 * @need_update: indicates need to update read/write idx
162 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
163 *
164 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
165 * descriptors) and required locking structures.
166 */
167 #define TFD_TX_CMD_SLOTS 256
168 #define TFD_CMD_SLOTS 32
169
170 struct il_tx_queue {
171 struct il_queue q;
172 void *tfds;
173 struct il_device_cmd **cmd;
174 struct il_cmd_meta *meta;
175 struct il_tx_info *txb;
176 unsigned long time_stamp;
177 u8 need_update;
178 u8 sched_retry;
179 u8 active;
180 u8 swq_id;
181 };
182
183 /*
184 * EEPROM access time values:
185 *
186 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
187 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
188 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
189 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
190 */
191 #define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
192
193 #define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
194 #define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
195
196 /*
197 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
198 *
199 * IBSS and/or AP operation is allowed *only* on those channels with
200 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
201 * RADAR detection is not supported by the 4965 driver, but is a
202 * requirement for establishing a new network for legal operation on channels
203 * requiring RADAR detection or restricting ACTIVE scanning.
204 *
205 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
206 * It only indicates that 20 MHz channel use is supported; HT40 channel
207 * usage is indicated by a separate set of regulatory flags for each
208 * HT40 channel pair.
209 *
210 * NOTE: Using a channel inappropriately will result in a uCode error!
211 */
212 #define IL_NUM_TX_CALIB_GROUPS 5
213 enum {
214 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
215 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
216 /* Bit 2 Reserved */
217 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
218 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
219 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
220 /* Bit 6 Reserved (was Narrow Channel) */
221 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
222 };
223
224 /* SKU Capabilities */
225 /* 3945 only */
226 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
227 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
228
229 /* *regulatory* channel data format in eeprom, one for each channel.
230 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
231 struct il_eeprom_channel {
232 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
233 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
234 } __packed;
235
236 /* 3945 Specific */
237 #define EEPROM_3945_EEPROM_VERSION (0x2f)
238
239 /* 4965 has two radio transmitters (and 3 radio receivers) */
240 #define EEPROM_TX_POWER_TX_CHAINS (2)
241
242 /* 4965 has room for up to 8 sets of txpower calibration data */
243 #define EEPROM_TX_POWER_BANDS (8)
244
245 /* 4965 factory calibration measures txpower gain settings for
246 * each of 3 target output levels */
247 #define EEPROM_TX_POWER_MEASUREMENTS (3)
248
249 /* 4965 Specific */
250 /* 4965 driver does not work with txpower calibration version < 5 */
251 #define EEPROM_4965_TX_POWER_VERSION (5)
252 #define EEPROM_4965_EEPROM_VERSION (0x2f)
253 #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
254 #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
255 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
256 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
257
258 /* 2.4 GHz */
259 extern const u8 il_eeprom_band_1[14];
260
261 /*
262 * factory calibration data for one txpower level, on one channel,
263 * measured on one of the 2 tx chains (radio transmitter and associated
264 * antenna). EEPROM contains:
265 *
266 * 1) Temperature (degrees Celsius) of device when measurement was made.
267 *
268 * 2) Gain table idx used to achieve the target measurement power.
269 * This refers to the "well-known" gain tables (see 4965.h).
270 *
271 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
272 *
273 * 4) RF power amplifier detector level measurement (not used).
274 */
275 struct il_eeprom_calib_measure {
276 u8 temperature; /* Device temperature (Celsius) */
277 u8 gain_idx; /* Index into gain table */
278 u8 actual_pow; /* Measured RF output power, half-dBm */
279 s8 pa_det; /* Power amp detector level (not used) */
280 } __packed;
281
282 /*
283 * measurement set for one channel. EEPROM contains:
284 *
285 * 1) Channel number measured
286 *
287 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
288 * (a.k.a. "tx chains") (6 measurements altogether)
289 */
290 struct il_eeprom_calib_ch_info {
291 u8 ch_num;
292 struct il_eeprom_calib_measure
293 measurements[EEPROM_TX_POWER_TX_CHAINS]
294 [EEPROM_TX_POWER_MEASUREMENTS];
295 } __packed;
296
297 /*
298 * txpower subband info.
299 *
300 * For each frequency subband, EEPROM contains the following:
301 *
302 * 1) First and last channels within range of the subband. "0" values
303 * indicate that this sample set is not being used.
304 *
305 * 2) Sample measurement sets for 2 channels close to the range endpoints.
306 */
307 struct il_eeprom_calib_subband_info {
308 u8 ch_from; /* channel number of lowest channel in subband */
309 u8 ch_to; /* channel number of highest channel in subband */
310 struct il_eeprom_calib_ch_info ch1;
311 struct il_eeprom_calib_ch_info ch2;
312 } __packed;
313
314 /*
315 * txpower calibration info. EEPROM contains:
316 *
317 * 1) Factory-measured saturation power levels (maximum levels at which
318 * tx power amplifier can output a signal without too much distortion).
319 * There is one level for 2.4 GHz band and one for 5 GHz band. These
320 * values apply to all channels within each of the bands.
321 *
322 * 2) Factory-measured power supply voltage level. This is assumed to be
323 * constant (i.e. same value applies to all channels/bands) while the
324 * factory measurements are being made.
325 *
326 * 3) Up to 8 sets of factory-measured txpower calibration values.
327 * These are for different frequency ranges, since txpower gain
328 * characteristics of the analog radio circuitry vary with frequency.
329 *
330 * Not all sets need to be filled with data;
331 * struct il_eeprom_calib_subband_info contains range of channels
332 * (0 if unused) for each set of data.
333 */
334 struct il_eeprom_calib_info {
335 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
336 u8 saturation_power52; /* half-dBm */
337 __le16 voltage; /* signed */
338 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
339 } __packed;
340
341 /* General */
342 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
343 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
344 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
345 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
346 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
347 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
348 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
349 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
350 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
351 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
352
353 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
354 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
355 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
356 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
357 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
358 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
359 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
360
361 #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
362 #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
363
364 /*
365 * Per-channel regulatory data.
366 *
367 * Each channel that *might* be supported by iwl has a fixed location
368 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
369 * txpower (MSB).
370 *
371 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
372 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
373 *
374 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
375 */
376 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
377 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
378 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
379
380 /*
381 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
382 * 5.0 GHz channels 7, 8, 11, 12, 16
383 * (4915-5080MHz) (none of these is ever supported)
384 */
385 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
386 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
387
388 /*
389 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
390 * (5170-5320MHz)
391 */
392 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
393 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
394
395 /*
396 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
397 * (5500-5700MHz)
398 */
399 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
400 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
401
402 /*
403 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
404 * (5725-5825MHz)
405 */
406 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
407 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
408
409 /*
410 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
411 *
412 * The channel listed is the center of the lower 20 MHz half of the channel.
413 * The overall center frequency is actually 2 channels (10 MHz) above that,
414 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
415 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
416 * and the overall HT40 channel width centers on channel 3.
417 *
418 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
419 * control channel to which to tune. RXON also specifies whether the
420 * control channel is the upper or lower half of a HT40 channel.
421 *
422 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
423 */
424 #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
425
426 /*
427 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
428 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
429 */
430 #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
431
432 #define EEPROM_REGULATORY_BAND_NO_HT40 (0)
433
434 struct il_eeprom_ops {
435 const u32 regulatory_bands[7];
436 int (*acquire_semaphore) (struct il_priv *il);
437 void (*release_semaphore) (struct il_priv *il);
438 };
439
440 int il_eeprom_init(struct il_priv *il);
441 void il_eeprom_free(struct il_priv *il);
442 const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
443 u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
444 int il_init_channel_map(struct il_priv *il);
445 void il_free_channel_map(struct il_priv *il);
446 const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
447 enum ieee80211_band band,
448 u16 channel);
449
450 #define IL_NUM_SCAN_RATES (2)
451
452 struct il4965_channel_tgd_info {
453 u8 type;
454 s8 max_power;
455 };
456
457 struct il4965_channel_tgh_info {
458 s64 last_radar_time;
459 };
460
461 #define IL4965_MAX_RATE (33)
462
463 struct il3945_clip_group {
464 /* maximum power level to prevent clipping for each rate, derived by
465 * us from this band's saturation power in EEPROM */
466 const s8 clip_powers[IL_MAX_RATES];
467 };
468
469 /* current Tx power values to use, one for each rate for each channel.
470 * requested power is limited by:
471 * -- regulatory EEPROM limits for this channel
472 * -- hardware capabilities (clip-powers)
473 * -- spectrum management
474 * -- user preference (e.g. iwconfig)
475 * when requested power is set, base power idx must also be set. */
476 struct il3945_channel_power_info {
477 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
478 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
479 s8 base_power_idx; /* gain idx for power at factory temp. */
480 s8 requested_power; /* power (dBm) requested for this chnl/rate */
481 };
482
483 /* current scan Tx power values to use, one for each scan rate for each
484 * channel. */
485 struct il3945_scan_power_info {
486 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
487 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
488 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
489 };
490
491 /*
492 * One for each channel, holds all channel setup data
493 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
494 * with one another!
495 */
496 struct il_channel_info {
497 struct il4965_channel_tgd_info tgd;
498 struct il4965_channel_tgh_info tgh;
499 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
500 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
501 * HT40 channel */
502
503 u8 channel; /* channel number */
504 u8 flags; /* flags copied from EEPROM */
505 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
506 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
507 s8 min_power; /* always 0 */
508 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
509
510 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
511 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
512 enum ieee80211_band band;
513
514 /* HT40 channel info */
515 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
516 u8 ht40_flags; /* flags copied from EEPROM */
517 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
518
519 /* Radio/DSP gain settings for each "normal" data Tx rate.
520 * These include, in addition to RF and DSP gain, a few fields for
521 * remembering/modifying gain settings (idxes). */
522 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
523
524 /* Radio/DSP gain settings for each scan rate, for directed scans. */
525 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
526 };
527
528 #define IL_TX_FIFO_BK 0 /* shared */
529 #define IL_TX_FIFO_BE 1
530 #define IL_TX_FIFO_VI 2 /* shared */
531 #define IL_TX_FIFO_VO 3
532 #define IL_TX_FIFO_UNUSED -1
533
534 /* Minimum number of queues. MAX_NUM is defined in hw specific files.
535 * Set the minimum to accommodate the 4 standard TX queues, 1 command
536 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
537 #define IL_MIN_NUM_QUEUES 10
538
539 #define IL_DEFAULT_CMD_QUEUE_NUM 4
540
541 #define IEEE80211_DATA_LEN 2304
542 #define IEEE80211_4ADDR_LEN 30
543 #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
544 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
545
546 struct il_frame {
547 union {
548 struct ieee80211_hdr frame;
549 struct il_tx_beacon_cmd beacon;
550 u8 raw[IEEE80211_FRAME_LEN];
551 u8 cmd[360];
552 } u;
553 struct list_head list;
554 };
555
556 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
557 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
558 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
559
560 enum {
561 CMD_SYNC = 0,
562 CMD_SIZE_NORMAL = 0,
563 CMD_NO_SKB = 0,
564 CMD_SIZE_HUGE = (1 << 0),
565 CMD_ASYNC = (1 << 1),
566 CMD_WANT_SKB = (1 << 2),
567 CMD_MAPPED = (1 << 3),
568 };
569
570 #define DEF_CMD_PAYLOAD_SIZE 320
571
572 /**
573 * struct il_device_cmd
574 *
575 * For allocation of the command and tx queues, this establishes the overall
576 * size of the largest command we send to uCode, except for a scan command
577 * (which is relatively huge; space is allocated separately).
578 */
579 struct il_device_cmd {
580 struct il_cmd_header hdr; /* uCode API */
581 union {
582 u32 flags;
583 u8 val8;
584 u16 val16;
585 u32 val32;
586 struct il_tx_cmd tx;
587 u8 payload[DEF_CMD_PAYLOAD_SIZE];
588 } __packed cmd;
589 } __packed;
590
591 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
592
593 struct il_host_cmd {
594 const void *data;
595 unsigned long reply_page;
596 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
597 struct il_rx_pkt *pkt);
598 u32 flags;
599 u16 len;
600 u8 id;
601 };
602
603 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
604 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
605 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
606
607 /**
608 * struct il_rx_queue - Rx queue
609 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
610 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
611 * @read: Shared idx to newest available Rx buffer
612 * @write: Shared idx to oldest written Rx packet
613 * @free_count: Number of pre-allocated buffers in rx_free
614 * @rx_free: list of free SKBs for use
615 * @rx_used: List of Rx buffers with no SKB
616 * @need_update: flag to indicate we need to update read/write idx
617 * @rb_stts: driver's pointer to receive buffer status
618 * @rb_stts_dma: bus address of receive buffer status
619 *
620 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
621 */
622 struct il_rx_queue {
623 __le32 *bd;
624 dma_addr_t bd_dma;
625 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
626 struct il_rx_buf *queue[RX_QUEUE_SIZE];
627 u32 read;
628 u32 write;
629 u32 free_count;
630 u32 write_actual;
631 struct list_head rx_free;
632 struct list_head rx_used;
633 int need_update;
634 struct il_rb_status *rb_stts;
635 dma_addr_t rb_stts_dma;
636 spinlock_t lock;
637 };
638
639 #define IL_SUPPORTED_RATES_IE_LEN 8
640
641 #define MAX_TID_COUNT 9
642
643 #define IL_INVALID_RATE 0xFF
644 #define IL_INVALID_VALUE -1
645
646 /**
647 * struct il_ht_agg -- aggregation status while waiting for block-ack
648 * @txq_id: Tx queue used for Tx attempt
649 * @frame_count: # frames attempted by Tx command
650 * @wait_for_ba: Expect block-ack before next Tx reply
651 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
652 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
653 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
654 * @rate_n_flags: Rate at which Tx was attempted
655 *
656 * If C_TX indicates that aggregation was attempted, driver must wait
657 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
658 * until block ack arrives.
659 */
660 struct il_ht_agg {
661 u16 txq_id;
662 u16 frame_count;
663 u16 wait_for_ba;
664 u16 start_idx;
665 u64 bitmap;
666 u32 rate_n_flags;
667 #define IL_AGG_OFF 0
668 #define IL_AGG_ON 1
669 #define IL_EMPTYING_HW_QUEUE_ADDBA 2
670 #define IL_EMPTYING_HW_QUEUE_DELBA 3
671 u8 state;
672 };
673
674 struct il_tid_data {
675 u16 seq_number; /* 4965 only */
676 u16 tfds_in_queue;
677 struct il_ht_agg agg;
678 };
679
680 struct il_hw_key {
681 u32 cipher;
682 int keylen;
683 u8 keyidx;
684 u8 key[32];
685 };
686
687 union il_ht_rate_supp {
688 u16 rates;
689 struct {
690 u8 siso_rate;
691 u8 mimo_rate;
692 };
693 };
694
695 #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
696 #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
697 #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
698 #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
699 #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
700 #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
701 #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
702
703 /*
704 * Maximal MPDU density for TX aggregation
705 * 4 - 2us density
706 * 5 - 4us density
707 * 6 - 8us density
708 * 7 - 16us density
709 */
710 #define CFG_HT_MPDU_DENSITY_2USEC (0x4)
711 #define CFG_HT_MPDU_DENSITY_4USEC (0x5)
712 #define CFG_HT_MPDU_DENSITY_8USEC (0x6)
713 #define CFG_HT_MPDU_DENSITY_16USEC (0x7)
714 #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
715 #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
716 #define CFG_HT_MPDU_DENSITY_MIN (0x1)
717
718 struct il_ht_config {
719 bool single_chain_sufficient;
720 enum ieee80211_smps_mode smps; /* current smps mode */
721 };
722
723 /* QoS structures */
724 struct il_qos_info {
725 int qos_active;
726 struct il_qosparam_cmd def_qos_parm;
727 };
728
729 /*
730 * Structure should be accessed with sta_lock held. When station addition
731 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
732 * the commands (il_addsta_cmd and il_link_quality_cmd) without
733 * sta_lock held.
734 */
735 struct il_station_entry {
736 struct il_addsta_cmd sta;
737 struct il_tid_data tid[MAX_TID_COUNT];
738 u8 used, ctxid;
739 struct il_hw_key keyinfo;
740 struct il_link_quality_cmd *lq;
741 };
742
743 struct il_station_priv_common {
744 struct il_rxon_context *ctx;
745 u8 sta_id;
746 };
747
748 /**
749 * struct il_vif_priv - driver's ilate per-interface information
750 *
751 * When mac80211 allocates a virtual interface, it can allocate
752 * space for us to put data into.
753 */
754 struct il_vif_priv {
755 struct il_rxon_context *ctx;
756 u8 ibss_bssid_sta_id;
757 };
758
759 /* one for each uCode image (inst/data, boot/init/runtime) */
760 struct fw_desc {
761 void *v_addr; /* access by driver */
762 dma_addr_t p_addr; /* access by card's busmaster DMA */
763 u32 len; /* bytes */
764 };
765
766 /* uCode file layout */
767 struct il_ucode_header {
768 __le32 ver; /* major/minor/API/serial */
769 struct {
770 __le32 inst_size; /* bytes of runtime code */
771 __le32 data_size; /* bytes of runtime data */
772 __le32 init_size; /* bytes of init code */
773 __le32 init_data_size; /* bytes of init data */
774 __le32 boot_size; /* bytes of bootstrap code */
775 u8 data[0]; /* in same order as sizes */
776 } v1;
777 };
778
779 struct il4965_ibss_seq {
780 u8 mac[ETH_ALEN];
781 u16 seq_num;
782 u16 frag_num;
783 unsigned long packet_time;
784 struct list_head list;
785 };
786
787 struct il_sensitivity_ranges {
788 u16 min_nrg_cck;
789 u16 max_nrg_cck;
790
791 u16 nrg_th_cck;
792 u16 nrg_th_ofdm;
793
794 u16 auto_corr_min_ofdm;
795 u16 auto_corr_min_ofdm_mrc;
796 u16 auto_corr_min_ofdm_x1;
797 u16 auto_corr_min_ofdm_mrc_x1;
798
799 u16 auto_corr_max_ofdm;
800 u16 auto_corr_max_ofdm_mrc;
801 u16 auto_corr_max_ofdm_x1;
802 u16 auto_corr_max_ofdm_mrc_x1;
803
804 u16 auto_corr_max_cck;
805 u16 auto_corr_max_cck_mrc;
806 u16 auto_corr_min_cck;
807 u16 auto_corr_min_cck_mrc;
808
809 u16 barker_corr_th_min;
810 u16 barker_corr_th_min_mrc;
811 u16 nrg_th_cca;
812 };
813
814 #define KELVIN_TO_CELSIUS(x) ((x)-273)
815 #define CELSIUS_TO_KELVIN(x) ((x)+273)
816
817 /**
818 * struct il_hw_params
819 * @max_txq_num: Max # Tx queues supported
820 * @dma_chnl_num: Number of Tx DMA/FIFO channels
821 * @scd_bc_tbls_size: size of scheduler byte count tables
822 * @tfd_size: TFD size
823 * @tx/rx_chains_num: Number of TX/RX chains
824 * @valid_tx/rx_ant: usable antennas
825 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
826 * @max_rxq_log: Log-base-2 of max_rxq_size
827 * @rx_page_order: Rx buffer page order
828 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
829 * @max_stations:
830 * @ht40_channel: is 40MHz width possible in band 2.4
831 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
832 * @sw_crypto: 0 for hw, 1 for sw
833 * @max_xxx_size: for ucode uses
834 * @ct_kill_threshold: temperature threshold
835 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
836 * @struct il_sensitivity_ranges: range of sensitivity values
837 */
838 struct il_hw_params {
839 u8 max_txq_num;
840 u8 dma_chnl_num;
841 u16 scd_bc_tbls_size;
842 u32 tfd_size;
843 u8 tx_chains_num;
844 u8 rx_chains_num;
845 u8 valid_tx_ant;
846 u8 valid_rx_ant;
847 u16 max_rxq_size;
848 u16 max_rxq_log;
849 u32 rx_page_order;
850 u32 rx_wrt_ptr_reg;
851 u8 max_stations;
852 u8 ht40_channel;
853 u8 max_beacon_itrvl; /* in 1024 ms */
854 u32 max_inst_size;
855 u32 max_data_size;
856 u32 max_bsm_size;
857 u32 ct_kill_threshold; /* value in hw-dependent units */
858 u16 beacon_time_tsf_bits;
859 const struct il_sensitivity_ranges *sens;
860 };
861
862 /******************************************************************************
863 *
864 * Functions implemented in core module which are forward declared here
865 * for use by iwl-[4-5].c
866 *
867 * NOTE: The implementation of these functions are not hardware specific
868 * which is why they are in the core module files.
869 *
870 * Naming convention --
871 * il_ <-- Is part of iwlwifi
872 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
873 * il4965_bg_ <-- Called from work queue context
874 * il4965_mac_ <-- mac80211 callback
875 *
876 ****************************************************************************/
877 extern void il4965_update_chain_flags(struct il_priv *il);
878 extern const u8 il_bcast_addr[ETH_ALEN];
879 extern int il_queue_space(const struct il_queue *q);
880 static inline int
il_queue_used(const struct il_queue * q,int i)881 il_queue_used(const struct il_queue *q, int i)
882 {
883 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
884 i < q->write_ptr) : !(i <
885 q->read_ptr
886 && i >=
887 q->
888 write_ptr);
889 }
890
891 static inline u8
il_get_cmd_idx(struct il_queue * q,u32 idx,int is_huge)892 il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
893 {
894 /*
895 * This is for init calibration result and scan command which
896 * required buffer > TFD_MAX_PAYLOAD_SIZE,
897 * the big buffer at end of command array
898 */
899 if (is_huge)
900 return q->n_win; /* must be power of 2 */
901
902 /* Otherwise, use normal size buffers */
903 return idx & (q->n_win - 1);
904 }
905
906 struct il_dma_ptr {
907 dma_addr_t dma;
908 void *addr;
909 size_t size;
910 };
911
912 #define IL_OPERATION_MODE_AUTO 0
913 #define IL_OPERATION_MODE_HT_ONLY 1
914 #define IL_OPERATION_MODE_MIXED 2
915 #define IL_OPERATION_MODE_20MHZ 3
916
917 #define IL_TX_CRC_SIZE 4
918 #define IL_TX_DELIMITER_SIZE 4
919
920 #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
921
922 /* Sensitivity and chain noise calibration */
923 #define INITIALIZATION_VALUE 0xFFFF
924 #define IL4965_CAL_NUM_BEACONS 20
925 #define IL_CAL_NUM_BEACONS 16
926 #define MAXIMUM_ALLOWED_PATHLOSS 15
927
928 #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
929
930 #define MAX_FA_OFDM 50
931 #define MIN_FA_OFDM 5
932 #define MAX_FA_CCK 50
933 #define MIN_FA_CCK 5
934
935 #define AUTO_CORR_STEP_OFDM 1
936
937 #define AUTO_CORR_STEP_CCK 3
938 #define AUTO_CORR_MAX_TH_CCK 160
939
940 #define NRG_DIFF 2
941 #define NRG_STEP_CCK 2
942 #define NRG_MARGIN 8
943 #define MAX_NUMBER_CCK_NO_FA 100
944
945 #define AUTO_CORR_CCK_MIN_VAL_DEF (125)
946
947 #define CHAIN_A 0
948 #define CHAIN_B 1
949 #define CHAIN_C 2
950 #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
951 #define ALL_BAND_FILTER 0xFF00
952 #define IN_BAND_FILTER 0xFF
953 #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
954
955 #define NRG_NUM_PREV_STAT_L 20
956 #define NUM_RX_CHAINS 3
957
958 enum il4965_false_alarm_state {
959 IL_FA_TOO_MANY = 0,
960 IL_FA_TOO_FEW = 1,
961 IL_FA_GOOD_RANGE = 2,
962 };
963
964 enum il4965_chain_noise_state {
965 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
966 IL_CHAIN_NOISE_ACCUMULATE,
967 IL_CHAIN_NOISE_CALIBRATED,
968 IL_CHAIN_NOISE_DONE,
969 };
970
971 enum il4965_calib_enabled_state {
972 IL_CALIB_DISABLED = 0, /* must be 0 */
973 IL_CALIB_ENABLED = 1,
974 };
975
976 /*
977 * enum il_calib
978 * defines the order in which results of initial calibrations
979 * should be sent to the runtime uCode
980 */
981 enum il_calib {
982 IL_CALIB_MAX,
983 };
984
985 /* Opaque calibration results */
986 struct il_calib_result {
987 void *buf;
988 size_t buf_len;
989 };
990
991 enum ucode_type {
992 UCODE_NONE = 0,
993 UCODE_INIT,
994 UCODE_RT
995 };
996
997 /* Sensitivity calib data */
998 struct il_sensitivity_data {
999 u32 auto_corr_ofdm;
1000 u32 auto_corr_ofdm_mrc;
1001 u32 auto_corr_ofdm_x1;
1002 u32 auto_corr_ofdm_mrc_x1;
1003 u32 auto_corr_cck;
1004 u32 auto_corr_cck_mrc;
1005
1006 u32 last_bad_plcp_cnt_ofdm;
1007 u32 last_fa_cnt_ofdm;
1008 u32 last_bad_plcp_cnt_cck;
1009 u32 last_fa_cnt_cck;
1010
1011 u32 nrg_curr_state;
1012 u32 nrg_prev_state;
1013 u32 nrg_value[10];
1014 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
1015 u32 nrg_silence_ref;
1016 u32 nrg_energy_idx;
1017 u32 nrg_silence_idx;
1018 u32 nrg_th_cck;
1019 s32 nrg_auto_corr_silence_diff;
1020 u32 num_in_cck_no_fa;
1021 u32 nrg_th_ofdm;
1022
1023 u16 barker_corr_th_min;
1024 u16 barker_corr_th_min_mrc;
1025 u16 nrg_th_cca;
1026 };
1027
1028 /* Chain noise (differential Rx gain) calib data */
1029 struct il_chain_noise_data {
1030 u32 active_chains;
1031 u32 chain_noise_a;
1032 u32 chain_noise_b;
1033 u32 chain_noise_c;
1034 u32 chain_signal_a;
1035 u32 chain_signal_b;
1036 u32 chain_signal_c;
1037 u16 beacon_count;
1038 u8 disconn_array[NUM_RX_CHAINS];
1039 u8 delta_gain_code[NUM_RX_CHAINS];
1040 u8 radio_write;
1041 u8 state;
1042 };
1043
1044 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
1045 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1046
1047 #define IL_TRAFFIC_ENTRIES (256)
1048 #define IL_TRAFFIC_ENTRY_SIZE (64)
1049
1050 enum {
1051 MEASUREMENT_READY = (1 << 0),
1052 MEASUREMENT_ACTIVE = (1 << 1),
1053 };
1054
1055 /* interrupt stats */
1056 struct isr_stats {
1057 u32 hw;
1058 u32 sw;
1059 u32 err_code;
1060 u32 sch;
1061 u32 alive;
1062 u32 rfkill;
1063 u32 ctkill;
1064 u32 wakeup;
1065 u32 rx;
1066 u32 handlers[IL_CN_MAX];
1067 u32 tx;
1068 u32 unhandled;
1069 };
1070
1071 /* management stats */
1072 enum il_mgmt_stats {
1073 MANAGEMENT_ASSOC_REQ = 0,
1074 MANAGEMENT_ASSOC_RESP,
1075 MANAGEMENT_REASSOC_REQ,
1076 MANAGEMENT_REASSOC_RESP,
1077 MANAGEMENT_PROBE_REQ,
1078 MANAGEMENT_PROBE_RESP,
1079 MANAGEMENT_BEACON,
1080 MANAGEMENT_ATIM,
1081 MANAGEMENT_DISASSOC,
1082 MANAGEMENT_AUTH,
1083 MANAGEMENT_DEAUTH,
1084 MANAGEMENT_ACTION,
1085 MANAGEMENT_MAX,
1086 };
1087 /* control stats */
1088 enum il_ctrl_stats {
1089 CONTROL_BACK_REQ = 0,
1090 CONTROL_BACK,
1091 CONTROL_PSPOLL,
1092 CONTROL_RTS,
1093 CONTROL_CTS,
1094 CONTROL_ACK,
1095 CONTROL_CFEND,
1096 CONTROL_CFENDACK,
1097 CONTROL_MAX,
1098 };
1099
1100 struct traffic_stats {
1101 #ifdef CONFIG_IWLEGACY_DEBUGFS
1102 u32 mgmt[MANAGEMENT_MAX];
1103 u32 ctrl[CONTROL_MAX];
1104 u32 data_cnt;
1105 u64 data_bytes;
1106 #endif
1107 };
1108
1109 /*
1110 * host interrupt timeout value
1111 * used with setting interrupt coalescing timer
1112 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1113 *
1114 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1115 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1116 */
1117 #define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1118 #define IL_HOST_INT_TIMEOUT_DEF (0x40)
1119 #define IL_HOST_INT_TIMEOUT_MIN (0x0)
1120 #define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1121 #define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1122 #define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1123
1124 #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1125
1126 /* TX queue watchdog timeouts in mSecs */
1127 #define IL_DEF_WD_TIMEOUT (2000)
1128 #define IL_LONG_WD_TIMEOUT (10000)
1129 #define IL_MAX_WD_TIMEOUT (120000)
1130
1131 struct il_force_reset {
1132 int reset_request_count;
1133 int reset_success_count;
1134 int reset_reject_count;
1135 unsigned long reset_duration;
1136 unsigned long last_force_reset_jiffies;
1137 };
1138
1139 /* extend beacon time format bit shifting */
1140 /*
1141 * for _3945 devices
1142 * bits 31:24 - extended
1143 * bits 23:0 - interval
1144 */
1145 #define IL3945_EXT_BEACON_TIME_POS 24
1146 /*
1147 * for _4965 devices
1148 * bits 31:22 - extended
1149 * bits 21:0 - interval
1150 */
1151 #define IL4965_EXT_BEACON_TIME_POS 22
1152
1153 struct il_rxon_context {
1154 struct ieee80211_vif *vif;
1155
1156 const u8 *ac_to_fifo;
1157 const u8 *ac_to_queue;
1158 u8 mcast_queue;
1159
1160 /*
1161 * We could use the vif to indicate active, but we
1162 * also need it to be active during disabling when
1163 * we already removed the vif for type setting.
1164 */
1165 bool always_active, is_active;
1166
1167 bool ht_need_multiple_chains;
1168
1169 int ctxid;
1170
1171 u32 interface_modes, exclusive_interface_modes;
1172 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1173
1174 /*
1175 * We declare this const so it can only be
1176 * changed via explicit cast within the
1177 * routines that actually update the physical
1178 * hardware.
1179 */
1180 const struct il_rxon_cmd active;
1181 struct il_rxon_cmd staging;
1182
1183 struct il_rxon_time_cmd timing;
1184
1185 struct il_qos_info qos_data;
1186
1187 u8 bcast_sta_id, ap_sta_id;
1188
1189 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
1190 u8 qos_cmd;
1191 u8 wep_key_cmd;
1192
1193 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1194 u8 key_mapping_keys;
1195
1196 __le32 station_flags;
1197
1198 struct {
1199 bool non_gf_sta_present;
1200 u8 protection;
1201 bool enabled, is_40mhz;
1202 u8 extension_chan_offset;
1203 } ht;
1204 };
1205
1206 struct il_power_mgr {
1207 struct il_powertable_cmd sleep_cmd;
1208 struct il_powertable_cmd sleep_cmd_next;
1209 int debug_sleep_level_override;
1210 bool pci_pm;
1211 };
1212
1213 struct il_priv {
1214
1215 /* ieee device used by generic ieee processing code */
1216 struct ieee80211_hw *hw;
1217 struct ieee80211_channel *ieee_channels;
1218 struct ieee80211_rate *ieee_rates;
1219 struct il_cfg *cfg;
1220
1221 /* temporary frame storage list */
1222 struct list_head free_frames;
1223 int frames_count;
1224
1225 enum ieee80211_band band;
1226 int alloc_rxb_page;
1227
1228 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1229 struct il_rx_buf *rxb);
1230
1231 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1232
1233 /* spectrum measurement report caching */
1234 struct il_spectrum_notification measure_report;
1235 u8 measurement_status;
1236
1237 /* ucode beacon time */
1238 u32 ucode_beacon_time;
1239 int missed_beacon_threshold;
1240
1241 /* track IBSS manager (last beacon) status */
1242 u32 ibss_manager;
1243
1244 /* force reset */
1245 struct il_force_reset force_reset;
1246
1247 /* we allocate array of il_channel_info for NIC's valid channels.
1248 * Access via channel # using indirect idx array */
1249 struct il_channel_info *channel_info; /* channel info array */
1250 u8 channel_count; /* # of channels */
1251
1252 /* thermal calibration */
1253 s32 temperature; /* degrees Kelvin */
1254 s32 last_temperature;
1255
1256 /* init calibration results */
1257 struct il_calib_result calib_results[IL_CALIB_MAX];
1258
1259 /* Scan related variables */
1260 unsigned long scan_start;
1261 unsigned long scan_start_tsf;
1262 void *scan_cmd;
1263 enum ieee80211_band scan_band;
1264 struct cfg80211_scan_request *scan_request;
1265 struct ieee80211_vif *scan_vif;
1266 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1267 u8 mgmt_tx_ant;
1268
1269 /* spinlock */
1270 spinlock_t lock; /* protect general shared data */
1271 spinlock_t hcmd_lock; /* protect hcmd */
1272 spinlock_t reg_lock; /* protect hw register access */
1273 struct mutex mutex;
1274
1275 /* basic pci-network driver stuff */
1276 struct pci_dev *pci_dev;
1277
1278 /* pci hardware address support */
1279 void __iomem *hw_base;
1280 u32 hw_rev;
1281 u32 hw_wa_rev;
1282 u8 rev_id;
1283
1284 /* command queue number */
1285 u8 cmd_queue;
1286
1287 /* max number of station keys */
1288 u8 sta_key_max_num;
1289
1290 /* EEPROM MAC addresses */
1291 struct mac_address addresses[1];
1292
1293 /* uCode images, save to reload in case of failure */
1294 int fw_idx; /* firmware we're trying to load */
1295 u32 ucode_ver; /* version of ucode, copy of
1296 il_ucode.ver */
1297 struct fw_desc ucode_code; /* runtime inst */
1298 struct fw_desc ucode_data; /* runtime data original */
1299 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1300 struct fw_desc ucode_init; /* initialization inst */
1301 struct fw_desc ucode_init_data; /* initialization data */
1302 struct fw_desc ucode_boot; /* bootstrap inst */
1303 enum ucode_type ucode_type;
1304 u8 ucode_write_complete; /* the image write is complete */
1305 char firmware_name[25];
1306
1307 struct il_rxon_context ctx;
1308
1309 __le16 switch_channel;
1310
1311 /* 1st responses from initialize and runtime uCode images.
1312 * _4965's initialize alive response contains some calibration data. */
1313 struct il_init_alive_resp card_alive_init;
1314 struct il_alive_resp card_alive;
1315
1316 u16 active_rate;
1317
1318 u8 start_calib;
1319 struct il_sensitivity_data sensitivity_data;
1320 struct il_chain_noise_data chain_noise_data;
1321 __le16 sensitivity_tbl[HD_TBL_SIZE];
1322
1323 struct il_ht_config current_ht_config;
1324
1325 /* Rate scaling data */
1326 u8 retry_rate;
1327
1328 wait_queue_head_t wait_command_queue;
1329
1330 int activity_timer_active;
1331
1332 /* Rx and Tx DMA processing queues */
1333 struct il_rx_queue rxq;
1334 struct il_tx_queue *txq;
1335 unsigned long txq_ctx_active_msk;
1336 struct il_dma_ptr kw; /* keep warm address */
1337 struct il_dma_ptr scd_bc_tbls;
1338
1339 u32 scd_base_addr; /* scheduler sram base address */
1340
1341 unsigned long status;
1342
1343 /* counts mgmt, ctl, and data packets */
1344 struct traffic_stats tx_stats;
1345 struct traffic_stats rx_stats;
1346
1347 /* counts interrupts */
1348 struct isr_stats isr_stats;
1349
1350 struct il_power_mgr power_data;
1351
1352 /* context information */
1353 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
1354
1355 /* station table variables */
1356
1357 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1358 spinlock_t sta_lock;
1359 int num_stations;
1360 struct il_station_entry stations[IL_STATION_COUNT];
1361 unsigned long ucode_key_table;
1362
1363 /* queue refcounts */
1364 #define IL_MAX_HW_QUEUES 32
1365 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1366 /* for each AC */
1367 atomic_t queue_stop_count[4];
1368
1369 /* Indication if ieee80211_ops->open has been called */
1370 u8 is_open;
1371
1372 u8 mac80211_registered;
1373
1374 /* eeprom -- this is in the card's little endian byte order */
1375 u8 *eeprom;
1376 struct il_eeprom_calib_info *calib_info;
1377
1378 enum nl80211_iftype iw_mode;
1379
1380 /* Last Rx'd beacon timestamp */
1381 u64 timestamp;
1382
1383 union {
1384 #if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1385 struct {
1386 void *shared_virt;
1387 dma_addr_t shared_phys;
1388
1389 struct delayed_work thermal_periodic;
1390 struct delayed_work rfkill_poll;
1391
1392 struct il3945_notif_stats stats;
1393 #ifdef CONFIG_IWLEGACY_DEBUGFS
1394 struct il3945_notif_stats accum_stats;
1395 struct il3945_notif_stats delta_stats;
1396 struct il3945_notif_stats max_delta;
1397 #endif
1398
1399 u32 sta_supp_rates;
1400 int last_rx_rssi; /* From Rx packet stats */
1401
1402 /* Rx'd packet timing information */
1403 u32 last_beacon_time;
1404 u64 last_tsf;
1405
1406 /*
1407 * each calibration channel group in the
1408 * EEPROM has a derived clip setting for
1409 * each rate.
1410 */
1411 const struct il3945_clip_group clip_groups[5];
1412
1413 } _3945;
1414 #endif
1415 #if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1416 struct {
1417 struct il_rx_phy_res last_phy_res;
1418 bool last_phy_res_valid;
1419
1420 struct completion firmware_loading_complete;
1421
1422 /*
1423 * chain noise reset and gain commands are the
1424 * two extra calibration commands follows the standard
1425 * phy calibration commands
1426 */
1427 u8 phy_calib_chain_noise_reset_cmd;
1428 u8 phy_calib_chain_noise_gain_cmd;
1429
1430 struct il_notif_stats stats;
1431 #ifdef CONFIG_IWLEGACY_DEBUGFS
1432 struct il_notif_stats accum_stats;
1433 struct il_notif_stats delta_stats;
1434 struct il_notif_stats max_delta;
1435 #endif
1436
1437 } _4965;
1438 #endif
1439 };
1440
1441 struct il_hw_params hw_params;
1442
1443 u32 inta_mask;
1444
1445 struct workqueue_struct *workqueue;
1446
1447 struct work_struct restart;
1448 struct work_struct scan_completed;
1449 struct work_struct rx_replenish;
1450 struct work_struct abort_scan;
1451
1452 struct il_rxon_context *beacon_ctx;
1453 struct sk_buff *beacon_skb;
1454
1455 struct work_struct tx_flush;
1456
1457 struct tasklet_struct irq_tasklet;
1458
1459 struct delayed_work init_alive_start;
1460 struct delayed_work alive_start;
1461 struct delayed_work scan_check;
1462
1463 /* TX Power */
1464 s8 tx_power_user_lmt;
1465 s8 tx_power_device_lmt;
1466 s8 tx_power_next;
1467
1468 #ifdef CONFIG_IWLEGACY_DEBUG
1469 /* debugging info */
1470 u32 debug_level; /* per device debugging will override global
1471 il_debug_level if set */
1472 #endif /* CONFIG_IWLEGACY_DEBUG */
1473 #ifdef CONFIG_IWLEGACY_DEBUGFS
1474 /* debugfs */
1475 u16 tx_traffic_idx;
1476 u16 rx_traffic_idx;
1477 u8 *tx_traffic;
1478 u8 *rx_traffic;
1479 struct dentry *debugfs_dir;
1480 u32 dbgfs_sram_offset, dbgfs_sram_len;
1481 bool disable_ht40;
1482 #endif /* CONFIG_IWLEGACY_DEBUGFS */
1483
1484 struct work_struct txpower_work;
1485 u32 disable_sens_cal;
1486 u32 disable_chain_noise_cal;
1487 u32 disable_tx_power_cal;
1488 struct work_struct run_time_calib_work;
1489 struct timer_list stats_periodic;
1490 struct timer_list watchdog;
1491 bool hw_ready;
1492
1493 struct led_classdev led;
1494 unsigned long blink_on, blink_off;
1495 bool led_registered;
1496 }; /*il_priv */
1497
1498 static inline void
il_txq_ctx_activate(struct il_priv * il,int txq_id)1499 il_txq_ctx_activate(struct il_priv *il, int txq_id)
1500 {
1501 set_bit(txq_id, &il->txq_ctx_active_msk);
1502 }
1503
1504 static inline void
il_txq_ctx_deactivate(struct il_priv * il,int txq_id)1505 il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1506 {
1507 clear_bit(txq_id, &il->txq_ctx_active_msk);
1508 }
1509
1510 static inline struct ieee80211_hdr *
il_tx_queue_get_hdr(struct il_priv * il,int txq_id,int idx)1511 il_tx_queue_get_hdr(struct il_priv *il, int txq_id, int idx)
1512 {
1513 if (il->txq[txq_id].txb[idx].skb)
1514 return (struct ieee80211_hdr *)il->txq[txq_id].txb[idx].skb->
1515 data;
1516 return NULL;
1517 }
1518
1519 static inline struct il_rxon_context *
il_rxon_ctx_from_vif(struct ieee80211_vif * vif)1520 il_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1521 {
1522 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1523
1524 return vif_priv->ctx;
1525 }
1526
1527 #define for_each_context(il, _ctx) \
1528 for (_ctx = &il->ctx; _ctx == &il->ctx; _ctx++)
1529
1530 static inline int
il_is_associated(struct il_priv * il)1531 il_is_associated(struct il_priv *il)
1532 {
1533 return (il->ctx.active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1534 }
1535
1536 static inline int
il_is_any_associated(struct il_priv * il)1537 il_is_any_associated(struct il_priv *il)
1538 {
1539 return il_is_associated(il);
1540 }
1541
1542 static inline int
il_is_associated_ctx(struct il_rxon_context * ctx)1543 il_is_associated_ctx(struct il_rxon_context *ctx)
1544 {
1545 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1546 }
1547
1548 static inline int
il_is_channel_valid(const struct il_channel_info * ch_info)1549 il_is_channel_valid(const struct il_channel_info *ch_info)
1550 {
1551 if (ch_info == NULL)
1552 return 0;
1553 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1554 }
1555
1556 static inline int
il_is_channel_radar(const struct il_channel_info * ch_info)1557 il_is_channel_radar(const struct il_channel_info *ch_info)
1558 {
1559 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1560 }
1561
1562 static inline u8
il_is_channel_a_band(const struct il_channel_info * ch_info)1563 il_is_channel_a_band(const struct il_channel_info *ch_info)
1564 {
1565 return ch_info->band == IEEE80211_BAND_5GHZ;
1566 }
1567
1568 static inline int
il_is_channel_passive(const struct il_channel_info * ch)1569 il_is_channel_passive(const struct il_channel_info *ch)
1570 {
1571 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1572 }
1573
1574 static inline int
il_is_channel_ibss(const struct il_channel_info * ch)1575 il_is_channel_ibss(const struct il_channel_info *ch)
1576 {
1577 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1578 }
1579
1580 static inline void
__il_free_pages(struct il_priv * il,struct page * page)1581 __il_free_pages(struct il_priv *il, struct page *page)
1582 {
1583 __free_pages(page, il->hw_params.rx_page_order);
1584 il->alloc_rxb_page--;
1585 }
1586
1587 static inline void
il_free_pages(struct il_priv * il,unsigned long page)1588 il_free_pages(struct il_priv *il, unsigned long page)
1589 {
1590 free_pages(page, il->hw_params.rx_page_order);
1591 il->alloc_rxb_page--;
1592 }
1593
1594 #define IWLWIFI_VERSION "in-tree:"
1595 #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1596 #define DRV_AUTHOR "<ilw@linux.intel.com>"
1597
1598 #define IL_PCI_DEVICE(dev, subdev, cfg) \
1599 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1600 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1601 .driver_data = (kernel_ulong_t)&(cfg)
1602
1603 #define TIME_UNIT 1024
1604
1605 #define IL_SKU_G 0x1
1606 #define IL_SKU_A 0x2
1607 #define IL_SKU_N 0x8
1608
1609 #define IL_CMD(x) case x: return #x
1610
1611 /* Size of one Rx buffer in host DRAM */
1612 #define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
1613 #define IL_RX_BUF_SIZE_4K (4 * 1024)
1614 #define IL_RX_BUF_SIZE_8K (8 * 1024)
1615
1616 struct il_hcmd_ops {
1617 int (*rxon_assoc) (struct il_priv *il, struct il_rxon_context *ctx);
1618 int (*commit_rxon) (struct il_priv *il, struct il_rxon_context *ctx);
1619 void (*set_rxon_chain) (struct il_priv *il,
1620 struct il_rxon_context *ctx);
1621 };
1622
1623 struct il_hcmd_utils_ops {
1624 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1625 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1626 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1627 void (*post_scan) (struct il_priv *il);
1628 };
1629
1630 struct il_apm_ops {
1631 int (*init) (struct il_priv *il);
1632 void (*config) (struct il_priv *il);
1633 };
1634
1635 #ifdef CONFIG_IWLEGACY_DEBUGFS
1636 struct il_debugfs_ops {
1637 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1638 size_t count, loff_t *ppos);
1639 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1640 size_t count, loff_t *ppos);
1641 ssize_t(*general_stats_read) (struct file *file,
1642 char __user *user_buf, size_t count,
1643 loff_t *ppos);
1644 };
1645 #endif
1646
1647 struct il_temp_ops {
1648 void (*temperature) (struct il_priv *il);
1649 };
1650
1651 struct il_lib_ops {
1652 /* set hw dependent parameters */
1653 int (*set_hw_params) (struct il_priv *il);
1654 /* Handling TX */
1655 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1656 struct il_tx_queue *txq,
1657 u16 byte_cnt);
1658 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1659 struct il_tx_queue *txq, dma_addr_t addr,
1660 u16 len, u8 reset, u8 pad);
1661 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1662 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1663 /* setup Rx handler */
1664 void (*handler_setup) (struct il_priv *il);
1665 /* alive notification after init uCode load */
1666 void (*init_alive_start) (struct il_priv *il);
1667 /* check validity of rtc data address */
1668 int (*is_valid_rtc_data_addr) (u32 addr);
1669 /* 1st ucode load */
1670 int (*load_ucode) (struct il_priv *il);
1671
1672 void (*dump_nic_error_log) (struct il_priv *il);
1673 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1674 int (*set_channel_switch) (struct il_priv *il,
1675 struct ieee80211_channel_switch *ch_switch);
1676 /* power management */
1677 struct il_apm_ops apm_ops;
1678
1679 /* power */
1680 int (*send_tx_power) (struct il_priv *il);
1681 void (*update_chain_flags) (struct il_priv *il);
1682
1683 /* eeprom operations */
1684 struct il_eeprom_ops eeprom_ops;
1685
1686 /* temperature */
1687 struct il_temp_ops temp_ops;
1688
1689 #ifdef CONFIG_IWLEGACY_DEBUGFS
1690 struct il_debugfs_ops debugfs_ops;
1691 #endif
1692
1693 };
1694
1695 struct il_led_ops {
1696 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1697 };
1698
1699 struct il_legacy_ops {
1700 void (*post_associate) (struct il_priv *il);
1701 void (*config_ap) (struct il_priv *il);
1702 /* station management */
1703 int (*update_bcast_stations) (struct il_priv *il);
1704 int (*manage_ibss_station) (struct il_priv *il,
1705 struct ieee80211_vif *vif, bool add);
1706 };
1707
1708 struct il_ops {
1709 const struct il_lib_ops *lib;
1710 const struct il_hcmd_ops *hcmd;
1711 const struct il_hcmd_utils_ops *utils;
1712 const struct il_led_ops *led;
1713 const struct il_nic_ops *nic;
1714 const struct il_legacy_ops *legacy;
1715 const struct ieee80211_ops *ieee80211_ops;
1716 };
1717
1718 struct il_mod_params {
1719 int sw_crypto; /* def: 0 = using hardware encryption */
1720 int disable_hw_scan; /* def: 0 = use h/w scan */
1721 int num_of_queues; /* def: HW dependent */
1722 int disable_11n; /* def: 0 = 11n capabilities enabled */
1723 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
1724 int antenna; /* def: 0 = both antennas (use diversity) */
1725 int restart_fw; /* def: 1 = restart firmware */
1726 };
1727
1728 /*
1729 * @led_compensation: compensate on the led on/off time per HW according
1730 * to the deviation to achieve the desired led frequency.
1731 * The detail algorithm is described in common.c
1732 * @chain_noise_num_beacons: number of beacons used to compute chain noise
1733 * @wd_timeout: TX queues watchdog timeout
1734 * @temperature_kelvin: temperature report by uCode in kelvin
1735 * @ucode_tracing: support ucode continuous tracing
1736 * @sensitivity_calib_by_driver: driver has the capability to perform
1737 * sensitivity calibration operation
1738 * @chain_noise_calib_by_driver: driver has the capability to perform
1739 * chain noise calibration operation
1740 */
1741 struct il_base_params {
1742 int eeprom_size;
1743 int num_of_queues; /* def: HW dependent */
1744 int num_of_ampdu_queues; /* def: HW dependent */
1745 /* for il_apm_init() */
1746 u32 pll_cfg_val;
1747 bool set_l0s;
1748 bool use_bsm;
1749
1750 u16 led_compensation;
1751 int chain_noise_num_beacons;
1752 unsigned int wd_timeout;
1753 bool temperature_kelvin;
1754 const bool ucode_tracing;
1755 const bool sensitivity_calib_by_driver;
1756 const bool chain_noise_calib_by_driver;
1757 };
1758
1759 #define IL_LED_SOLID 11
1760 #define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1761
1762 #define IL_LED_ACTIVITY (0<<1)
1763 #define IL_LED_LINK (1<<1)
1764
1765 /*
1766 * LED mode
1767 * IL_LED_DEFAULT: use device default
1768 * IL_LED_RF_STATE: turn LED on/off based on RF state
1769 * LED ON = RF ON
1770 * LED OFF = RF OFF
1771 * IL_LED_BLINK: adjust led blink rate based on blink table
1772 */
1773 enum il_led_mode {
1774 IL_LED_DEFAULT,
1775 IL_LED_RF_STATE,
1776 IL_LED_BLINK,
1777 };
1778
1779 void il_leds_init(struct il_priv *il);
1780 void il_leds_exit(struct il_priv *il);
1781
1782 /**
1783 * struct il_cfg
1784 * @fw_name_pre: Firmware filename prefix. The api version and extension
1785 * (.ucode) will be added to filename before loading from disk. The
1786 * filename is constructed as fw_name_pre<api>.ucode.
1787 * @ucode_api_max: Highest version of uCode API supported by driver.
1788 * @ucode_api_min: Lowest version of uCode API supported by driver.
1789 * @scan_antennas: available antenna for scan operation
1790 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1791 *
1792 * We enable the driver to be backward compatible wrt API version. The
1793 * driver specifies which APIs it supports (with @ucode_api_max being the
1794 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1795 * it has a supported API version. The firmware's API version will be
1796 * stored in @il_priv, enabling the driver to make runtime changes based
1797 * on firmware version used.
1798 *
1799 * For example,
1800 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
1801 * Driver interacts with Firmware API version >= 2.
1802 * } else {
1803 * Driver interacts with Firmware API version 1.
1804 * }
1805 *
1806 * The ideal usage of this infrastructure is to treat a new ucode API
1807 * release as a new hardware revision. That is, through utilizing the
1808 * il_hcmd_utils_ops etc. we accommodate different command structures
1809 * and flows between hardware versions as well as their API
1810 * versions.
1811 *
1812 */
1813 struct il_cfg {
1814 /* params specific to an individual device within a device family */
1815 const char *name;
1816 const char *fw_name_pre;
1817 const unsigned int ucode_api_max;
1818 const unsigned int ucode_api_min;
1819 u8 valid_tx_ant;
1820 u8 valid_rx_ant;
1821 unsigned int sku;
1822 u16 eeprom_ver;
1823 u16 eeprom_calib_ver;
1824 const struct il_ops *ops;
1825 /* module based parameters which can be set from modprobe cmd */
1826 const struct il_mod_params *mod_params;
1827 /* params not likely to change within a device family */
1828 struct il_base_params *base_params;
1829 /* params likely to change within a device family */
1830 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
1831 enum il_led_mode led_mode;
1832 };
1833
1834 /***************************
1835 * L i b *
1836 ***************************/
1837
1838 struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg);
1839 int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1840 u16 queue, const struct ieee80211_tx_queue_params *params);
1841 int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1842
1843 void il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
1844 int hw_decrypt);
1845 int il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx);
1846 int il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx);
1847 int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
1848 struct il_rxon_context *ctx);
1849 void il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
1850 enum ieee80211_band band, struct ieee80211_vif *vif);
1851 u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1852 void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1853 bool il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
1854 struct ieee80211_sta_ht_cap *ht_cap);
1855 void il_connection_init_rx_config(struct il_priv *il,
1856 struct il_rxon_context *ctx);
1857 void il_set_rate(struct il_priv *il);
1858 int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1859 u32 decrypt_res, struct ieee80211_rx_status *stats);
1860 void il_irq_handle_error(struct il_priv *il);
1861 int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1862 void il_mac_remove_interface(struct ieee80211_hw *hw,
1863 struct ieee80211_vif *vif);
1864 int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1865 enum nl80211_iftype newtype, bool newp2p);
1866 int il_alloc_txq_mem(struct il_priv *il);
1867 void il_txq_mem(struct il_priv *il);
1868
1869 #ifdef CONFIG_IWLEGACY_DEBUGFS
1870 int il_alloc_traffic_mem(struct il_priv *il);
1871 void il_free_traffic_mem(struct il_priv *il);
1872 void il_reset_traffic_log(struct il_priv *il);
1873 void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1874 struct ieee80211_hdr *header);
1875 void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1876 struct ieee80211_hdr *header);
1877 const char *il_get_mgmt_string(int cmd);
1878 const char *il_get_ctrl_string(int cmd);
1879 void il_clear_traffic_stats(struct il_priv *il);
1880 void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1881 #else
1882 static inline int
il_alloc_traffic_mem(struct il_priv * il)1883 il_alloc_traffic_mem(struct il_priv *il)
1884 {
1885 return 0;
1886 }
1887
1888 static inline void
il_free_traffic_mem(struct il_priv * il)1889 il_free_traffic_mem(struct il_priv *il)
1890 {
1891 }
1892
1893 static inline void
il_reset_traffic_log(struct il_priv * il)1894 il_reset_traffic_log(struct il_priv *il)
1895 {
1896 }
1897
1898 static inline void
il_dbg_log_tx_data_frame(struct il_priv * il,u16 length,struct ieee80211_hdr * header)1899 il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1900 struct ieee80211_hdr *header)
1901 {
1902 }
1903
1904 static inline void
il_dbg_log_rx_data_frame(struct il_priv * il,u16 length,struct ieee80211_hdr * header)1905 il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1906 struct ieee80211_hdr *header)
1907 {
1908 }
1909
1910 static inline void
il_update_stats(struct il_priv * il,bool is_tx,__le16 fc,u16 len)1911 il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1912 {
1913 }
1914 #endif
1915 /*****************************************************
1916 * RX handlers.
1917 * **************************************************/
1918 void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1919 void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1920 void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1921
1922 /*****************************************************
1923 * RX
1924 ******************************************************/
1925 void il_cmd_queue_unmap(struct il_priv *il);
1926 void il_cmd_queue_free(struct il_priv *il);
1927 int il_rx_queue_alloc(struct il_priv *il);
1928 void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1929 int il_rx_queue_space(const struct il_rx_queue *q);
1930 void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1931 /* Handlers */
1932 void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1933 void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1934 void il_chswitch_done(struct il_priv *il, bool is_success);
1935 void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1936
1937 /* TX helpers */
1938
1939 /*****************************************************
1940 * TX
1941 ******************************************************/
1942 void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1943 int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1944 u32 txq_id);
1945 void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1946 int slots_num, u32 txq_id);
1947 void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1948 void il_tx_queue_free(struct il_priv *il, int txq_id);
1949 void il_setup_watchdog(struct il_priv *il);
1950 /*****************************************************
1951 * TX power
1952 ****************************************************/
1953 int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1954
1955 /*******************************************************************************
1956 * Rate
1957 ******************************************************************************/
1958
1959 u8 il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx);
1960
1961 /*******************************************************************************
1962 * Scanning
1963 ******************************************************************************/
1964 void il_init_scan_params(struct il_priv *il);
1965 int il_scan_cancel(struct il_priv *il);
1966 int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1967 void il_force_scan_end(struct il_priv *il);
1968 int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1969 struct cfg80211_scan_request *req);
1970 void il_internal_short_hw_scan(struct il_priv *il);
1971 int il_force_reset(struct il_priv *il, bool external);
1972 u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1973 const u8 *ta, const u8 *ie, int ie_len, int left);
1974 void il_setup_rx_scan_handlers(struct il_priv *il);
1975 u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1976 u8 n_probes);
1977 u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1978 struct ieee80211_vif *vif);
1979 void il_setup_scan_deferred_work(struct il_priv *il);
1980 void il_cancel_scan_deferred_work(struct il_priv *il);
1981
1982 /* For faster active scanning, scan will move to the next channel if fewer than
1983 * PLCP_QUIET_THRESH packets are heard on this channel within
1984 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1985 * time if it's a quiet channel (nothing responded to our probe, and there's
1986 * no other traffic).
1987 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
1988 #define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1989 #define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
1990
1991 #define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1992
1993 /*****************************************************
1994 * S e n d i n g H o s t C o m m a n d s *
1995 *****************************************************/
1996
1997 const char *il_get_cmd_string(u8 cmd);
1998 int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1999 int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
2000 int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
2001 const void *data);
2002 int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
2003 void (*callback) (struct il_priv *il,
2004 struct il_device_cmd *cmd,
2005 struct il_rx_pkt *pkt));
2006
2007 int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
2008
2009 /*****************************************************
2010 * PCI *
2011 *****************************************************/
2012
2013 static inline u16
il_pcie_link_ctl(struct il_priv * il)2014 il_pcie_link_ctl(struct il_priv *il)
2015 {
2016 int pos;
2017 u16 pci_lnk_ctl;
2018 pos = pci_pcie_cap(il->pci_dev);
2019 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
2020 return pci_lnk_ctl;
2021 }
2022
2023 void il_bg_watchdog(unsigned long data);
2024 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
2025 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
2026 u32 beacon_interval);
2027
2028 #ifdef CONFIG_PM
2029 int il_pci_suspend(struct device *device);
2030 int il_pci_resume(struct device *device);
2031 extern const struct dev_pm_ops il_pm_ops;
2032
2033 #define IL_LEGACY_PM_OPS (&il_pm_ops)
2034
2035 #else /* !CONFIG_PM */
2036
2037 #define IL_LEGACY_PM_OPS NULL
2038
2039 #endif /* !CONFIG_PM */
2040
2041 /*****************************************************
2042 * Error Handling Debugging
2043 ******************************************************/
2044 void il4965_dump_nic_error_log(struct il_priv *il);
2045 #ifdef CONFIG_IWLEGACY_DEBUG
2046 void il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx);
2047 #else
2048 static inline void
il_print_rx_config_cmd(struct il_priv * il,struct il_rxon_context * ctx)2049 il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
2050 {
2051 }
2052 #endif
2053
2054 void il_clear_isr_stats(struct il_priv *il);
2055
2056 /*****************************************************
2057 * GEOS
2058 ******************************************************/
2059 int il_init_geos(struct il_priv *il);
2060 void il_free_geos(struct il_priv *il);
2061
2062 /*************** DRIVER STATUS FUNCTIONS *****/
2063
2064 #define S_HCMD_ACTIVE 0 /* host command in progress */
2065 /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
2066 #define S_INT_ENABLED 2
2067 #define S_RF_KILL_HW 3
2068 #define S_CT_KILL 4
2069 #define S_INIT 5
2070 #define S_ALIVE 6
2071 #define S_READY 7
2072 #define S_TEMPERATURE 8
2073 #define S_GEO_CONFIGURED 9
2074 #define S_EXIT_PENDING 10
2075 #define S_STATS 12
2076 #define S_SCANNING 13
2077 #define S_SCAN_ABORTING 14
2078 #define S_SCAN_HW 15
2079 #define S_POWER_PMI 16
2080 #define S_FW_ERROR 17
2081 #define S_CHANNEL_SWITCH_PENDING 18
2082
2083 static inline int
il_is_ready(struct il_priv * il)2084 il_is_ready(struct il_priv *il)
2085 {
2086 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2087 * set but EXIT_PENDING is not */
2088 return test_bit(S_READY, &il->status) &&
2089 test_bit(S_GEO_CONFIGURED, &il->status) &&
2090 !test_bit(S_EXIT_PENDING, &il->status);
2091 }
2092
2093 static inline int
il_is_alive(struct il_priv * il)2094 il_is_alive(struct il_priv *il)
2095 {
2096 return test_bit(S_ALIVE, &il->status);
2097 }
2098
2099 static inline int
il_is_init(struct il_priv * il)2100 il_is_init(struct il_priv *il)
2101 {
2102 return test_bit(S_INIT, &il->status);
2103 }
2104
2105 static inline int
il_is_rfkill_hw(struct il_priv * il)2106 il_is_rfkill_hw(struct il_priv *il)
2107 {
2108 return test_bit(S_RF_KILL_HW, &il->status);
2109 }
2110
2111 static inline int
il_is_rfkill(struct il_priv * il)2112 il_is_rfkill(struct il_priv *il)
2113 {
2114 return il_is_rfkill_hw(il);
2115 }
2116
2117 static inline int
il_is_ctkill(struct il_priv * il)2118 il_is_ctkill(struct il_priv *il)
2119 {
2120 return test_bit(S_CT_KILL, &il->status);
2121 }
2122
2123 static inline int
il_is_ready_rf(struct il_priv * il)2124 il_is_ready_rf(struct il_priv *il)
2125 {
2126
2127 if (il_is_rfkill(il))
2128 return 0;
2129
2130 return il_is_ready(il);
2131 }
2132
2133 extern void il_send_bt_config(struct il_priv *il);
2134 extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
2135 void il_apm_stop(struct il_priv *il);
2136 int il_apm_init(struct il_priv *il);
2137
2138 int il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx);
2139 static inline int
il_send_rxon_assoc(struct il_priv * il,struct il_rxon_context * ctx)2140 il_send_rxon_assoc(struct il_priv *il, struct il_rxon_context *ctx)
2141 {
2142 return il->cfg->ops->hcmd->rxon_assoc(il, ctx);
2143 }
2144
2145 static inline int
il_commit_rxon(struct il_priv * il,struct il_rxon_context * ctx)2146 il_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
2147 {
2148 return il->cfg->ops->hcmd->commit_rxon(il, ctx);
2149 }
2150
2151 static inline const struct ieee80211_supported_band *
il_get_hw_mode(struct il_priv * il,enum ieee80211_band band)2152 il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
2153 {
2154 return il->hw->wiphy->bands[band];
2155 }
2156
2157 /* mac80211 handlers */
2158 int il_mac_config(struct ieee80211_hw *hw, u32 changed);
2159 void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2160 void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2161 struct ieee80211_bss_conf *bss_conf, u32 changes);
2162 void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
2163 __le16 fc, __le32 *tx_flags);
2164
2165 irqreturn_t il_isr(int irq, void *data);
2166
2167 extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
2168 extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
2169 extern int _il_grab_nic_access(struct il_priv *il);
2170 extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
2171 extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
2172 extern u32 il_rd_prph(struct il_priv *il, u32 reg);
2173 extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
2174 extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
2175 extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
2176
2177 static inline void
_il_write8(struct il_priv * il,u32 ofs,u8 val)2178 _il_write8(struct il_priv *il, u32 ofs, u8 val)
2179 {
2180 iowrite8(val, il->hw_base + ofs);
2181 }
2182 #define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2183
2184 static inline void
_il_wr(struct il_priv * il,u32 ofs,u32 val)2185 _il_wr(struct il_priv *il, u32 ofs, u32 val)
2186 {
2187 iowrite32(val, il->hw_base + ofs);
2188 }
2189
2190 static inline u32
_il_rd(struct il_priv * il,u32 ofs)2191 _il_rd(struct il_priv *il, u32 ofs)
2192 {
2193 return ioread32(il->hw_base + ofs);
2194 }
2195
2196 static inline void
_il_clear_bit(struct il_priv * il,u32 reg,u32 mask)2197 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2198 {
2199 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2200 }
2201
2202 static inline void
_il_set_bit(struct il_priv * il,u32 reg,u32 mask)2203 _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2204 {
2205 _il_wr(il, reg, _il_rd(il, reg) | mask);
2206 }
2207
2208 static inline void
_il_release_nic_access(struct il_priv * il)2209 _il_release_nic_access(struct il_priv *il)
2210 {
2211 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2212 }
2213
2214 static inline u32
il_rd(struct il_priv * il,u32 reg)2215 il_rd(struct il_priv *il, u32 reg)
2216 {
2217 u32 value;
2218 unsigned long reg_flags;
2219
2220 spin_lock_irqsave(&il->reg_lock, reg_flags);
2221 _il_grab_nic_access(il);
2222 value = _il_rd(il, reg);
2223 _il_release_nic_access(il);
2224 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2225 return value;
2226 }
2227
2228 static inline void
il_wr(struct il_priv * il,u32 reg,u32 value)2229 il_wr(struct il_priv *il, u32 reg, u32 value)
2230 {
2231 unsigned long reg_flags;
2232
2233 spin_lock_irqsave(&il->reg_lock, reg_flags);
2234 if (!_il_grab_nic_access(il)) {
2235 _il_wr(il, reg, value);
2236 _il_release_nic_access(il);
2237 }
2238 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2239 }
2240
2241 static inline u32
_il_rd_prph(struct il_priv * il,u32 reg)2242 _il_rd_prph(struct il_priv *il, u32 reg)
2243 {
2244 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2245 rmb();
2246 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2247 }
2248
2249 static inline void
_il_wr_prph(struct il_priv * il,u32 addr,u32 val)2250 _il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2251 {
2252 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2253 wmb();
2254 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2255 }
2256
2257 static inline void
il_set_bits_prph(struct il_priv * il,u32 reg,u32 mask)2258 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2259 {
2260 unsigned long reg_flags;
2261
2262 spin_lock_irqsave(&il->reg_lock, reg_flags);
2263 _il_grab_nic_access(il);
2264 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2265 _il_release_nic_access(il);
2266 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2267 }
2268
2269 static inline void
il_set_bits_mask_prph(struct il_priv * il,u32 reg,u32 bits,u32 mask)2270 il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2271 {
2272 unsigned long reg_flags;
2273
2274 spin_lock_irqsave(&il->reg_lock, reg_flags);
2275 _il_grab_nic_access(il);
2276 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2277 _il_release_nic_access(il);
2278 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2279 }
2280
2281 static inline void
il_clear_bits_prph(struct il_priv * il,u32 reg,u32 mask)2282 il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2283 {
2284 unsigned long reg_flags;
2285 u32 val;
2286
2287 spin_lock_irqsave(&il->reg_lock, reg_flags);
2288 _il_grab_nic_access(il);
2289 val = _il_rd_prph(il, reg);
2290 _il_wr_prph(il, reg, (val & ~mask));
2291 _il_release_nic_access(il);
2292 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2293 }
2294
2295 #define HW_KEY_DYNAMIC 0
2296 #define HW_KEY_DEFAULT 1
2297
2298 #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2299 #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2300 #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2301 being activated */
2302 #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2303 (this is for the IBSS BSSID stations) */
2304 #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
2305
2306 void il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx);
2307 void il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx);
2308 void il_dealloc_bcast_stations(struct il_priv *il);
2309 int il_get_free_ucode_key_idx(struct il_priv *il);
2310 int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2311 int il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
2312 const u8 *addr, bool is_ap,
2313 struct ieee80211_sta *sta, u8 *sta_id_r);
2314 int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2315 int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2316 struct ieee80211_sta *sta);
2317
2318 u8 il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
2319 const u8 *addr, bool is_ap, struct ieee80211_sta *sta);
2320
2321 int il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2322 struct il_link_quality_cmd *lq, u8 flags, bool init);
2323
2324 /**
2325 * il_clear_driver_stations - clear knowledge of all stations from driver
2326 * @il: iwl il struct
2327 *
2328 * This is called during il_down() to make sure that in the case
2329 * we're coming there from a hardware restart mac80211 will be
2330 * able to reconfigure stations -- if we're getting there in the
2331 * normal down flow then the stations will already be cleared.
2332 */
2333 static inline void
il_clear_driver_stations(struct il_priv * il)2334 il_clear_driver_stations(struct il_priv *il)
2335 {
2336 unsigned long flags;
2337 struct il_rxon_context *ctx = &il->ctx;
2338
2339 spin_lock_irqsave(&il->sta_lock, flags);
2340 memset(il->stations, 0, sizeof(il->stations));
2341 il->num_stations = 0;
2342
2343 il->ucode_key_table = 0;
2344
2345 /*
2346 * Remove all key information that is not stored as part
2347 * of station information since mac80211 may not have had
2348 * a chance to remove all the keys. When device is
2349 * reconfigured by mac80211 after an error all keys will
2350 * be reconfigured.
2351 */
2352 memset(ctx->wep_keys, 0, sizeof(ctx->wep_keys));
2353 ctx->key_mapping_keys = 0;
2354
2355 spin_unlock_irqrestore(&il->sta_lock, flags);
2356 }
2357
2358 static inline int
il_sta_id(struct ieee80211_sta * sta)2359 il_sta_id(struct ieee80211_sta *sta)
2360 {
2361 if (WARN_ON(!sta))
2362 return IL_INVALID_STATION;
2363
2364 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2365 }
2366
2367 /**
2368 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2369 * @il: iwl il
2370 * @context: the current context
2371 * @sta: mac80211 station
2372 *
2373 * In certain circumstances mac80211 passes a station pointer
2374 * that may be %NULL, for example during TX or key setup. In
2375 * that case, we need to use the broadcast station, so this
2376 * inline wraps that pattern.
2377 */
2378 static inline int
il_sta_id_or_broadcast(struct il_priv * il,struct il_rxon_context * context,struct ieee80211_sta * sta)2379 il_sta_id_or_broadcast(struct il_priv *il, struct il_rxon_context *context,
2380 struct ieee80211_sta *sta)
2381 {
2382 int sta_id;
2383
2384 if (!sta)
2385 return context->bcast_sta_id;
2386
2387 sta_id = il_sta_id(sta);
2388
2389 /*
2390 * mac80211 should not be passing a partially
2391 * initialised station!
2392 */
2393 WARN_ON(sta_id == IL_INVALID_STATION);
2394
2395 return sta_id;
2396 }
2397
2398 /**
2399 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2400 * @idx -- current idx
2401 * @n_bd -- total number of entries in queue (must be power of 2)
2402 */
2403 static inline int
il_queue_inc_wrap(int idx,int n_bd)2404 il_queue_inc_wrap(int idx, int n_bd)
2405 {
2406 return ++idx & (n_bd - 1);
2407 }
2408
2409 /**
2410 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2411 * @idx -- current idx
2412 * @n_bd -- total number of entries in queue (must be power of 2)
2413 */
2414 static inline int
il_queue_dec_wrap(int idx,int n_bd)2415 il_queue_dec_wrap(int idx, int n_bd)
2416 {
2417 return --idx & (n_bd - 1);
2418 }
2419
2420 /* TODO: Move fw_desc functions to iwl-pci.ko */
2421 static inline void
il_free_fw_desc(struct pci_dev * pci_dev,struct fw_desc * desc)2422 il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2423 {
2424 if (desc->v_addr)
2425 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2426 desc->p_addr);
2427 desc->v_addr = NULL;
2428 desc->len = 0;
2429 }
2430
2431 static inline int
il_alloc_fw_desc(struct pci_dev * pci_dev,struct fw_desc * desc)2432 il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2433 {
2434 if (!desc->len) {
2435 desc->v_addr = NULL;
2436 return -EINVAL;
2437 }
2438
2439 desc->v_addr =
2440 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2441 GFP_KERNEL);
2442 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2443 }
2444
2445 /*
2446 * we have 8 bits used like this:
2447 *
2448 * 7 6 5 4 3 2 1 0
2449 * | | | | | | | |
2450 * | | | | | | +-+-------- AC queue (0-3)
2451 * | | | | | |
2452 * | +-+-+-+-+------------ HW queue ID
2453 * |
2454 * +---------------------- unused
2455 */
2456 static inline void
il_set_swq_id(struct il_tx_queue * txq,u8 ac,u8 hwq)2457 il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2458 {
2459 BUG_ON(ac > 3); /* only have 2 bits */
2460 BUG_ON(hwq > 31); /* only use 5 bits */
2461
2462 txq->swq_id = (hwq << 2) | ac;
2463 }
2464
2465 static inline void
il_wake_queue(struct il_priv * il,struct il_tx_queue * txq)2466 il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2467 {
2468 u8 queue = txq->swq_id;
2469 u8 ac = queue & 3;
2470 u8 hwq = (queue >> 2) & 0x1f;
2471
2472 if (test_and_clear_bit(hwq, il->queue_stopped))
2473 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2474 ieee80211_wake_queue(il->hw, ac);
2475 }
2476
2477 static inline void
il_stop_queue(struct il_priv * il,struct il_tx_queue * txq)2478 il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2479 {
2480 u8 queue = txq->swq_id;
2481 u8 ac = queue & 3;
2482 u8 hwq = (queue >> 2) & 0x1f;
2483
2484 if (!test_and_set_bit(hwq, il->queue_stopped))
2485 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2486 ieee80211_stop_queue(il->hw, ac);
2487 }
2488
2489 #ifdef ieee80211_stop_queue
2490 #undef ieee80211_stop_queue
2491 #endif
2492
2493 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2494
2495 #ifdef ieee80211_wake_queue
2496 #undef ieee80211_wake_queue
2497 #endif
2498
2499 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2500
2501 static inline void
il_disable_interrupts(struct il_priv * il)2502 il_disable_interrupts(struct il_priv *il)
2503 {
2504 clear_bit(S_INT_ENABLED, &il->status);
2505
2506 /* disable interrupts from uCode/NIC to host */
2507 _il_wr(il, CSR_INT_MASK, 0x00000000);
2508
2509 /* acknowledge/clear/reset any interrupts still pending
2510 * from uCode or flow handler (Rx/Tx DMA) */
2511 _il_wr(il, CSR_INT, 0xffffffff);
2512 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2513 }
2514
2515 static inline void
il_enable_rfkill_int(struct il_priv * il)2516 il_enable_rfkill_int(struct il_priv *il)
2517 {
2518 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2519 }
2520
2521 static inline void
il_enable_interrupts(struct il_priv * il)2522 il_enable_interrupts(struct il_priv *il)
2523 {
2524 set_bit(S_INT_ENABLED, &il->status);
2525 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2526 }
2527
2528 /**
2529 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2530 * @il -- pointer to il_priv data structure
2531 * @tsf_bits -- number of bits need to shift for masking)
2532 */
2533 static inline u32
il_beacon_time_mask_low(struct il_priv * il,u16 tsf_bits)2534 il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2535 {
2536 return (1 << tsf_bits) - 1;
2537 }
2538
2539 /**
2540 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2541 * @il -- pointer to il_priv data structure
2542 * @tsf_bits -- number of bits need to shift for masking)
2543 */
2544 static inline u32
il_beacon_time_mask_high(struct il_priv * il,u16 tsf_bits)2545 il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2546 {
2547 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2548 }
2549
2550 /**
2551 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2552 *
2553 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2554 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2555 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2556 * in which the last frame was written to
2557 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2558 * which was transferred
2559 */
2560 struct il_rb_status {
2561 __le16 closed_rb_num;
2562 __le16 closed_fr_num;
2563 __le16 finished_rb_num;
2564 __le16 finished_fr_nam;
2565 __le32 __unused; /* 3945 only */
2566 } __packed;
2567
2568 #define TFD_QUEUE_SIZE_MAX (256)
2569 #define TFD_QUEUE_SIZE_BC_DUP (64)
2570 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2571 #define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2572 #define IL_NUM_OF_TBS 20
2573
2574 static inline u8
il_get_dma_hi_addr(dma_addr_t addr)2575 il_get_dma_hi_addr(dma_addr_t addr)
2576 {
2577 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2578 }
2579
2580 /**
2581 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2582 *
2583 * This structure contains dma address and length of transmission address
2584 *
2585 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2586 * unaligned on 16 bit boundary
2587 * @hi_n_len: 0-3 [35:32] portion of dma
2588 * 4-15 length of the tx buffer
2589 */
2590 struct il_tfd_tb {
2591 __le32 lo;
2592 __le16 hi_n_len;
2593 } __packed;
2594
2595 /**
2596 * struct il_tfd
2597 *
2598 * Transmit Frame Descriptor (TFD)
2599 *
2600 * @ __reserved1[3] reserved
2601 * @ num_tbs 0-4 number of active tbs
2602 * 5 reserved
2603 * 6-7 padding (not used)
2604 * @ tbs[20] transmit frame buffer descriptors
2605 * @ __pad padding
2606 *
2607 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2608 * Both driver and device share these circular buffers, each of which must be
2609 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2610 *
2611 * Driver must indicate the physical address of the base of each
2612 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
2613 *
2614 * Each TFD contains pointer/size information for up to 20 data buffers
2615 * in host DRAM. These buffers collectively contain the (one) frame described
2616 * by the TFD. Each buffer must be a single contiguous block of memory within
2617 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2618 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2619 * Tx frame, up to 8 KBytes in size.
2620 *
2621 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2622 */
2623 struct il_tfd {
2624 u8 __reserved1[3];
2625 u8 num_tbs;
2626 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2627 __le32 __pad;
2628 } __packed;
2629 /* PCI registers */
2630 #define PCI_CFG_RETRY_TIMEOUT 0x041
2631
2632 /* PCI register values */
2633 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2634 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2635
2636 struct il_rate_info {
2637 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2638 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2639 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2640 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2641 u8 prev_ieee; /* previous rate in IEEE speeds */
2642 u8 next_ieee; /* next rate in IEEE speeds */
2643 u8 prev_rs; /* previous rate used in rs algo */
2644 u8 next_rs; /* next rate used in rs algo */
2645 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2646 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2647 };
2648
2649 struct il3945_rate_info {
2650 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2651 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2652 u8 prev_ieee; /* previous rate in IEEE speeds */
2653 u8 next_ieee; /* next rate in IEEE speeds */
2654 u8 prev_rs; /* previous rate used in rs algo */
2655 u8 next_rs; /* next rate used in rs algo */
2656 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2657 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2658 u8 table_rs_idx; /* idx in rate scale table cmd */
2659 u8 prev_table_rs; /* prev in rate table cmd */
2660 };
2661
2662 /*
2663 * These serve as idxes into
2664 * struct il_rate_info il_rates[RATE_COUNT];
2665 */
2666 enum {
2667 RATE_1M_IDX = 0,
2668 RATE_2M_IDX,
2669 RATE_5M_IDX,
2670 RATE_11M_IDX,
2671 RATE_6M_IDX,
2672 RATE_9M_IDX,
2673 RATE_12M_IDX,
2674 RATE_18M_IDX,
2675 RATE_24M_IDX,
2676 RATE_36M_IDX,
2677 RATE_48M_IDX,
2678 RATE_54M_IDX,
2679 RATE_60M_IDX,
2680 RATE_COUNT,
2681 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2682 RATE_COUNT_3945 = RATE_COUNT - 1,
2683 RATE_INVM_IDX = RATE_COUNT,
2684 RATE_INVALID = RATE_COUNT,
2685 };
2686
2687 enum {
2688 RATE_6M_IDX_TBL = 0,
2689 RATE_9M_IDX_TBL,
2690 RATE_12M_IDX_TBL,
2691 RATE_18M_IDX_TBL,
2692 RATE_24M_IDX_TBL,
2693 RATE_36M_IDX_TBL,
2694 RATE_48M_IDX_TBL,
2695 RATE_54M_IDX_TBL,
2696 RATE_1M_IDX_TBL,
2697 RATE_2M_IDX_TBL,
2698 RATE_5M_IDX_TBL,
2699 RATE_11M_IDX_TBL,
2700 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2701 };
2702
2703 enum {
2704 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2705 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2706 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2707 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2708 IL_LAST_CCK_RATE = RATE_11M_IDX,
2709 };
2710
2711 /* #define vs. enum to keep from defaulting to 'large integer' */
2712 #define RATE_6M_MASK (1 << RATE_6M_IDX)
2713 #define RATE_9M_MASK (1 << RATE_9M_IDX)
2714 #define RATE_12M_MASK (1 << RATE_12M_IDX)
2715 #define RATE_18M_MASK (1 << RATE_18M_IDX)
2716 #define RATE_24M_MASK (1 << RATE_24M_IDX)
2717 #define RATE_36M_MASK (1 << RATE_36M_IDX)
2718 #define RATE_48M_MASK (1 << RATE_48M_IDX)
2719 #define RATE_54M_MASK (1 << RATE_54M_IDX)
2720 #define RATE_60M_MASK (1 << RATE_60M_IDX)
2721 #define RATE_1M_MASK (1 << RATE_1M_IDX)
2722 #define RATE_2M_MASK (1 << RATE_2M_IDX)
2723 #define RATE_5M_MASK (1 << RATE_5M_IDX)
2724 #define RATE_11M_MASK (1 << RATE_11M_IDX)
2725
2726 /* uCode API values for legacy bit rates, both OFDM and CCK */
2727 enum {
2728 RATE_6M_PLCP = 13,
2729 RATE_9M_PLCP = 15,
2730 RATE_12M_PLCP = 5,
2731 RATE_18M_PLCP = 7,
2732 RATE_24M_PLCP = 9,
2733 RATE_36M_PLCP = 11,
2734 RATE_48M_PLCP = 1,
2735 RATE_54M_PLCP = 3,
2736 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2737 RATE_1M_PLCP = 10,
2738 RATE_2M_PLCP = 20,
2739 RATE_5M_PLCP = 55,
2740 RATE_11M_PLCP = 110,
2741 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
2742 };
2743
2744 /* uCode API values for OFDM high-throughput (HT) bit rates */
2745 enum {
2746 RATE_SISO_6M_PLCP = 0,
2747 RATE_SISO_12M_PLCP = 1,
2748 RATE_SISO_18M_PLCP = 2,
2749 RATE_SISO_24M_PLCP = 3,
2750 RATE_SISO_36M_PLCP = 4,
2751 RATE_SISO_48M_PLCP = 5,
2752 RATE_SISO_54M_PLCP = 6,
2753 RATE_SISO_60M_PLCP = 7,
2754 RATE_MIMO2_6M_PLCP = 0x8,
2755 RATE_MIMO2_12M_PLCP = 0x9,
2756 RATE_MIMO2_18M_PLCP = 0xa,
2757 RATE_MIMO2_24M_PLCP = 0xb,
2758 RATE_MIMO2_36M_PLCP = 0xc,
2759 RATE_MIMO2_48M_PLCP = 0xd,
2760 RATE_MIMO2_54M_PLCP = 0xe,
2761 RATE_MIMO2_60M_PLCP = 0xf,
2762 RATE_SISO_INVM_PLCP,
2763 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2764 };
2765
2766 /* MAC header values for bit rates */
2767 enum {
2768 RATE_6M_IEEE = 12,
2769 RATE_9M_IEEE = 18,
2770 RATE_12M_IEEE = 24,
2771 RATE_18M_IEEE = 36,
2772 RATE_24M_IEEE = 48,
2773 RATE_36M_IEEE = 72,
2774 RATE_48M_IEEE = 96,
2775 RATE_54M_IEEE = 108,
2776 RATE_60M_IEEE = 120,
2777 RATE_1M_IEEE = 2,
2778 RATE_2M_IEEE = 4,
2779 RATE_5M_IEEE = 11,
2780 RATE_11M_IEEE = 22,
2781 };
2782
2783 #define IL_CCK_BASIC_RATES_MASK \
2784 (RATE_1M_MASK | \
2785 RATE_2M_MASK)
2786
2787 #define IL_CCK_RATES_MASK \
2788 (IL_CCK_BASIC_RATES_MASK | \
2789 RATE_5M_MASK | \
2790 RATE_11M_MASK)
2791
2792 #define IL_OFDM_BASIC_RATES_MASK \
2793 (RATE_6M_MASK | \
2794 RATE_12M_MASK | \
2795 RATE_24M_MASK)
2796
2797 #define IL_OFDM_RATES_MASK \
2798 (IL_OFDM_BASIC_RATES_MASK | \
2799 RATE_9M_MASK | \
2800 RATE_18M_MASK | \
2801 RATE_36M_MASK | \
2802 RATE_48M_MASK | \
2803 RATE_54M_MASK)
2804
2805 #define IL_BASIC_RATES_MASK \
2806 (IL_OFDM_BASIC_RATES_MASK | \
2807 IL_CCK_BASIC_RATES_MASK)
2808
2809 #define RATES_MASK ((1 << RATE_COUNT) - 1)
2810 #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2811
2812 #define IL_INVALID_VALUE -1
2813
2814 #define IL_MIN_RSSI_VAL -100
2815 #define IL_MAX_RSSI_VAL 0
2816
2817 /* These values specify how many Tx frame attempts before
2818 * searching for a new modulation mode */
2819 #define IL_LEGACY_FAILURE_LIMIT 160
2820 #define IL_LEGACY_SUCCESS_LIMIT 480
2821 #define IL_LEGACY_TBL_COUNT 160
2822
2823 #define IL_NONE_LEGACY_FAILURE_LIMIT 400
2824 #define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2825 #define IL_NONE_LEGACY_TBL_COUNT 1500
2826
2827 /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2828 #define IL_RS_GOOD_RATIO 12800 /* 100% */
2829 #define RATE_SCALE_SWITCH 10880 /* 85% */
2830 #define RATE_HIGH_TH 10880 /* 85% */
2831 #define RATE_INCREASE_TH 6400 /* 50% */
2832 #define RATE_DECREASE_TH 1920 /* 15% */
2833
2834 /* possible actions when in legacy mode */
2835 #define IL_LEGACY_SWITCH_ANTENNA1 0
2836 #define IL_LEGACY_SWITCH_ANTENNA2 1
2837 #define IL_LEGACY_SWITCH_SISO 2
2838 #define IL_LEGACY_SWITCH_MIMO2_AB 3
2839 #define IL_LEGACY_SWITCH_MIMO2_AC 4
2840 #define IL_LEGACY_SWITCH_MIMO2_BC 5
2841
2842 /* possible actions when in siso mode */
2843 #define IL_SISO_SWITCH_ANTENNA1 0
2844 #define IL_SISO_SWITCH_ANTENNA2 1
2845 #define IL_SISO_SWITCH_MIMO2_AB 2
2846 #define IL_SISO_SWITCH_MIMO2_AC 3
2847 #define IL_SISO_SWITCH_MIMO2_BC 4
2848 #define IL_SISO_SWITCH_GI 5
2849
2850 /* possible actions when in mimo mode */
2851 #define IL_MIMO2_SWITCH_ANTENNA1 0
2852 #define IL_MIMO2_SWITCH_ANTENNA2 1
2853 #define IL_MIMO2_SWITCH_SISO_A 2
2854 #define IL_MIMO2_SWITCH_SISO_B 3
2855 #define IL_MIMO2_SWITCH_SISO_C 4
2856 #define IL_MIMO2_SWITCH_GI 5
2857
2858 #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2859
2860 #define IL_ACTION_LIMIT 3 /* # possible actions */
2861
2862 #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2863
2864 /* load per tid defines for A-MPDU activation */
2865 #define IL_AGG_TPT_THREHOLD 0
2866 #define IL_AGG_LOAD_THRESHOLD 10
2867 #define IL_AGG_ALL_TID 0xff
2868 #define TID_QUEUE_CELL_SPACING 50 /*mS */
2869 #define TID_QUEUE_MAX_SIZE 20
2870 #define TID_ROUND_VALUE 5 /* mS */
2871 #define TID_MAX_LOAD_COUNT 8
2872
2873 #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2874 #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2875
2876 extern const struct il_rate_info il_rates[RATE_COUNT];
2877
2878 enum il_table_type {
2879 LQ_NONE,
2880 LQ_G, /* legacy types */
2881 LQ_A,
2882 LQ_SISO, /* high-throughput types */
2883 LQ_MIMO2,
2884 LQ_MAX,
2885 };
2886
2887 #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2888 #define is_siso(tbl) ((tbl) == LQ_SISO)
2889 #define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2890 #define is_mimo(tbl) (is_mimo2(tbl))
2891 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2892 #define is_a_band(tbl) ((tbl) == LQ_A)
2893 #define is_g_and(tbl) ((tbl) == LQ_G)
2894
2895 #define ANT_NONE 0x0
2896 #define ANT_A BIT(0)
2897 #define ANT_B BIT(1)
2898 #define ANT_AB (ANT_A | ANT_B)
2899 #define ANT_C BIT(2)
2900 #define ANT_AC (ANT_A | ANT_C)
2901 #define ANT_BC (ANT_B | ANT_C)
2902 #define ANT_ABC (ANT_AB | ANT_C)
2903
2904 #define IL_MAX_MCS_DISPLAY_SIZE 12
2905
2906 struct il_rate_mcs_info {
2907 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2908 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2909 };
2910
2911 /**
2912 * struct il_rate_scale_data -- tx success history for one rate
2913 */
2914 struct il_rate_scale_data {
2915 u64 data; /* bitmap of successful frames */
2916 s32 success_counter; /* number of frames successful */
2917 s32 success_ratio; /* per-cent * 128 */
2918 s32 counter; /* number of frames attempted */
2919 s32 average_tpt; /* success ratio * expected throughput */
2920 unsigned long stamp;
2921 };
2922
2923 /**
2924 * struct il_scale_tbl_info -- tx params and success history for all rates
2925 *
2926 * There are two of these in struct il_lq_sta,
2927 * one for "active", and one for "search".
2928 */
2929 struct il_scale_tbl_info {
2930 enum il_table_type lq_type;
2931 u8 ant_type;
2932 u8 is_SGI; /* 1 = short guard interval */
2933 u8 is_ht40; /* 1 = 40 MHz channel width */
2934 u8 is_dup; /* 1 = duplicated data streams */
2935 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2936 u8 max_search; /* maximun number of tables we can search */
2937 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
2938 u32 current_rate; /* rate_n_flags, uCode API format */
2939 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
2940 };
2941
2942 struct il_traffic_load {
2943 unsigned long time_stamp; /* age of the oldest stats */
2944 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
2945 * slice */
2946 u32 total; /* total num of packets during the
2947 * last TID_MAX_TIME_DIFF */
2948 u8 queue_count; /* number of queues that has
2949 * been used since the last cleanup */
2950 u8 head; /* start of the circular buffer */
2951 };
2952
2953 /**
2954 * struct il_lq_sta -- driver's rate scaling ilate structure
2955 *
2956 * Pointer to this gets passed back and forth between driver and mac80211.
2957 */
2958 struct il_lq_sta {
2959 u8 active_tbl; /* idx of active table, range 0-1 */
2960 u8 enable_counter; /* indicates HT mode */
2961 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2962 u8 search_better_tbl; /* 1: currently trying alternate mode */
2963 s32 last_tpt;
2964
2965 /* The following determine when to search for a new mode */
2966 u32 table_count_limit;
2967 u32 max_failure_limit; /* # failed frames before new search */
2968 u32 max_success_limit; /* # successful frames before new search */
2969 u32 table_count;
2970 u32 total_failed; /* total failed frames, any/all rates */
2971 u32 total_success; /* total successful frames, any/all rates */
2972 u64 flush_timer; /* time staying in mode before new search */
2973
2974 u8 action_counter; /* # mode-switch actions tried */
2975 u8 is_green;
2976 u8 is_dup;
2977 enum ieee80211_band band;
2978
2979 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2980 u32 supp_rates;
2981 u16 active_legacy_rate;
2982 u16 active_siso_rate;
2983 u16 active_mimo2_rate;
2984 s8 max_rate_idx; /* Max rate set by user */
2985 u8 missed_rate_counter;
2986
2987 struct il_link_quality_cmd lq;
2988 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
2989 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2990 u8 tx_agg_tid_en;
2991 #ifdef CONFIG_MAC80211_DEBUGFS
2992 struct dentry *rs_sta_dbgfs_scale_table_file;
2993 struct dentry *rs_sta_dbgfs_stats_table_file;
2994 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2995 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2996 u32 dbg_fixed_rate;
2997 #endif
2998 struct il_priv *drv;
2999
3000 /* used to be in sta_info */
3001 int last_txrate_idx;
3002 /* last tx rate_n_flags */
3003 u32 last_rate_n_flags;
3004 /* packets destined for this STA are aggregated */
3005 u8 is_agg;
3006 };
3007
3008 /*
3009 * il_station_priv: Driver's ilate station information
3010 *
3011 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
3012 * in the structure for use by driver. This structure is places in that
3013 * space.
3014 *
3015 * The common struct MUST be first because it is shared between
3016 * 3945 and 4965!
3017 */
3018 struct il_station_priv {
3019 struct il_station_priv_common common;
3020 struct il_lq_sta lq_sta;
3021 atomic_t pending_frames;
3022 bool client;
3023 bool asleep;
3024 };
3025
3026 static inline u8
il4965_num_of_ant(u8 m)3027 il4965_num_of_ant(u8 m)
3028 {
3029 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
3030 }
3031
3032 static inline u8
il4965_first_antenna(u8 mask)3033 il4965_first_antenna(u8 mask)
3034 {
3035 if (mask & ANT_A)
3036 return ANT_A;
3037 if (mask & ANT_B)
3038 return ANT_B;
3039 return ANT_C;
3040 }
3041
3042 /**
3043 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
3044 *
3045 * The specific throughput table used is based on the type of network
3046 * the associated with, including A, B, G, and G w/ TGG protection
3047 */
3048 extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
3049
3050 /* Initialize station's rate scaling information after adding station */
3051 extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3052 u8 sta_id);
3053 extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3054 u8 sta_id);
3055
3056 /**
3057 * il_rate_control_register - Register the rate control algorithm callbacks
3058 *
3059 * Since the rate control algorithm is hardware specific, there is no need
3060 * or reason to place it as a stand alone module. The driver can call
3061 * il_rate_control_register in order to register the rate control callbacks
3062 * with the mac80211 subsystem. This should be performed prior to calling
3063 * ieee80211_register_hw
3064 *
3065 */
3066 extern int il4965_rate_control_register(void);
3067 extern int il3945_rate_control_register(void);
3068
3069 /**
3070 * il_rate_control_unregister - Unregister the rate control callbacks
3071 *
3072 * This should be called after calling ieee80211_unregister_hw, but before
3073 * the driver is unloaded.
3074 */
3075 extern void il4965_rate_control_unregister(void);
3076 extern void il3945_rate_control_unregister(void);
3077
3078 extern int il_power_update_mode(struct il_priv *il, bool force);
3079 extern void il_power_initialize(struct il_priv *il);
3080
3081 extern u32 il_debug_level;
3082
3083 #ifdef CONFIG_IWLEGACY_DEBUG
3084 /*
3085 * il_get_debug_level: Return active debug level for device
3086 *
3087 * Using sysfs it is possible to set per device debug level. This debug
3088 * level will be used if set, otherwise the global debug level which can be
3089 * set via module parameter is used.
3090 */
3091 static inline u32
il_get_debug_level(struct il_priv * il)3092 il_get_debug_level(struct il_priv *il)
3093 {
3094 if (il->debug_level)
3095 return il->debug_level;
3096 else
3097 return il_debug_level;
3098 }
3099 #else
3100 static inline u32
il_get_debug_level(struct il_priv * il)3101 il_get_debug_level(struct il_priv *il)
3102 {
3103 return il_debug_level;
3104 }
3105 #endif
3106
3107 #define il_print_hex_error(il, p, len) \
3108 do { \
3109 print_hex_dump(KERN_ERR, "iwl data: ", \
3110 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3111 } while (0)
3112
3113 #ifdef CONFIG_IWLEGACY_DEBUG
3114 #define IL_DBG(level, fmt, args...) \
3115 do { \
3116 if (il_get_debug_level(il) & level) \
3117 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3118 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3119 __func__ , ## args); \
3120 } while (0)
3121
3122 #define il_print_hex_dump(il, level, p, len) \
3123 do { \
3124 if (il_get_debug_level(il) & level) \
3125 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3126 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3127 } while (0)
3128
3129 #else
3130 #define IL_DBG(level, fmt, args...)
3131 static inline void
il_print_hex_dump(struct il_priv * il,int level,const void * p,u32 len)3132 il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3133 {
3134 }
3135 #endif /* CONFIG_IWLEGACY_DEBUG */
3136
3137 #ifdef CONFIG_IWLEGACY_DEBUGFS
3138 int il_dbgfs_register(struct il_priv *il, const char *name);
3139 void il_dbgfs_unregister(struct il_priv *il);
3140 #else
3141 static inline int
il_dbgfs_register(struct il_priv * il,const char * name)3142 il_dbgfs_register(struct il_priv *il, const char *name)
3143 {
3144 return 0;
3145 }
3146
3147 static inline void
il_dbgfs_unregister(struct il_priv * il)3148 il_dbgfs_unregister(struct il_priv *il)
3149 {
3150 }
3151 #endif /* CONFIG_IWLEGACY_DEBUGFS */
3152
3153 /*
3154 * To use the debug system:
3155 *
3156 * If you are defining a new debug classification, simply add it to the #define
3157 * list here in the form of
3158 *
3159 * #define IL_DL_xxxx VALUE
3160 *
3161 * where xxxx should be the name of the classification (for example, WEP).
3162 *
3163 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3164 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3165 * to send output to that classification.
3166 *
3167 * The active debug levels can be accessed via files
3168 *
3169 * /sys/module/iwl4965/parameters/debug
3170 * /sys/module/iwl3945/parameters/debug
3171 * /sys/class/net/wlan0/device/debug_level
3172 *
3173 * when CONFIG_IWLEGACY_DEBUG=y.
3174 */
3175
3176 /* 0x0000000F - 0x00000001 */
3177 #define IL_DL_INFO (1 << 0)
3178 #define IL_DL_MAC80211 (1 << 1)
3179 #define IL_DL_HCMD (1 << 2)
3180 #define IL_DL_STATE (1 << 3)
3181 /* 0x000000F0 - 0x00000010 */
3182 #define IL_DL_MACDUMP (1 << 4)
3183 #define IL_DL_HCMD_DUMP (1 << 5)
3184 #define IL_DL_EEPROM (1 << 6)
3185 #define IL_DL_RADIO (1 << 7)
3186 /* 0x00000F00 - 0x00000100 */
3187 #define IL_DL_POWER (1 << 8)
3188 #define IL_DL_TEMP (1 << 9)
3189 #define IL_DL_NOTIF (1 << 10)
3190 #define IL_DL_SCAN (1 << 11)
3191 /* 0x0000F000 - 0x00001000 */
3192 #define IL_DL_ASSOC (1 << 12)
3193 #define IL_DL_DROP (1 << 13)
3194 #define IL_DL_TXPOWER (1 << 14)
3195 #define IL_DL_AP (1 << 15)
3196 /* 0x000F0000 - 0x00010000 */
3197 #define IL_DL_FW (1 << 16)
3198 #define IL_DL_RF_KILL (1 << 17)
3199 #define IL_DL_FW_ERRORS (1 << 18)
3200 #define IL_DL_LED (1 << 19)
3201 /* 0x00F00000 - 0x00100000 */
3202 #define IL_DL_RATE (1 << 20)
3203 #define IL_DL_CALIB (1 << 21)
3204 #define IL_DL_WEP (1 << 22)
3205 #define IL_DL_TX (1 << 23)
3206 /* 0x0F000000 - 0x01000000 */
3207 #define IL_DL_RX (1 << 24)
3208 #define IL_DL_ISR (1 << 25)
3209 #define IL_DL_HT (1 << 26)
3210 /* 0xF0000000 - 0x10000000 */
3211 #define IL_DL_11H (1 << 28)
3212 #define IL_DL_STATS (1 << 29)
3213 #define IL_DL_TX_REPLY (1 << 30)
3214 #define IL_DL_QOS (1 << 31)
3215
3216 #define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3217 #define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3218 #define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3219 #define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3220 #define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3221 #define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3222 #define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3223 #define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3224 #define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3225 #define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3226 #define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3227 #define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3228 #define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3229 #define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3230 #define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3231 #define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3232 #define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3233 #define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3234 #define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3235 #define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3236 #define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3237 #define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3238 #define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3239 #define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3240 #define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3241 #define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3242 #define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3243 #define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3244 #define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3245
3246 #endif /* __il_core_h__ */
3247